RFK70N06 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 70A, 60V
  • r DS(ON) = 0.014Ω
  • Temperature Compensating PSPICE Model
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve
  • 175 oC Operating Temperature Symbol Packaging TO-204AE

Ordering Information

RFK70N06 TO-204AE RFK70N06 NOTE: When ordering, use the entire part number. G D S DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) Data Sheet September 1998

Absolute Maximum Ratings TC = 25oC Unless Otherwise Specified RFK70N06 UNITS Refer to Peak Current Curve A 150 1.0 W W/oC Maximum Temperature for Soldering CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V 60 - - V Gate to Source Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA 2-4V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS , VGS = 0V - - 1 µA VDS = 0.8 x Rated BVDSS , VGS = 0V, TC = 150oC- - 2 5 µA Gate to Source Leakage Current I GSS VGS =±20V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 70A, VGS = 10V (Figure 10) - - 0.014 Ω Turn-On Time t ON VDD = 30V, ID ≈ 70A, RL = 0.43Ω , VGS = 10V, RG = 2.5Ω (Figures 14, 17, 18) - - 125 ns Turn-On Delay Time t d(ON) -1 2- n s Rise Time t r -5 0- n s Turn-Off Delay Time t d(OFF) -4 0- n s Fall Time t f -1 5- n s Turn-Off Time t OFF - - 125 ns Total Gate Charge Q g(TOT) VGS = 0V to 20V V DD = 48V, ID ≈ 70A, R L = 0.68Ω , IG(REF) = 1.0mA (Figures 19, 20) - 185 215 nC Gate Charge at 10V Q g(10) VGS = 0V to 10V - 100 115 nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - 5.5 6.5 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) - 3000 - pF Output Capacitance C OSS - 900 - pF Reverse Transfer Capacitance C RSS - 300 - pF Thermal Resistance Junction to Case R θJC - - 1.0 oC/W Thermal Resistance Junction to Ambient R θJA -- 8 0 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 70A - - 1.5 V Reverse Recovery Time t rr ISD = 70A, dISD /dt = 100A/µs - - 125 ns NOTES: 2. Pulse test: pulse width≤ 300ms, duty cycle≤ 2%. 3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Temperature curve (Figure 3). RFK70N06

.SUBCKT RFK70N06 2 1 3 ; rev 1/16/97 CA 12 8 5.56e-9 CB 15 14 5.30e-9 CIN 6 8 2.63e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.18 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 11.45e-9 LSOURCE 3 7 4.60e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 4.66e-3 RLDRAIN 2 5 10 RGATE 9 20 1.21 RLGATE 1 9 114.5 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RLSOURCE 3 7 46 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.605 .MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5) .MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7) .MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6) .MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0) .ENDS NOTE: For further discussion of the PSPICE model, consultA New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temper- ature Options; written by William J. Hepp and C. Frank Wheatley. GATE LGATE RGATE EVTO 12 13 S1A S1B S2A S2B CA CB EGS EDS RIN CIN MOS1 MOS2 DBREAK EBREAK DBODY LDRAIN DRAIN RSOURCE LSOURCE SOURCE RBREAK RVTO VBAT IT VTO ESG DPLCAP 17 18 RDRAIN RLGATE RLDRAIN RLSOURCE RFK70N06

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RFK70N06