RFH12N35 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 12A, 350V and 400V
- r DS(ON) = 0.380Ω
- Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-218AC
Ordering Information
RFH12N35 TO-218AC RFH12N35 RFH12N40 TO-218AC RFH12N40 NOTE: When ordering, use the entire part number. G D S DRAIN SOURCE DRAIN GATE October 1998 File Number 1630.2Data Sheet
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFH12N35 RFH12N40 UNITS Maximum Temperature for Soldering 300 260 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V RFH12N35 350 - - V RFH12N40 400 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA, (Figure 8) 2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS, VGS = 0V - - 1 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC- - 2 5 µA Gate to Source Leakage Current I GSS VGS =±20V, VDS = 0V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 12A, VGS = 10V, (Figures 6, 7) - - 0.380 Ω Drain to Source On Voltage (Note 2) V DS(ON) ID = 12A, VGS = 10V - - 4.56 V Turn-On Delay Time t d(ON) ID ≈ 6A, VDD = 200V, RG = 50Ω, VGS = 10V, R L = 33Ω (Figures 10, 11, 12) -3 0 5 0 n s Rise Time t r - 105 150 ns Turn-Off Delay Time t d(OFF) - 480 750 ns Fall Time t f - 140 200 ns Input Capacitance C ISS VGS = 0V, VDS = 25V, f = 1MHz, (Figure 9) - - 3000 pF Output Capacitance C OSS - - 900 pF Reverse-Transfer Capacitance C RSS - - 400 pF Thermal Resistance Junction-to-Case R θJC RFH12N35, RFH12N40 - - 0.83 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD ISD = 6A - - 1.4 V Diode Reverse Recovery Time t rr ISD = 4A, dISD /dt = 100A/µs - 950 - ns NOTES: 2. Pulse test: pulse width≤ 300µs, duty cycle≤ 2%. 3. Repetitive rating: pulse width is limited by maximum junction temperature. RFH12N35, RFH12N40
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FIGURE 13. GATE CHARGE TEST CIRCUIT FIGURE 14. GATE CHARGE WAVEFORMS