RFG75N05E INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 75A, 50V
  • r DS(ON) = 0.008Ω
  • Electrostatic Discharge Rated
  • UIS Rating Curve (Single Pulse)
  • 175 oC Operating Temperature
  • Temperature Compensated PSPICE® Model Provided Symbol Packaging JEDEC STYLE TO-247

Ordering Information

RFG75N05E TO-247 RFG75N05E NOTE: When ordering, include the entire part number. G D S DRAIN (BOTTOM SIDE METAL) SOURCE DRAIN GATE July 1999Data Sheet File Number 2275.5

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG75N05E UNITS Curves Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS VGS = 0V, ID = 250µA (Figure 9) 50 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 8) 2.0 - 4.0 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS , VGS = 0V - - 1 µA VDS = 0.8 x Rated BVDSS , VGS = 0V, TC = 150oC- - 2 5 µA Gate to Source Leakage I GSS VGS =±20V - - ±100 nA Drain to Source on Resistance (Note 2) rDS(ON) VGS = 10V, ID = 75A (Figure 7) - - 0.008 Ω Turn On Time t (ON) VDD = 25V, ID ≈ 37.5A, R L = 0.67Ω , RG = 1.67Ω, VGS = 10V, (Figure 11) - - 125 ns Turn On Delay Time t d(ON) -1 7- n s Rise Time t r -7 5- n s Turn Off Delay Time t d(OFF) -7 0- n s Fall Time t f -1 7- n s Turn Off Time t (OFF) - - 125 ns Total Gate Charge (Gate to Source + Gate to Drain) Q g(TOT) VGS = 0, 20V V DD = 40V, ID = 75A, R L = 0.53Ω IG(REF) = 3.44mA (Figure 11) - - 400 nC Gate Charge at 10V Q g(10) VGS = 0, 10V - - 220 nC Threshold Gate Charge Q g(TH) VGS = 0, 2V - - 15 nC Junction to Case R θJC - - 0.625 oC/W Junction to Ambient R θJA -- 8 0 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 75A - - 1.5 V Diode Reverse Recovery Time t rr ISD = 75A, dISD /dt = 100A/µs - - 125 ns NOTES: 2. Pulse test: pulse width≤ 300µs, duty cycle≤ 2%. 3. Repetitive pulse: pulse width is limited by maximum junction temperature. 4. Refer to Intersil Application Notes AN9321 and AN9322. See Figure 4. RFG75N05E

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 PSpice Electrical Model .SUBCKT RFG75N05 2 1 3 ; rev 10/30/90 *Nominal Temperature = 25oC CA 12 8 8.98e-9 CB 15 14 8.81e-9 Cin 6 8 4.48e-9 DPLCAP 10 5 DPLCAPMOD Dbody 7 5 DBODYMOD Dbreak 5 11 DBREAKMOD Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Ebreak 11 7 17 18 58.4 EVTEMP 20 6 18 8 1 IT 8 17 1 Ldrain 2 5 e-10 Lgate 1 9 5e-9 Lsource 3 7 3e-9 Mos 16 6 8 8 MODMOD Rbreak 17 18 RBREAKMOD 1 Rdrain 5 16 RSOURCEMOD 3.07e-3 Rgate 9 20 1.2 Rin 6 8 1e9 Rsource 8 7 RSOURCEMOD 2.e-3 RVTEMP 18 19 RVTONEGMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2b 13 15 14 13 S2AMOD Vbat 8 19 DC 1 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.48 VOFF=-0.48) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.48 VOFF=-2.48) .MODEL S2AMOD VSWITCH (RON=1e=5 ROFF=0.1 VON=-2.25 VOFF=2.75) .MODEL S2ABMOD VSWITCH (RON=1e-5 ROFF=0.1 VON =2.75 VOFF=-2.25) .MODEL DBODYMOD D (IS=2.23e-12 RS=249e-3 TRS1=2.5e-3 CJO=7.55e-9 TT=4e-8) .MODEL DBREAKMOD D (RS=8e-2 TRS1=2.5e-3) .MODEL DPLCAPMOD D (IS=1e-30 N=10 CJO=2.14e-9) .MODEL RBREAKMOD RES (TC1=9.5e-4 TC2=-1.17e-6) .MODEL RSOURCEMOD RES (TC1=5.2e-3 TC2=1.37e-5) .MODEL RVTONEGMOD RES (TC1=-3.78e-3 TC2=-7.51e-7) .MODEL MODMOD NMOS (VTO=3.48 N=10 IS=1e-30 KP=78.5 TOX=1 L=1u W1u) .ENDS GATE RGATE EVTO 229 12 13 S1A S1B S2A S2B CA CB EGS EDS CIN DBREAK EBREAK DBODY DRAIN RSOURCE SOURCE RBREAK RVTEMP VBAT IT ESG DPLCAP 17 18 MOS LSOURCE LDRAIN LGATE RDRAIN RIN RFG75N05E