RFG60P05E INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 60A, 50V
  • r DS(ON) = 0.030Ω
  • Temperature Compensating PSPICE® Model
  • 2kV ESD Rated
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve
  • 175 oC Operating Temperature
  • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC STYLE TO-247

Ordering Information

RFG60P05E TO-247 RFG60P05E NOTE: When ordering, use the entire part number. D G S DRAIN (BOTTOM SIDE METAL) SOURCE DRAIN GATE Data Sheet July 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG60P05E UNITS Refer to Peak Current Curve A 215 1.43 W W/oC MIL-STD-883, Category B(2) 2k V Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V -50 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA - 2-- 4V Zero Gate Voltage Drain Current I DSS VDS = -50V, VGS = 0V - - -1 µA VDS = 0.8 x Rated BVDSS , TC = 150oC - - -25 µA Gate to Source Leakage Current I GSS VGS =±20V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 60A, VGS = -10V (Figure 9) - - 0.030 Ω Turn-On Time t (ON) VDD = -25V, ID = 30A, RL = 0.83Ω , VGS = -10V, RGS = 2.5Ω (Figure 13) - - 125 ns Turn-On Delay Time t d(ON) -2 0- n s Rise Time t r -6 0- n s Turn-Off Delay Time t d(OFF) -6 5- n s Fall Time t F -2 0- n s Turn-Off Time t (OFF) - - 125 ns Total Gate Charge Q g(TOT) VGS = 0V to -20V V DD = -40V, ID = 60A, R L = 0.67Ω Ig(REF) = -4mA - - 450 nC Gate Charge at 10V Q g(-10) VGS = 0V to -10V - - 225 nC Threshold Gate Charge Q g(TH) VGS = 0V to -2V - - 15 nC Input Capacitance C ISS VDS = -25V, VGS = 0V, f = 1MHz (Figure 12) - 7200 - pF Output Capacitance C OSS - 1700 - pF Reverse Transfer Capacitance C RSS - 325 - pF Thermal Resistance, Junction to Case R θJC - - 0.70 oC/W Thermal Resistance, Junction to Ambient R θJA -- 3 0 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) VSD ISD = -60A - - -1.75 V Diode Reverse Recovery Time t RR ISD = -60A, dISD /dt = 100A/µs - - 200 ns NOTE: 2. Pulse test: pulse width≤ 300µs maximum, duty cycle≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). RFG60P05E

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

175 T C–

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

0.75 BVDSS

0.50 BVDSS

0.25 BVDSS

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com .SUBCKT RFG60P05E 2 1 3; REV 9/20/94 CA 12 8 1.01e-8 CB 15 14 1.05e-8 CIN 6 8 6.9e-9 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -76.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 7.9e-9 LSOURCE 3 7 4.18e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 12.83e-3 RGATE 9 20 1.5 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.25e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.83 .MODEL DBKMOD D (RS = 1.11e-1 TRS1 = 1.34e-3 TRS2 = 4.46e-12) .MODEL DPLCAPMOD D (CJO = 15e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -3.71 KP = 31.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.42e-4 TC2 = 0) .MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 7.69e-6) .MODEL RVTOMOD RES (TC1 = -3.39e-3 TC2 = 1.07e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.6 VOFF = 2.6) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.6 VOFF = 4.6) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.16 VOFF = -3.84) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.84 VOFF = 1.16) .ENDS For further discussion of the PSPICE model, consultA New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. MOS1 DPLCAP RDRAIN DBREAK LDRAIN DRAIN SOURCE LSOURCE DBODY RBREAK RVTO VBAT 19IT RSOURCE EBREAK MOS2 EDSEGS RIN CIN VTO ESG S1A S2A S2BS1B CBCA EVTORGATEGATE LGATE 1817 2091 12 15 13 + + - RFG60P05E