RFF70N06 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 25A†, 60V
- r DS(ON) = 0.025Ω
- Temperature Compensating PSPICE™ Model
- Peak Current vs Pulse Width Curve
- UIS Rating Curve
- 150 oC Operating Temperature
- Reliability Screened Current is limited by the package capability. Symbol Packaging JEDEC TO-254AA CAUTION: Berylia Warning per MIL-S-19500. Refer to package specifications.
Ordering Information
RFF70N06 TO-254AA RFF70N06 NOTE: When ordering, use the entire part number. D G S GATE SOURCE DRAINPACKAGE TAB (ISOLATED) Data Sheet March 1999
Absolute Maximum RatingsTC = 25oC, Unless Otherwise Specified RFF70N06 UNITS 25 (Note 2) Refer to Peak Current Curve A 100 0.80 W W/oC Maximum Temperature for Soldering CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. 2. Current is limited by the package capability. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V 60 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA 2.0 3.0 4.5 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS, VGS = 0V - - 25 µA VDS = 0.8 x Rated BVDSS ,VGS = 0V, TC = 125oC - - 250 µA Gate to Source Leakage Current I GSS VGS =±20V, TC = 125oC- - ±100 µΑ Drain to Source On Resistance (Note 3) rDS(ON) ID = 25A, VGS = 10V - - 0.025 Ω Turn-On Time t ON VDD = 30V, ID ≈ 25A, RL = 1.2Ω , VGS = 10V, RGS = 2.35Ω (Figures 13, 16, 17) - - 240 ns Turn-On Delay Time t d(ON) -2 5 7 0 n s Rise Time t r - 70 170 ns Turn-Off Delay Time t d(OFF) - 60 150 ns Fall Time t f -2 5 6 5 n s Turn-Off Time t OFF - - 215 ns Total Gate Charge Q g(TOT) VGS = 0 to 20V VDD = 30V, ID = 25A, R L = 1.2Ω IG(REF) = 1.0mA (Figures 18, 19) - - 260 nC Gate Charge at 10V Q g(10) VGS = 0 to 10V - - 145 nC Threshold Gate Charge Q g(TH) VGS = 0 to 2V - - 7 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 3100 - pF Output Capacitance C OSS - 900 - pF Reverse Transfer Capacitance C RSS - 300 - pF Thermal Resistance Junction to Case R θJC - - 1.25 oC/W Thermal Resistance Junction to Ambient RθJA -- 4 8 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 25A - 1.1 1.5 V Diode Reverse Recovery Time t rr ISD = 25A, dISD /dt = 100A/µs - 190 300 ns NOTES: 3. Pulse test: pulse width≤ 300ms, duty cycle≤ 2%. 4. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve Figure 3). RFF70N06
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
150 T C
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
- TX/TXV Equivalent - Standard Data Package
- TX/TXV Equivalent - Optional Data Package
SUBCKT RFF70N06 2 1 3 ; rev 5/29/95 CA 12 8 5.20e-9 CB 15 14 5.20e-9 CIN 6 8 2.80e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 68.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRESH 6 21 19 8 1 EZTEMPCO 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 6.04e-9 LSOURCE 3 7 2.24e-9 MOS1 16 6 8 8 MSTRONG M = 0.99 MOS2 16 21 8 8 MWEAK M = 0.01 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 8.03e-3 RGATE 9 20 1 RIN 6 8 1e9 RLDRAIN 2 5 10 RLGATE 1 9 60.4 RLSOURCE 3 7 22.4 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 7.20e-3 RTHRESH 22 8 RTHRESMOD 1 RZTEMPCO 18 19 RZTEMPCOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),3))} .MODEL DBREAKMOD D (RS = 88e-3 TRS1 = 1.50e-3 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 2.60e-9 IS = 1e-30 N = 10 M=0.7) .MODEL MSTRONG NMOS (VTO = 3.85 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u) .MODEL MWEAK NMOS (VTO = 3.09 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 7e-3 TC2 = 1.90e-5) .MODEL RDSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSCLMOD RES (TC1 = 0 TC2 = 0) .MODEL RTHRESHMOD RES (TC1 = -3.10e-3 TC2 = -1e-5) .MODEL RZTEMPCOMOD RES (TC1 = -2.25e-3 TC2 = -5.75e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.0 VOFF= -4.0) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -6.0) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 2.0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.0 VOFF= -2.0) .ENDS NOTE: For further discussion of the PSPICE model, consultA New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. GATE LGATE RGATE EZTEMPCO 12 13 S1A S1B S2A S2B CA CB EGS EDS RIN CIN MOS1 MOS2 DBREAK EBREAK DBODY LDRAIN DRAIN RSOURCE LSOURCE SOURCE RBREAK RZTEMPCO VBAT IT EVTHRESH ESG DPLCAP 17 18 + + 209 RLGATE RLSOURCE RLDRAIN RTHRESH RDRAIN ESCL RSCL1 RSCL2 51 RFF70N06
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table) Delta Tests and Limits (JANTX/JANTXV Equivalent) PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS =±20V, TC = 25oC ±20 (Note 5) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value, TC = 25oC ±25 (Note 5) µA On Resistance rDS(ON) TC = 125oC at Rated ID ±20% (Note 6) Ω Gate Threshold Voltage VGS(TH) ID = 1.0mA, TC = 25oC ±20% (Note 6) V NOTES: 5. Or 100% of Initial Reading (whichever is greater). 6. Of Initial Reading. Screening Information TEST JANTX/JANTXV EQUIVALENT Gate Stress V GS = 30V, t = 250µs Pind Optional PDA 10% Pre Burn-In Test (Note 7) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25 oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 7) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A V DS = 80% of Rated Value, TA = 150oC, Time = 168 hours Final Electrical Tests (Note 7) MIL-S-19500, Group A, Subgroup 2 NOTE: 7. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Safe Operating Area SOA VDS = 48V, t = 10ms 4.8 A Unclamped Inductive Switching IAS VGS(PEAK) = 15V, L = 0.1mH 75 A Thermal Response ΔVSD tH = 100ms; VH = 25V, IH = 4A 220 mV Thermal Impedance ΔVSD tH = 500ms; VH = 25V, IH = 4A 330 mV RFF70N06