RFF60P06 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 25A, 60V
- r DS(ON) = 0.030Ω
- Temperature Compensating PSPICE® Model
- Peak Current vs Pulse Width Curve
- UIS Rating Curve
- 150 oC Operating Temperature
- Reliability Screened Symbol Packaging JEDEC TO-254AA CAUTION: Berylia Warning per MIL-S-19500. Refer to package specifications.
Ordering Information
RFF60P06 TO-254AA RFF60P06 NOTE: When ordering, use the entire part number. D G S GATE SOURCE DRAINPACKAGE TAB (ISOLATED) Data Sheet September 1998
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFF60P06 UNITS 25 (Note 5) Refer to Peak Current Curve A 125 1.0 W W/oC Maximum Temperature for Soldering CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V -60 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA -2.0 -3.0 -4.5 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS ,VGS = 0V - - -25 µA VDS = 0.8 x Rated BVDSS , VGS = 0V, TC = 125oC - - -250 µA Gate to Source Leakage Current I GSS VGS =±20V, TC = 125oC- - ±100 µA Drain to Source On Resistance (Note 2) rDS(ON) ID = 25A, VGS = -10V, (Figure 9) - - 0.030 Ω Turn-On Time t ON VDD = -30V, ID = 25A, RL = 1.2Ω , VGS = -10V R G = 2.35Ω (Figures 13, 16, 17) - - 195 ns Turn-On Delay Time t d(ON) -2 57 0 n s Rise Time t r - 50 125 ns Turn-Off Delay Time t d(OFF) - 80 200 ns Fall Time t f -3 07 5 n s Turn-Off Time t OFF - - 275 ns Total Gate Charge Q g(TOT) VGS = 0 to -20V V DD = -30V, ID = 25A, R L = 1.2Ω IG(REF) = -4.2mA (Figures 18, 19) - - 450 nC Gate Charge at -10V Q g(-10) VGS = 0 to -10V - - 225 nC Threshold Gate Charge Q g(TH) VGS = 0 to -2V - - 15 nC Input Capacitance C ISS VDS = -25V, VGS = 0V f = 1MHz - 7200 - pF Output Capacitance C OSS - 1800 - pF Reverse Transfer Capacitance C RSS - 400 - pF Thermal Resistance Junction to Case R θJC - - 1.0 oC/W Thermal Resistance Junction to Ambient R θJA --4 8 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD ISD = -25A - -1.1 -1.5 V Diode Reverse Recovery Time t rr ISD = -25A, dISD /dt = -100A/µs - 130 200 ns NOTES: 2. Pulse test: pulse width≤ 300µs, duty cycle≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) 4. Current is limited by package capability. RFF60P06
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
150 T C–
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
- TX/TXV Equivalent - Standard Data Package
- TX/TXV Equivalent - Optional Data Package
.SUBCKT RFF60P06 2 1 3 REV 9/20/94 CA 12 8 1.01e-8 CB 15 14 1.05e-8 CIN 6 8 6.9e-9 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 5 11 17 18 -76.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 7.9e-9 LSOURCE 3 7 4.18e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 12.83e-3 RGATE 9 20 1.55 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.25e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.83 .MODEL DBKMOD D (RS=1.11e-1 TRS1=1.34e-3 TRS2=4.46e-12) .MODEL DPLCAPMOD D (CJO=15e-10 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.71 KP=31.5 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=9.42e-4 TC2=0) .MODEL RDSMOD RES (TC1=5.85e-3 TC2=7.69e-6) .MODEL RVTOMOD RES (TC1=-3.39e-3 TC2=1.07e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.6 VOFF=2.6) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.6 VOFF=4.6) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.16 VOFF=-3.84) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.84 VOFF=1.16) .ENDS NOTE: For further discussion of the PSPICE model consultA New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. MOS1 DPLCAP RDRAIN DBREAK LDRAIN DRAIN LSOURCE DBODY RBREAK RVTO VBAT 19IT RSOURCE EBREAK MOS2 EDSEGS RIN CIN VTO ESG S1A S2A S2BS1B CBCA EVTORGATEGATE LGATE 1817 2091 12 15 136 + - RFF60P06
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANTX/JANTXV Equivalent) PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current I GSS VGS =±20V, TC = 25oC ±20 (Note 4) nA Zero Gate Voltage Drain Current I DSS VDS = 80% Rated Value, TC = 25oC ±25 (Note 4) µA On Resistance r DS(ON) TC = 125oC at Rated ID ±20% (Note 5) Ω Gate Threshold Voltage V GS(TH) ID = 1.0mA, TC = 25oC ±20% (Note 5) V NOTES: 5. Or 100% of Initial Reading (whichever is greater). 6. Of Initial Reading. Screening Information TEST JANTX/JANTXV EQUIVALENT Gate Stress V GS = -30V, t = 250µs Pind Optional PDA 10% Pre Burn-In Test (Note 1) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25 oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 6) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A V DS = 80% of Rated Value, TA = 150oC, Time = 168 hours Final Electrical Tests (Note 6) MIL-S-19500, Group A, Subgroup 2 NOTE: 7. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Safe Operating Area SOA V DS = -48V, t = 10ms 8.0 A Unclamped Inductive Switching I AS VGS(PEAK) = -15V, L = 0.1mH 75 A Thermal Response ΔVSD tH = 100ms; VH = 25V, IH = 4A 142 mV Thermal Impedance ΔVSD tH = 500ms; VH = 25V, IH = 4A 182 mV RFF60P06