RFD14N05L ONSEMI | Alldatasheet

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©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM Rev. C0 RFD14N05L, RFD14N05LSM N-Channel Logic Level Power MOSFET

50 V, 14 A, 100 mΩ

These are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V-5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA09870.

Features

  • 14A, 50V r DS(ON) = 0.100Ω  Temperature Compensating PSPICE ® Model  Can be Driven Directly from CMOS, NMOS, and TTL Circuits  Peak Current vs Pulse Width Curve  UIS Rating Curve 1 7 5oC Operating Temperature  Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-251AA JEDEC TO-252AA

Ordering Information

RFD14N05LSM TO-252AA 14N05L RFD14N05LSM9A TO-252AA 14N05L NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A. G D S SOURCE DRAIN (FLANGE) GATE DRAIN GATE SOURCE DRAIN (FLANGE) Data Sheet October 2013

©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM Rev. C0 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD14N05L, RFD14N05LSM, RFD14N05LSM9A UNITS Refer to Peak Current Curve A 0.32 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, Figure 13 50 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, Figure12 1 - 2 V Zero Gate Voltage Drain Current IDSS VDS = 40V, VGS = 0V - - 1 µA VDS = 40V, VGS = 0V, TC = 150oC- - 5 0 µA Gate to Source Leakage Current IGSS VGS = ±10V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 14A, VGS = 5V, Figures 9, 11 - - 0.100 Ω Turn-On Time t(ON) VDD = 25V, ID = 7A, RL = 3.57Ω, VGS = 5V, RGS = 0.6Ω --6 0n s Turn-On Delay Time td(ON) -1 3 - n s Rise Time tr -2 4 - n s Turn-Off Delay Time td(OFF) -4 2 - n s Fall Time tf -1 6 - n s Turn-Off Time t(OFF) - - 100 ns Total Gate Charge Qg(TOT) VGS = 0V to 10V V DD = 40V, ID = 14A, RL = 2.86Ω Figures 20, 21 - - 40 nC Gate Charge at 5V Qg(5) VGS = 0V to 5V - - 25 nC Threshold Gate Charge Qg(TH) VGS = 0V to 1V - - 1.5 nC Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz Figure 14 - 670 - pF Output Capacitance COSS - 185 - pF Reverse Transfer Capacitance CRSS -5 0 - p F Thermal Resistance Junction to Case RθJC - - 3.125 oC/W Thermal Resistance Junction to Ambient RθJA TO-251 - - 100 oC/W RθJA TO-252 - - 100 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD ISD = 14A - - 1.5 V Diode Reverse Recovery Time trr ISD = 14A, dISD/dt = 100A/µs - - 125 ns NOTES: 2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). RFD14N05L, RFD14N05LSM

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

2.5 PULSE DURATION = 80µs

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

0.75 BVDSS

0.50 BVDSS

0.25 BVDSS

©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM Rev. C0 .SUBCKT RFP14N05L 2 1 3 ; rev 9/15/94 CA 12 8 1.464e-9 CB 15 14 1.64e-9 CIN 6 8 6.17e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.68e-9 LSOURCE 3 7 5.35e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 33.1e-3 RGATE 9 20 5.85 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 14.3e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.485 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))} .MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5) .MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6) .MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5) .MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6) .MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley. GATE LGATE RGATE EVTO 12 13 S1A S1B S2A S2B CA CB EGS EDS RIN CIN MOS1 MOS2 DBREAK EBREAK DBODY LDRAIN DRAIN RSOURCE LSOURCE SOURCE RBREAK RVTO VBAT IT VTO ESG DPLCAP 7 3 17 18 RDRAIN ESCL RSCL1 RSCL2 51 RFD14N05L, RFD14N05LSM

©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM Rev. C0 RFD14N05L, RFD14N05LSM TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESI GN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIO NS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used here in: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms AccuPower™ AX-CAP®* BitSiC™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED Dual Cool™ EcoSPARK® EfficentMax™ ESBC™ Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FETBench™ FPS™ F-PFS™ FRFET Global Power ResourceSM GreenBridge™ Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ Marking Small Speakers Sound Louder and Better™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™ mWSaver OptoHiT™ OPTOLOGIC OPTOPLANAR® PowerTrench® PowerXS™ Programmable Active Droop™ QFET QS™ Quiet Series™ RapidConfigure™ Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ Solutions for Your Success™ SPM STEALTH™ SuperFET SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS SyncFET™ Sync-Lock™ TinyBoost® TinyBuck® TinyCalc™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TranSiC™ TriFault Detect™ TRUECURRENT SerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ VisualMax™ VoltagePlus™ XS™ Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. 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