RFB915B

MICRF620 MICREL | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• “Drop in” RF solution
• Small size: 11.5x14.1mm
• RF tested
• Low Power
• Surface Mountable
• Tape & Reel
• Digital Bit Synchronizer
• Received Signal Strength Indicator (RSSI)
• RX and TX power management
• Power down function
• Register read back function

Applications

• Telemetry
• Remote metering
• Wireless controller
• Remote data repeater
• Remote control systems
• Wireless modem
• Wireless security system

Micrel, Inc. MICRF620 December 2005 M9999-120205

Contents

Micrel, Inc. MICRF620 December 2005 M9999-120205 VCO Bias RSSI DataIXO DataClk LDout ANT LNA Sallen-key Sallen-key Main filter Main filter IFAMP PA DIV 2 IFAMP LO-Buffer PA-buffer Frequency Synthesiser Demodulator Clock recovery Modulator Deviation control RSSI XCO Control logic CS IO SCLK RadioWire® RF Module Selection Guide Device Frequency Range Data Rate Receive Supply Voltage Transmit Modulation Type Package MICRF600 902-928 MHz <20 kbps 13.5 mA 2.0-2.5 v 28 mA FSK 11.5x14.1 mm MICRF610 868-870 MHz <15 kbps 13.5 mA 2.0-2.5 v 26 mA FSK 11.5x14.1 mm MICRF620 410-450 MHz <20 kbps 12.0 mA 2.0-2.5 v 23 mA FSK 11.5x14.1 mm RFB433B 430-440 MHz 19.2 kbaud 8 mA 2.5-3.4 V 42 mA FSK 1”x1” RFB868B 868-870 MHz 19.2 kbaud 10 mA 2.5-3.4 V 50 mA FSK 1”x1” RFB915B 902-928 MHz 19.2 kbaud 10 mA 2.5-3.4 V 50 mA FSK 1”x1”

Ordering Information

Junction Temp. Range(1) Package MICRF620 TR –20° to +75°C 11.5 x 14.1mm Block Diagram MICRF620

Micrel, Inc. MICRF620 December 2005 M9999-120205 Pin Configuration MICRF620 TR 11.5 x 14.1 mm (Top view) Pin Description Pin Number Pin Name Type Pin Function NC Not connected NC Not connected CS I Chip select, three wire programming interface SClk I Clock, three wire programming interface IO I/O Data, three wire programming interface DataIXO I/O Data receive/transmit, bi-directional DataClk O Data clock receive/transmit LD O Lock detect RSSI O Receive signal strength indicator GND Ground GND Ground GND Ground ANT I/O RF In/Out GND Ground VDD VDD (2.0-2.5V) GND Ground

Micrel, Inc. MICRF620 December 2005 M9999-120205 Absolute Maximum Ratings(1) Operating Ratings(2)

Electrical Characteristics

fRF = 434MHz, Data rate = 20kbps, VDD = 2.5V; TA = 25°C, bold values indicate –20°C< TA < +75°C, unless noted. Parameter Condition Min Typ Max Units Power Supply 2.0 2.5 V Power Down Current 0.3 µA Standby Current 280 µA VCO and PLL Section Tunable with on-chip cap bank MHz Crystal Oscillator Frequency Tuning range -30 +40 ppm Crystal Initial Tolerance -10 +10 ppm Crystal Temperature Tolerance -10 +10 ppm Rx 433.4MHz – Rx 434MHz 300 µs Rx – Tx, same frequency, measured @ frequency offset < 10kHz 200 µs Tx – Rx, same frequency, time to good data 350 µs Standby – Rx, 1.1 ms Switch Time Standby – Tx 1.1 ms Crystal Oscillator Start-Up Time XCO_tune=13 750 µs Transmit Section RLOAD = 50Ω, Pa2_0: 111 dBm Output Power RLOAD = 50Ω, Pa2_0: 001 dBm Over temperature range dB Output Power Tolerance Over power supply range dB RLOAD = 50Ω, PA2_0: 111 mA Tx Current Consumption RLOAD = 50Ω, PA2_0: 001 mA Tx Current Consumption Variation RLOAD = 50Ω, PA2_0: 111 2.5 mA Binary FSK Frequency Separation (5) Limited by receiver BW 400 kHz Data Rate NRZ kbps Occupied bandwidth 19.2kbps, β = 9 (±85kHz), -36dBm (RBW=10kHz) kHz Harmonics 434 -36 dBm Spurious Emission in Restricted bands < 1GHz -54 dBm Spurious Emission < 1GHz -36 dBm Spurious Emission > 1GHz ETSI EN300 220 -30 dBm

Micrel, Inc. MICRF620 December 2005 M9999-120205 Parameter Condition Min Typ Max Units Receive Section All functions on mA LNA bypass 10.3 mA Rx Current Consumption Switch cap filter bypass with LNA 9.6 mA Rx Current Consumption Variation Over temperature mA 2.4 kbps, β = 16, SC=50 kHz -110 dBm 4.8 kbps, β = 16, SC=50 kHz -109 dBm 4.8 kbps, β = 4, SC=31 kHz -108 dBm 19.2 kbps, β =8, SC=200 kHz -107 dBm Receiver Sensitivity 19.2 kbps, β =2, SC=67 kHz -105 dBm Receiver Maximum Input Power 19.2 kbps, β = 8 +10 dBm Over temperature dB Receiver Sensitivity Tolerance Over power supply range dB Receiver Bandwidth 350 kHz Co-Channel Rejection 19.2 kbps, β = 6, SC=133 kHz dB 200 kHz spacing TBD 500 kHz spacing TBD Adjacent Channel Rejection

1 MHz spacing

Offset ±1MHz dB Offset ±2MHz dB Offset ±5MHz dB Offset ±10MHz dB Blocking Desired signal: 19.2 kbps, β =6, 3dB above sens, SC=133 kHz Offset ±30MHz dB 1dB Compression -35 dB Input IP3 2 tones with 1MHz separation -25 dBm Input IP2 TBD dBm LO Leakage -90 dBm Spurious Emission < 1GHz -57 dBm Spurious Emission > 1GHz ETSI 300-220 -47 dBm Input Impedance 37+j18 Ω RSSI Dynamic Range dB Pin = -100 dBm 1.1 V RSSI Output Range Pin = -60 dBm 2.0 V Digital Inputs/Outputs Logic Input High 0.7VDD VDD V Logic Input Low 0.3VDD V Clock/Data Frequency(4) MHz Clock/Data Duty Cycle(4) Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 4. Guaranteed by design.

registers are carried out at a rate determined by the user. bus, sharing clock and data lines with other devices. power down mode after a battery reset.

0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5

Table 1. Control Registers in MICRF620

followed by a load-signal to activate the new setting. the address of the 1st control register to write to). registers. This bit is called the R/W bit. The values to write into the control register(s). A 7-bit field, ranging from 0 to 21. MSB is written first. Table 2. Writing to the Control Registers line before the negative edge. Refer to figures below. complete the write-sequence. registers have non-incremental addresses. example: Change from receive mode to power-down. Table 3. “Address” and “R/W bit” together make 1 octet. octets are clocked into the MICRF620. Figure 1. How to write to a single Control Register value of the R/W bits is always “0” for writing. After a power-on, all writable registers must be written. specific sections of this document for actual values. Table 4. “Address” and “R/W bit” together make 1 octet. In total, 23 octets are clocked into the MICRF620.

Micrel, Inc. MICRF620 December 2005 M9999-120205 Programming Summary Use CS, SCLK, and IO to get access to the control registers in MICRF620. SCLK is user-controlled. Write to the MICRF620 at positive edges (MICRF620 reads at negative edges). Read from the MICRF620 at negative edges (MICRF620 writes at positive edges) After power-on: Write to the complete set of control registers. Address field is 7 bits long. Enter msb first. R/W bit is 1 bit long (“1” for read, “0” for write) Address and R/W bit together make 1 octet All control registers are 8 bits long. Enter/read msb in every octet first. Always write 8 bits to/read 8 bits from a control register. This is the case for registers with less than 8 used programming bits as well. Writing: Bring CS high, write address and R/W bit followed by the new values to fill into the addressed control register(s) and bring CS low for loading, i.e., activation of the new control register values. Reading: Bring CS high, write address and R/W bit, set IO as an input, read present contents of the addressed control register(s), bring CS low and set IO an output. Frequency Synthesizer A6…A0 0001010 A0_5 A0_4 A0_3 A0_2 A0_1 A0_0 0001011 N0_11 N0_10 N0_9 N0_8 0001100 N0_7 N0_6 N0_5 N0_4 N0_3 N0_2 N0_1 N0_0 0001101 M0_11 M0_10 M0_9 M0_8 0001110 M0_7 M0_6 M0_5 M0_4 M0_3 M0_2 M0_1 M0_0 0001111 A1_5 A1_4 A1_3 A1_2 A1_1 A1_0 0010000 N1_11 N1_10 N1_9 N1_8 0010001 N1_7 N1_6 N1_5 N1_4 N1_3 N1_2 N1_1 N1_0 0010010 M1_11 M1_10 M1_9 M1_8 0010011 M1_7 M1_6 M1_5 M1_4 M1_3 M1_2 M1_1 M1_0 The frequency synthesizer consists of a voltage-controlled oscillator (VCO), a crystal oscillator, phase select prescaler, programmable frequency dividers and a phase- detector. The length of the N, M, and A registers are 12, 12 and 6 respectively. The N, M, and A values can be calculated from the formula: A N f A N f M f f RF VCO XCO PhD 1 ≤ A < N PhD: Phase detector comparison frequency fXCO: Crystal oscillator frequency fVCO: Voltage controlled oscillator frequency fRF: Input/output RF frequency There are two sets of each of the divide factors (i.e. A0 and A1). Storing the ‘0’ and the ‘1’ frequency in the 0- and the 1 registers respectively, does the 2-FSK. The receive frequency must be stored in the ‘0’ registers. Crystal Oscillator (XCO) Adr 0001001 ‘0’ ‘1’ ‘1’ XCOtune4 XCOtune3 XCOtune2 XCOtune1 XCOtune0 The crystal oscillator is a reference for the RF output frequency and the LO frequency in the receiver. It is possible to tune the internal crystal oscillator by switching in internal capacitance using 5 tune bits XCOtune4 – XCOtun0. The benefit of tuning the crystal oscillator is to eliminate the initial tolerance and the tolerance over temperature and aging. By using the crystal tuning feature the noise bandwidth of the receiver can be reduced and a higher sensitivity is achieved. When XCOtune4 – XCOtune0 = 0 no internal capacitors are connected to the crystal pins. When XCOtune4 – XCOtune0 = 1 all of the internal capacitors are connected to the crystal pins. Figure 5 shows the tuning range.

0000111 BitRate_clkS1 BitRate_clkS0

synchronized clock will be set out on pit DataClk. “USER” sample data on falling edge in receive mode. Figure 7. Data interface in Receive Mode on rising edge in transmit mode. Figure 8. Data interface in Transmit Mode noise amplifier (LNA) that drives a quadrature mixer pair.

incoming signal prior to the frequency conversion process. 2.0V to 2.5V variation in power supply. The LNA can be bypassed by setting bit LNA_by to ‘1’. front-end gain with the LNA bypassed is about 9-10dB. The mixers have a gain of about 10dB at 434MHz. channel signals, and it also works as an anti-aliasing filter. the SC filter to filter the clock frequency. Figure 9. RSSI Voltage The RSSI can be used as a signal presence indicator. When a RF signal is received, the RSSI output increases. a sleep mode configuration to conserve battery life.

compensation for crystal temperature drift and aging. Table 8. FEEC Control Bit

1. To calculate the negative value, a two’s

and this mode gives the best accuracy.

0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4

Micrel, Inc. MICRF620 December 2005 M9999-120205 A bit synchronizer can be enabled in receive mode by selecting the synchronous mode (Sync_en=1). The DataClk pin will output a clock with twice the frequency of the bit rate (a bit rate of 20 kbit/sec gives a DataClk of 20 kHz). A received symbol/bit on DataIXO will be output on rising edge of DataClk. The micro controller should therefore sample the symbol/bit on falling edge of DataClk. The bit synchronizer uses a clock that needs to be programmed according to the bit rate. The clock frequency should be 16 times the actual bit rate (a bit rate of 20 kbit/sec needs a bit synchronizer clock with frequency of 320 kHz). The clock frequency is set by the following formula: lkS) -BITSYNC_c XCO K BITSYNC_CL Refclk_K f f where fBITSYNC_CLK: The bit synchronizer clock frequency (16 times higher than the bit rate) fXCO: Crystal oscillator frequency Refclk_K: 6 bit divider, values between 1 and 63 BitSync_clkS: Bit synchronizer setting, values between 0 and 7 Refclk_K is also used to derive the modulator clock and the bit rate clock. At the beginning of a received data package, the bit synchronizer clock frequency is not synchronized to the bit rate. When these two are maximum offset to each other, it takes 22 bit/symbols before synchronization is achieved. Transmitter Power Amplifier A6..A0 0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 ’1’ 0000001 ‘1’ ‘0’ ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0 The maximum output power is approximately 10dBm for a 50Ω load. The output power is programmable in seven steps, with approximately 3dB between each step. Bits PA2 – PA0, control this. PA2 – PA0 = 1 give the maximum output power. The power amplifier can be turned off by setting PA2 – PA0 = 0. For all other combinations the PA is on and has maximum power when PA2 – PA0 = 1. Frequency Modulation FSK modulation is applied by switching between two sets of dividers (M,N,A). The formula for calculating the M, N and A values is given in chapter Frequency synthesizer. The divider values stored in the M0-, N0-, and A0- registers will be used when transmitting a ‘0’ and the M1-, N1-, and A1-registers will be used to transmit a ‘1’. The difference between the two carrier frequencies corresponds to the double sided frequency deviation. The data to be transmitted shall be applied to pin DataIXO (see chapter Transceiver sync-/non-synchronous mode on how to use the pin DataClk). The DataIXO pin is set as input in transmit mode and output in receive mode. Using the XCO-tune Bits The module has a built-in mechanism for tuning the frequency of the crystal oscillator and is often used in combination with the Frequency Error Estimator (FEE). The XCO tuning is designed to eliminate or reduce initial frequency tolerance of the crystal and/or the frequency stability over temperature. A procedure for using the XCO tuning feature in combination with the FEE is given below. The MICRF620 measures the frequency offset between the receivers LO frequency and the frequency of the transmitter. The receiver XCO frequency can be tuned until the receiver and transmitter frequencies are equal. A procedure like this can be called during production (storing the calibrated XCO_tune value), at regular intervals or implemented in the communication protocol when the frequency has changed. The MICRF620 development system can test this feature. Example: In FEE, count up+down pulses, counting 8 bits: A perfect case ==> FEE = 0 If FEE > 0: LO is too low, increase LO by decreasing XCO_tune value v.v. for FEE < 0 FEE field holds a number in the range -128, … , 127. However, it keeps counting above/below the range, which is: If FEE = -128 and still counting dwn-pulses: 1) =>-129 = +127 2) 126 3) 125 To avoid this situation, always make sure max count is between limits.