RF430CL330H-Q1

RF430CL330H-Q1 TI1 | Alldatasheet

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Sample & Buy T echnical Documents Tools & Software Support & Community RF430CL330H-Q1 SLASE81 –JUNE 2015 RF430CL330H-Q1AutomotiveDynamicNFCInterfaceTransponder

1 Device Overview

1.1 Features

• Qualified for Automotive Applications • 3KB of SRAM for NDEF Messages
• NFC Tag Type 4 • Automatic Checking of NDEF Structure
• ISO14443B-Compliant 13.56-MHz RF Interface • Interrupt Register and Output Pin to Indicate NDEF Supports up to 848 kbps Read or Write Completion
• SPI or I2C Interface to Write and Read NDEF Messages to Internal SRAM

1.2 Applications

• Bluetooth® Pairing • Diagnostic Interface
• Wi-Fi® Configuration • Sensor Interface

1.3 Description

The TI Dynamic Near Field Communication (NFC) Interface Transponder RF430CL330H is an NFC Tag Type 4 device that combines a wireless NFC interface and a wired SPI or I2C interface to connect the device to a host. The NDEF message in the SRAM can be written and read from the integrated SPI or I2C serial communication interface and can also be accessed and updated wirelessly through the integrated ISO14443B-compliant RF interface that supports up to 848 kbps. This operation allows NFC connection handover for an alternative carrier like Bluetooth, Bluetooth low energy (BLE), and Wi-Fi as an easy and intuitive pairing process or authentication process with only a tap. As a general NFC interface, the RF430CL330H enables end equipments to communicate with the fast- growing infrastructure of NFC-enabled smart phones, tablets, and notebooks. Device Information(1) PART NUMBER PACKAGE BODY SIZE(2) RF430CL330HTPWRQ1 TSSOP (14) 5 mm × 4.4 mm (1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. (2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Typical Application Diagram

Figure 1-1 shows a typical application diagram for the RF430CL330H device. Figure 1-1. Typical Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLASE81 –JUNE 2015 www.ti.com Table of Contents

2 Revision History

June 2015 * Initial Release

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10 SCK

12 SI/SDA

13 VCORE

14 VSS

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3 Terminal Configuration and Functions

Figure 3-1 shows the pinout for the PW package. Figure 3-1. 14-Pin PW Package (Top View)

3.1 Pin Attributes

Table 3-1. Pin Attributes PIN NO. SIGNAL NAME(1) (2) SIGNAL TYPE(3) BUFFER TYPE(4) POWER SOURCE RESET STATE(5)

1 VCC PWR Power VCC N/A

2 ANT1 RF Analog N/A

3 ANT2 RF Analog N/A

4 RST I LVCMOS VCC PU

5 E0 I LVCMOS VCC OFF

6 E1 I LVCMOS VCC OFF

7 E2 I LVCMOS VCC OFF

8 INTO O LVCMOS VCC DRIVE0

10 SCK I LVCMOS VCC OFF

13 VCORE PWR Power VCC N/A

14 VSS PWR Power VCC N/A

(1) For each multiplexed pin, the signal that is listed first in this table is the reset default. (2) To determine the pin mux encodings for each pin, see Section 3.3. (3) Signal Types: I = Input, O = Output, I/O = Input or Output, PWR = Power, RF = Radio frequency (4) Buffer Types: See Table 3-3 for details. (5) Reset States: OFF = High-impedance input with pullup or pulldown disabled (if available) PD = High-impedance input with pulldown enabled PU = High-impedance input with pullup enabled DRIVE0 = Drive output low DRIVE1 = Drive output high N/A = Not applicable Copyright © 2015, Texas Instruments Incorporated Terminal Configuration and Functions 3 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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3.2 Signal Descriptions

Table 3-2 describes the signals. Table 3-2. Signal Descriptions SIGNALFUNCTION SIGNAL NAME PIN NO. DESCRIPTIONTYPE(1) VCC 1 PWR 3.3-V power supply Power VCORE 13 PWR Regulated core supply voltage VSS 14 PWR Ground supply ANT1 2 RF Antenna input 1 RF ANT2 3 RF Antenna input 2 CS 9 I Chip select (in SPI mode) I2C address select 0E0 5 I SPI mode select 0 I2C address select 1E1 6 I SPI mode select 1 E2 7 I I2C address select 2(2) Serial SCK 10 I SPI clock input (SPI mode) communication SCL 11 I/O I2C clock (I2C mode) Serial communication mode select (during deviceSCMS 9 I initialization)(3) SDA I/O I2C data (I2C mode) SI 12 I SPI slave in (SPI mode) SO 11 O SPI slave out (SPI mode) INTO 8 O Interrupt output System RST 4 I Reset input (active low)(4) (1) I = Input, O = Output, PWR = Power, RF = RF Antenna (2) Tie low in SPI mode to avoid floating inputs. (3) Selects I2C or SPI mode during the power-up and initialization phase (see Section 5.3.1). Tie SCMS/CS low to select I2C mode. (4) With integrated pullup.

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3.3 Pin Multiplexing

The only pin multiplexing in this device is for the serial communication pins and is based on the mode (SPI or I2C) that is selected during power up. For details, see Section 5.3.1, SPI or I2C Mode Selection. Table 3-3. Buffer Type NOMINAL OUTPUT BUFFER TYPE NOMINAL PU OR PD DRIVE OTHERHYSTERESIS PU OR PD(STANDARD) VOLTAGE STRENGTH STRENGTH CHARACTERISTICS (µA) (mA) See Section 4.6, See Section 4.7,LVCMOS 3.3 V Y N/A Digital Inputs Digital Outputs See analog modules in Analog, RF 3.3 V N N/A N/A N/A Specifications (Section 4) for details Power 3.3 V Y with SVS on N/A N/A N/A

3.4 Connections for Unused Pins

Table 3-4 describes the recommended connections for unused pins. Table 3-4. Connections for Unused Signals ACCEPTABLEFUNCTION SIGNAL NAME PIN NUMBER PREFERRED PRACTICEPRACTICE I2C SCK 10 Connect to VSS Connect to VSS SPI E2 7 Connect to VSS Connect to VSS Copyright © 2015, Texas Instruments Incorporated Terminal Configuration and Functions 5 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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4 Specifications

4.1 Absolute Maximum Ratings(1) (2)

Voltage applied at VCC referenced to VSS (VAMR) –0.3 4.1 V Voltage applied at VANT referenced to VSS (VAMR) –0.3 4.1 V Voltage applied to any pin (references to VSS) –0.3 VCC + 0.3 V Diode current at any device pin ±2 mA Storage temperature, Tstg(3) –40 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are referenced to VSS. (3) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

4.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted) MIN NOM MAX UNIT During program execution no RF field present 3.0 3.3 3.6 VCC Supply voltage V During program execution with RF field present 2.0 3.3 3.6 VSS Supply voltage (GND reference) 0 V TA Operating free-air temperature –40 105 °C C1 Decoupling capacitor on VCC (1) 0.1 µF C2 Decoupling capacitor on VCC (1) 1 µF CVCORE Capacitor on VCORE (1) 0.1 0.47 1 µF (1) Low equivalent series resistance (ESR) capacitor

4.4 Recommended Operating Conditions, Resonant Circuit

fc Carrier frequency 13.56 MHz VANT_peak Antenna input voltage 3.6 V Z Impedance of LC circuit 6.5 15.5 kΩ LRES Coil inductance(1) 2.66 µH CRES Total resonance capacitance(1) CRES = CIN+CTune 51.8 pF CRES –CTune External resonance capacitance pFCIN (2) QT Tank quality factor 30 (1) The coil inductance of the antenna LRES together with the external capacitance CTune plus the device internal capacitance CIN is a resonant circuit. The resonant frequency of this LC circuit must be close to the carrier frequency fc: fRES = 1 / [2π(LRESCRES)1/2] = 1 / [2π(LRES(CIN + CTune))1/2] ≈ fc (2) For CIN refer to Table 4-4.

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4.5 Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Typical values are specified at VCC = 3.3 V and TA = 25°C PARAMETER VCC MIN TYP MAX UNIT ICC(SPI) SPI, fSCK,MAX, SO = Open, Writing into NDEF memory 3.3 V 45 1250 µA ICC(I2C) I2C, 400 kHz, Writing into NDEF memory 3.3 V 30 750 µA ICC(RF enabled) RF enabled, no RF field present 3.3 V 40 175 µA Standby enable = 0, RF disabled, no serialICC(Inactive) 3.3 V 15 140 µAcommunication Standby enable = 1, RF disabled, no serialICC(Standby) 3.3 V 10 110 µAcommunication

4.6 Electrical Characteristics, Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Typical values are specified at VCC = 3.3 V and TA = 25°C PARAMETER VCC MIN TYP MAX UNIT VIL Low-level input voltage 0.3 × VCC V VIH High-level input voltage 0.7 × VCC V VHYS Input hysteresis 0.1 × VCC V IL High-impedance leakage current 3.3 V –180 180 nA RPU(RST) Integrated RST pullup resistor 20 35 50 kΩ RPU(CS) Integrated SCMS/CS pullup resistor (only active during initialization) 20 35 50 kΩ

4.7 Electrical Characteristics, Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT 3 V 0.4 VOL Output low voltage IOL = 3 mA 3.3 V 0.4 V 3.6 V 0.4 3 V 2.6 VOH Output high voltage IOH = –3 mA 3.3 V 2.9 V 3.6 V 3.2

4.8 Thermal Characteristics, TSSOP-14 (PW) Package

over operating free-air temperature range (unless otherwise noted) PARAMETER VALUE UNIT θJA Junction-to-ambient thermal resistance, still air(1) 116.0 °C/W θJC(TOP) Junction-to-case (top) thermal resistance(2) 45.1 °C/W θJB Junction-to-board thermal resistance(3) 57.6 °C/W ΨJB Junction-to-board thermal characterization parameter 57.0 °C/W ΨJT Junction-to-top thermal characterization parameter 4.6 °C/W (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Copyright © 2015, Texas Instruments Incorporated Specifications 7 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

tHD,DA T tSU,DA T tHD,ST A tSU,ST A tHD,ST A tSU,STO tSP RF430CL330H-Q1 SLASE81 –JUNE 2015 www.ti.com

4.9 Timing and Switching Characteristics

4.9.1 Reset Timing

Table 4-1. Serial Communication Protocol Selection over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN MAX UNIT tSPIvsI2C Time after power up or reset until SCMS/CS is sampled for SPI or I2C decision(1) 1 10 ms tReady Time after power up or reset until device is ready to communicate using SPI or I2C(2) 20 ms (1) The SCMS/CS pin is sampled after tSPIvsI2C(MIN) at the earliest and after tSPIvsI2C(MAX) at the latest. (2) The device is ready to communicate after tReady(MAX) at the latest.

4.9.2 I2C Interface

Table 4-2. I2C Interface Timing over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-1) TESTPARAMETER VCC MIN MAX UNITCONDITIONS With master supporting clock stretching according to I2C 0 400standard, or when the device is not being addressedSCL clockfSCL 3.3 V kHzfrequency Write 0 120Device being addressed by master not supporting clock stretching Read 0 100 fSCL ≤ 100 kHz 4 tHD,STA Hold time (repeated) START 3.3 V µs fSCL > 100 kHz 0.6 fSCL ≤ 100 kHz 4.7 tSU,STA Setup time for a repeated START 3.3 V µs fSCL > 100 kHz 0.6 tHD,DAT Data hold time 3.3 V 0 ns tSU,DAT Data setup time 3.3 V 250 ns tSU,STO Setup time for STOP 3.3 V 4 µs tSP Pulse duration of spikes suppressed by input filter 3.3 V 6.25 75 ns Figure 4-1. I2C Mode Timing

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tSU,SI tHD,SI tVALID,SO tHIGH 1/fSCK tLOW CS tSU,CS tHD,CS tCS,HIGH RF430CL330H-Q1 www.ti.com SLASE81 –JUNE 2015

4.9.3 SPI Interface

Table 4-3. SPI Interface Timing over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Write 3.3 V 0 100 fSCK SCK clock frequency kHz Read 3.3 V 0 110 tHIGH,CS CS high time 3.3 V 50 µs tSU,CS CS setup time 3.3 V 25 µs tHD,CS CS hold time 3.3 V 100 ns tHIGH SCK high time 3.3 V 100 ns tLOW SCK low time 3.3 V 100 ns tSU,SI Data in (SI) setup time 3.3 V 50 ns tHD,SI Data in (SI) hold time 3.3 V 50 ns tVALID,SO Data out (SO) valid 3.3 V 0 50 ns tHOLD,SO Data out (SO) hold time 3.3 V 0 ns Figure 4-2. SPI Mode Timing Copyright © 2015, Texas Instruments Incorporated Specifications 9 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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4.9.4 RF143B Module

Table 4-4. RF143B, Recommended Operating Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDH Antenna rectified voltage Peak voltage limited by antenna limiter 3.0 3.3 3.6 V IDDH Antenna load current RMS, without limiter current 100 µA CIN Input capacitance ANT1 to ANT2, 2 V RMS 31.5 35 38.5 pF Table 4-5. RF143B, ISO14443B ASK Demodulator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN TYP MAX UNIT DR10 Input signal data rate 10% downlink modulation, 7% to 30% ASK, ISO1443B 106 848 kbps m10 Modulation depth 10%, tested as defined in ISO10373 7% 30% Table 4-6. RF143B, ISO14443B-Compliant Load Modulator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN MAX UNIT fPICC Uplink subcarrier modulation frequency 0.2 1 MHz VA_MOD Modulated antenna voltage, VA_unmod = 2.3 V 0.5 V VSUB14 Uplink modulation subcarrier level, ISO14443B: H = 1.5 to 7.5 A/m 22/H0.5 mV Table 4-7. RF143B, Power Supply over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VLIM Limiter clamping voltage ILIM ≤ 70 mA RMS, f = 13.56 MHz 3.0 3.6 Vpk ILIM,MAX Maximum limiter current 70 mA

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2 Processing

(MSP430- based) ISO14443B RF Interface NDEF Memory (SRAM) SCL/SO SDA/SI SCK E0 E1 E2 INTO ANT1 VCC VSS VCORE ANT2 SCMS/CS RST RF430CL330H-Q1 www.ti.com SLASE81 –JUNE 2015

5 Detailed Description

5.1 Overview

Figure 5-1 shows the functional block diagram.

5.2 Functional Block Diagram

Figure 5-1. Functional Block Diagram

5.3 Serial Communication Interface

A dual-mode serial communication interface supports either SPI or I2C communication. The serial interface allows writing and reading the internal NDEF memory as well as configuring the device operation.

5.3.1 SPI or I2C Mode Selection

The selection between I2C or SPI mode occurs during the power-up and initialization phase of the device based on the input level at pin SCMS/CS (see Table 5-1). Table 5-1. SPI or I2C Mode Selection INPUT LEVEL AT SCMS/CS SELECTED SERIAL INTERFACEDURING INITIALIZATION

0 I2C

1 SPI

During initialization, an integrated pullup resistor pulls SCMS/CS high, which makes SPI the default interface. To enable I2C, this pin must be tied low externally. The pullup resistor is disabled after initialization to avoid any current through the resistor during normal operation. In SPI mode, the pin reverts to its CS functionality after initialization. Copyright © 2015, Texas Instruments Incorporated Detailed Description 11 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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5.3.2 Communication Protocol

The tag is programmed and controlled by writing data into and reading data from the address map shown in Table 5-2 through the serial interface (SPI or I2C). Table 5-2. User Address Map RANGE ADDRESS SIZE DESCRIPTION 0xFFFE 2B Control Register 0xFFFC 2B Status Register 0xFFFA 2B Interrupt Enable 0xFFF8 2B Interrupt Flags 0xFFF6 2B CRC Result (16-bit CCITT) 0xFFF4 2B CRC Length 0xFFF2 2B CRC Start Address 0xFFF0 2B Communication Watchdog Control Register Registers 0xFFEE 2B Version 0xFFEC 2B Reserved 0xFFEA 2B Reserved 0xFFE8 2B Reserved 0xFFE6 2B Reserved 0xFFE4 2B Reserved 0xFFE2 2B Reserved 0xFFE0 2B Reserved 0x4000 to 0xFFDF Reserved Reserved 0x0C00 to 0x3FFF 13KB Reserved (for example, future extension of NDEF Memory size) NDEF 0x0000 to 0x0BFF 3KB NDEF Memory NOTE Crossing range boundaries causes writes to be ignored and reads to return undefined data.

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MSB LSBR/WACKMSB LSBACKMSB LSBACK MSB LSBACK Driven by: Driven by: Master Master Slave (NFC Tag) Slave (NFC Tag) Data @ Addr + 0 Device Address Address Bits 15-8 Address Bits 7-0 STOP MSB LSBACK MSB LSBACK Data @ Addr + nData @ Addr + 1 RF430CL330H-Q1 www.ti.com SLASE81 –JUNE 2015

5.3.3 I2C Protocol

A command is always initiated by the master by addressing the device using the specified I2C device address. The device address is a 7-bit I2C address. The upper 4 bits are hard-coded, and the lower 3 bits are programmable by the input pins E0 through E2. Table 5-3. I2C Device Address Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 1 E2 E1 E0 MSB LSB To write data, the device is addressed using the specified I2C device address with R/W = 0, followed by the upper 8 bits of the first address to be written and the lower 8 bits of that address. Next (without a repeated START), the data to be written starting at the specified address is received. With each data byte received, the address is automatically incremented by 1. The write access is terminated by the STOP condition on the I2C bus. Figure 5-2. I2C Write Access To read data, the device is addressed using the specified I2C device address with R/W = 0, followed by the upper 8 bits of the first address to be read and then the lower 8 bits of that address. Next, a repeated START condition is expected with the I2C device address and R/W = 1. The device then transmit data starting at the specified address until a NACK and a STOP condition are received. Copyright © 2015, Texas Instruments Incorporated Detailed Description 13 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

MSB LSBR/WACKMSB LSBACKMSB LSBACKMSB LSBR/WACK Driven by: Driven by: Master Master Slave (NFC Tag) Slave (NFC Tag) Device Address Address Bits 15-8 Address Bits 7-0 Device Address STOP MSB MSBLSB LSBACK ACK MSB LSB NO ACK Data @ Addr + nData @ Addr + 0 Data @ Addr + 1 RF430CL330H-Q1 SLASE81 –JUNE 2015 www.ti.com Figure 5-3. I2C Read Access Figure 5-4 and Figure 5-5 show examples of I2C access to the Control register at address 0xFFFE. Figure 5-4. I2C Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x02 (RF Enable = 1) Figure 5-5. I2C Access Example: Read of the Control Register at Address 0xFFFE, Responds With 0x00, 0x02 (RF Enable = 1)

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5.3.3.1 Bit-Interleaved Parity (BIP-8) Communication Mode With I2C

The BIP-8 communication mode is enabled by setting the BIP-8 bit in the General Control register. All communication after setting this bit uses the following conventions with exactly 2 address bytes (16-bit address) and 2 data bytes (16-bit data). Table 5-4. Write Access Address Bits Address BitsMaster Data at Addr + 0 Data at Addr + 1 BIP-815 to 8 7 to 0 Slave N/A N/A N/A N/A N/A The BIP-8 is calculated using 16-bit address and 16-bit data. If the received BIP-8 does not match with received data no write will be performed. The BIP-8 calculation does not include the I2C device address. Table 5-5. Read Access Address Bits Address BitsMaster N/A N/A N/A15 to 8 7 to 0 Slave N/A N/A Data at Addr + 0 Data at Addr + 1 BIP-8 For read access, the BIP-8 is calculated using the received 16-bit address and the 2 transmitted data bytes, and it is transmitted back to the master. The BIP-8 calculation does not include the device address.

5.3.4 SPI Protocol

The SPI communication mode (SCK idle state and clock phase) is selected by tying E0 and E1 to VSS or VCC according to Table 5-6. Table 5-6. SPI Mode Selection E1 E0 SPI MODE SPI Mode 0 with CPOL = 0 and CPHA = 0 SCK idle state: 00 0 SI capture starts on the first edge: SI data is captured on the rising edge, and SO data is propagated on the falling edge. SPI Mode 1 with CPOL = 0 and CPHA = 1 SCK idle state: 00 1 SI capture starts on the second edge: SI data is captured on the falling edge, and SO data is propagated on the rising edge. SPI Mode 2 with CPOL = 1 and CPHA = 0 SCK idle state: 11 0 SI capture starts on the first edge: SI data is captured on the falling edge, and SO data is propagated on the rising edge. SPI Mode 3 with CPOL = 1 and CPHA = 1 SCK idle state: 11 1 SI capture starts on the second edge: SI data is captured on the rising edge, and SO data is propagated on the falling edge. An SPI communication is always initiated by the master by pulling the CS pin low. To write data into the device (see Figure 5-6), this is followed by the master sending a write command (0x02) followed by the upper 8 bits of the first address to be written and then the lower 8 bits of that address. Next, the data to be written starting at the specified address is received. With each data byte received, the address is automatically incremented by 1. The write access is terminated by pulling the CS pin high. Copyright © 2015, Texas Instruments Incorporated Detailed Description 15 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

SCK (Mode 2) SCK (Mode 0) SCK (Mode 3) SCK (Mode 1) SI SO Address Bits 15-8 Address Bits 7-0Command: Write MSB LSBMSB LSBMSB LSB Hi-Z Hi-Z Data @ Addr + nData @ Addr + 0 CS SI SO SCK (Mode 2) SCK (Mode 0) SCK (Mode 3) SCK (Mode 1) MSB LSB Data @ Addr + 1 RF430CL330H-Q1 SLASE81 –JUNE 2015 www.ti.com Figure 5-6. SPI Write Access To read data from the device (see Figure 5-7), pulling the CS pin low is followed by the master sending a read command (0x03 or 0x0B) followed by the upper 8 bits of the first address to be read, the lower 8 bits of that address, and a dummy byte. The device responds with the data that is read starting at the specified address until the CS pin is pulled high.

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SLASE81 –JUNE 2015 www.ti.com Figure 5-8. SPI Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x02 (RF Enable = 1)

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www.ti.com SLASE81 –JUNE 2015 Figure 5-9. SPI Access Example: Read of the Control Register at Address 0xFFFE, Responds With 0x00, 0x02 (RF Enable = 1) Copyright © 2015, Texas Instruments Incorporated Detailed Description 19 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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5.3.4.1 BIP-8 Communication Mode With SPI

The BIP-8 communication mode is enabled by setting the BIP-8 bit in the General Control register. All communication after setting this bit uses the following conventions with exactly 2 address bytes (16-bit address) and 2 data bytes (16-bit data). Table 5-7. Write Access Address Bits Address BitsSI Command: Write Data at Addr + 0 Data at Addr + 1 BIP-815 to 8 7 to 0 SO N/A N/A N/A N/A N/A N/A The BIP-8 is calculated using 16-bit address and 16-bit data. If the received BIP-8 does not match with received data no write will be performed. The BIP-8 calculation does not include the write-command byte. Table 5-8. Read Access Address Bits Address BitsSI Command: Read Dummy Byte N/A N/A N/A15 to 8 7 to 0 SO N/A N/A N/A N/A Data at Addr + 0 Data at Addr + 1 BIP-8 For read access the BIP-8 is calculated using the received 16-bit address, the received dummy byte and the 2 transmitted data bytes and transmitted back to the master. The BIP-8 calculation does not include the read-command byte.

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5.4 Registers

All 16-bit registers are little-endian: the least significant byte with bits 7-0 is at the lowest address (this address is always even). The most significant byte with bits 15-8 is at the highest address (always odd).

5.4.1 General Control Register

Table 5-9. General Control Register Address 15 14 13 12 11 10 9 8 0xFFFF Reserved Address 7 6 5 4 3 2 1 0 Standby0xFFFE Reserved BIP-8 INTO Drive INTO High Enable INT Enable RF SW-ResetEnable Table 5-10. General Control Register Description BIT FIELD TYPE RESET DESCRIPTION 0 SW-Reset W 0 0b = Always reads 0. 1b = Resets the device to default settings and clears memory. The serial communication is restored after tReady, and the register settings and NDEF memory must be restored afterward. 1 Enable RF R/W 0 Global enable of RF interface. The RF interface should be disabled when writing to the NDEF memory. Enabling the RF interface triggers a basic check of the NDEF structure. If this check fails, the RF interface remains disabled and the NDEF Error interrupt flag is set. When the RF interface is enabled, writes using the serial interface (except to disable the RF interface) are discouraged to avoid any interference with RF communication. 0b = RF interface disabled 1b = RF interface enabled

2 Enable INT R/W 0 Global Interrupt Output Enable

0b = Interrupt output disabled. The INTO pin is Hi-Z. 1b = Interrupt output enabled. The INTO pin signals any enabled interrupt according to the INTO High and INTO Drive bits.

3 INTO High R/W 0 Interrupt Output pin INTO Configuration

0b = Interrupts are signaled with an active low 1b = Interrupts are signaled with an active high

4 INTO Drive R/W 0 Interrupt Output pin INTO Configuration

0b = Pin is Hi-Z if there is no pending interrupt. Application provides an external pullup resistor if bit 3 (INTO Active High) = 0. Application provides an external pulldown resistor if bit 3 (INTO Active High) = 1. 1b = Pin is actively driven high or low if there is no pending interrupt. It is driven high if bit 3 (INTO Active High) = 0. It is driven low if bit 3 (INTO Active High) = 1. Copyright © 2015, Texas Instruments Incorporated Detailed Description 21 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

SLASE81 –JUNE 2015 www.ti.com Table 5-10. General Control Register Description (continued) BIT FIELD TYPE RESET DESCRIPTION 5 BIP-8 R/W 0 Enables BIP-8 communication mode (bit interleaved parity). If BIP-8 is enabled, a separate running tally is kept of the parity (that is, the number of ones that occur) for every bit position in the bytes included in the BIP-8 calculation. The corresponding bit position of the BIP-8 byte is set to 1 if the parity is currently odd and is set to 0 if the parity is even – resulting in an overall even parity for each bit position including the BIP-8 byte. All communication when this bit is set must follow the conventions defined in the BIP-8 communication mode sections for I2C and SPI. 0b = BIP-8 communication mode disabled 1b = BIP-8 communication mode enabled 6 Standby Enable R/W 0 Enables a low-power standby mode. The standby mode is entered if the RF interface is disabled, the communication watchdog is disabled, and no serial communication is ongoing. 0b = Standby mode disabled 1b = Standby mode enabled

7 Reserved R/W 0

5.4.2 Status Register

Table 5-11. Status Register Address 15 14 13 12 11 10 9 8 0xFFFD Reserved Address 7 6 5 4 3 2 1 0 0xFFFC Reserved RF Busy CRC Active NDEF Ready Table 5-12. Status Register Description BIT FIELD TYPE RESET DESCRIPTION

0 NDEF Ready R 0 0b = Device not ready to receive updates to the NDEF memory from the serial

interface. 1b = Device ready. NDEF memory can be written by the serial interface.

1 CRC Active R 0 0b = No CRC calculation ongoing

1b = CRC calculation ongoing

2 RF Busy R 0 0b = No RF communication ongoing

1b = RF communication ongoing 3-15 Reserved R 0

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5.4.3 Interrupt Registers

The interrupt enable register (see Table 5-13 and Table 5-14) determines which interrupt events are signaled on the external output pin INTO. Setting any bit high in this register allows the corresponding event to trigger the interrupt signal. See Table 5-17 for a description of each interrupt. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. Table 5-13. Interrupt Enable Register Address 15 14 13 12 11 10 9 8 0xFFFB Reserved Address 7 6 5 4 3 2 1 0 CRCBIP-8 Error0xFFFA Generic Error Reserved NDEF Error Calculation End of Write End of Read ReservedDetected Completed Table 5-14. Interrupt Enable Register Description BIT FIELD TYPE RESET DESCRIPTION 0-15 Interrupt Enables R/W 0 Enable for the corresponding IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 0b = IRQ disabled 1b = IRQ enabled The interrupt flag register (see Table 5-15 and Table 5-16) is used to report the status of any interrupts that are pending. Setting any bit high in this register acknowledges and clears the interrupt associated with the respective bit. See Table 5-17 for a description of each interrupt. Table 5-15. Interrupt Flag Register Address 15 14 13 12 11 10 9 8 0xFFF9 Reserved Address 7 6 5 4 3 2 1 0 CRCBIP-8 Error0xFFF8 Generic Error Reserved NDEF Error Calculation End of Write End of Read ReservedDetected Completed Table 5-16. Interrupt Flag Register Description BIT FIELD TYPE RESET DESCRIPTION 0-15 Interrupt Flags R/W 0 Flag pending IRQ. Read Access: 0b = No pending IRQ. 1b = Pending IRQ. Write Access: 0b = No change. 1b = Clear pending IRQ flag. Copyright © 2015, Texas Instruments Incorporated Detailed Description 23 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

SLASE81 –JUNE 2015 www.ti.com Table 5-17. Interrupts BIT FIELD DESCRIPTION

0 Reserved

1 End of Read This IRQ occurs when the RF field is turned off by the reader after the reader has performed a read of the NDEF message. 2 End of Write This IRQ occurs when the RF field is turned off by the reader after the reader has performed a write into the NDEF message. 3 CRC Calculation Completed This IRQ occurs when a CRC calculation that is triggered by writing into the CRC registers is completed and the result can be read from the CRC result register (see Section 5.4.4). 4 BIP-8 Error Detected This IRQ occurs when a BIP-8 error is detected (only if the BIP-8 communication mode is enabled). 5 NDEF Error This IRQ occurs if an error is detected in the NDEF structure after an attempt to enable the RF interface.

6 Reserved

7 Generic Error This IRQ occurs for any error that makes the device unreliable or nonoperational. 8-15 Reserved

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5.4.4 CRC Registers

Writing the CRC address and the CRC length registers initiates a 16-bit CRC calculation of the specified address range. The length is always assumed to be even (16-bit aligned). Writing the length register starts the CRC calculation. During the CRC calculation, the CRC active bit is set (=1). When the calculation is complete, the "CRC completion" interrupt flag is set and the result of the CRC calculation can be read from the CRC result register. It is recommended to perform a CRC calculation only when the RF interface is disabled (RF Enable = 0). Table 5-18. CRC Result Register Address 15 14 13 12 11 10 9 8 0xFFF7 CRC CCITT Result (high byte) Address 7 6 5 4 3 2 1 0 0xFFF6 CRC CCITT Result (low byte) Table 5-19. CRC Result Register Description BIT FIELD TYPE RESET DESCRIPTION 0-15 CRC-CCITT Result R 0 CRC-CCITT Result Table 5-20. CRC Length Register Address 15 14 13 12 11 10 9 8 0xFFF5 CRC Length (high byte) Address 7 6 5 4 3 2 1 0 0xFFF4 CRC Length (low byte) Table 5-21. CRC Length Register Description BIT FIELD TYPE RESET DESCRIPTION 0-15 CRC Length RW 0 CRC Length - always assumed to be even (Bit 0 = 0). Writing into high byte starts CRC calculation. Table 5-22. CRC Start Address Register Address 15 14 13 12 11 10 9 8 0xFFF3 CRC Start Address (high byte) Address 7 6 5 4 3 2 1 0 0xFFF2 CRC Start Address (low byte) Table 5-23. CRC Start Address Register Description BIT FIELD TYPE RESET DESCRIPTION 0-15 CRC Start Address RW 0 CRC Start Address. Defines start address within NDEF memory. This address is always assumed to be even (bit 0 = 0). The CRC is calculated based on the CCITT polynomial initialized with 0xFFFF. CCITT polynomial: x16 + x12 + x5 + 1 Copyright © 2015, Texas Instruments Incorporated Detailed Description 25 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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5.4.5 Communication Watchdog Register

When the communication watchdog is enabled, it expects a write or read access within a specified period; otherwise, the watchdog resets the device. If the BIP-8 communication mode is enabled, the transfer must be valid to be accepted as a watchdog reset. Table 5-24. Communication Watchdog Register Address 15 14 13 12 11 10 9 8 0xFFF1 Reserved Address 7 6 5 4 3 2 1 0 0xFFF0 Reserved Time-out Period Selection Enable Table 5-25. Communication Watchdog Register Description BIT FIELD TYPE RESET DESCRIPTION

0 Enable R/W 0 0b = Communication Watchdog disabled

1b = Communication Watchdog enabled

1 Time-out Period R/W 0 000b = 2 s ±30%(1)

011b to 111b = Reserved 4-15 Reserved R 0 (1) This value is based on use of the integrated low-frequency oscillator with a frequency of 256 kHz ±30%.

5.4.6 Version Register

Provides version information about the implemented ROM code. Table 5-26. Version Register Address 15 14 13 12 11 10 9 8 0xFFEF Software Version Address 7 6 5 4 3 2 1 0 0xFFEE Software Identification Table 5-27. Version Register Description BIT FIELD TYPE RESET DESCRIPTION 0-7 Software Identification R 1h 0x01: RF430CL330H firmware 8-15 Software Version R Device Software versionspecific

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5.5 NFC Type-4 Tag Functionality

This device is an ISO14443B-compliant transponder that operates according to the NFC Forum Tag Type- 4 specification and supports the NFC Forum NDEF (NFC Data Exchange Format) requirements. Through the RF interface, the user can read and update the contents in the NDEF memory. The contents in the NDEF memory (stored in SRAM) are stored as long as power is maintained. NOTE This device does not have nonvolatile memory; therefore, the information stored in the NDEF memory is lost when power is removed. This device does not support the peer-to-peer or reader/writer modes in the ISO18092/NFC Forum specification. All RF communication between an NFC forum device and this device is in the passive tag mode. The device responds by load modulation and is not considered an intentional radiator. This device is intended to be used in applications where the primary reader/writer is for example an NFC- enabled cell phone. The device enables data transfer to and from an NFC phone by RF to the host application that is enabled with the dual interface device. In this case, the host application can be considered the destination device, and the cell phone or other type of mobile device is treated as the end- point device. This device supports ISO14443-3, ISO14443-4, and NFC Forum commands as described in the following sections. A high-level overview of the ISO14443B and NFC commands and responses are shown in Figure 5-10. 106-kbps, 212-kbps, 424-kbps, and 848-kbps data rates are supported. The device always answers ATTRIB commands from the PCD that request higher data rates. Note, this is not NFC-compliant, because for NFC-B the maximum data rate specified is 106 kbps. It is assumed that an NFC-compliant PCD would not request higher data rates thus no interoperability issues are expected. Even though all data rates up to 848 kbps are supported, the device by default reports only the capability to support 106 kbps to the PCD. To change this behavior, use the sequence described in Section 5.5.3. The ISO14443B command and response structure is detailed in ISO14443-3, ISO14443-4, and NFC Forum-TS-Digital Protocol. The applicable ISO7816-4 commands are detailed in NFC Forum-TS-Type-4- Tag_2.0. Copyright © 2015, Texas Instruments Incorporated Detailed Description 27 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

PCD PICC (RF430 NFC Tag)START (HF field presented to Tag) ISO14443-3 Type B Card Detection Procedure REQB ATTRIB ATQB ANSWER TO ATTRIB NFC Tag Type 4 Operations (ISO-DEP) NDEF Detection Procedure PCD PICC (RF430 NFC Tag) WUPB ATQB ATTRIB ANSWER TO ATTRIB A4, 04 SW1, SW2 A4, 0C, 0xE103 SW1, SW2 B0, Le = 0F A4, 0C, 0xE101 Response, SW1, SW2 SW1, SW2 B0, Le = 02 SW1, SW2 A4, 0C, 0xE101 SW1, SW2 B0, Le = 2D NDEF Message , SW1, SW2 B0, 2D, 02 Response, SW1, SW2 NDEF Tag Application Select, C-APDU (T4TOS) NDEF Tag Capability Container Select, C-APDU (T4TOS) Capability Container Read Read Binary Command, C-APDU (T4TOS) NDEF Select Command, C-APDU (T4TOS) NDEF Read Procedure Read Binary Command, C-APDU (T4TOS) NDEF Select Command, C-APDU (T4TOS) NDEF Read Procedure Read Binary Command, C-APDU (T4TOS) Deselect NDEF Messaging completed RF430CL330H-Q1 SLASE81 –JUNE 2015 www.ti.com Figure 5-10. Command and Response Exchange Flow

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5.5.1 ISO14443-3 Commands

These commands use the character, frame format, and timing that are described in ISO14443-3, clause 7.1. The following commands are used to manage communication: REQB and WUPB The REQB and WUPB commands sent by the PCD are used to probe the field for PICCs of Type B. In addition, WUPB is used to wake up PICCs that are in the HALT state. The number of slots N is included in the command as a parameter to optimize the anticollision algorithm for a given application. Slot-MARKER After a REQB or WUPB command, the PCD may send up to (N-1) Slot-MARKER commands to define the start of each timeslot. Slot-MARKER commands can be sent after the end of an ATQB message received by the PCD to mark the start of the next slot or earlier if no ATQB is received (there is no need to wait until the end of a slot, if this slot is known to be empty). ATTRIB The ATTRIB command sent by the PCD includes information required to select a single PICC. A PICC receiving an ATTRIB command with its identifier becomes selected and assigned to a dedicated channel. After being selected, this PICC only responds to commands defined in ISO/IEC 14443-4 that include its unique CID. HLTB The HLTB command is used to set a PICC in HALT state and stop responding to a REQB. After answering to this command, the PICC ignores any commands except the WUPB.

5.5.2 NFC Tag Type 4 Commands

Selection of applications or files ReadBinary Read data from file UpdateBinary Update (erase and write) data to file Copyright © 2015, Texas Instruments Incorporated Detailed Description 29 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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5.5.3 Data Rate Settings

106-kbps, 212-kbps, 424-kbps, and 848-kbps data rates are supported by the device. The device always answers ATTRIB commands from the PCD that request higher data rates. Note, this is not NFC-compliant, because for NFC-B the maximum data rate specified is 106 kbps. It is assumed that an NFC-compliant PCD would not request higher data rates thus no interoperability issues are expected. Even though all data rates up to 848 kbps are supported, the device by default reports only the capability to support 106 kbps to the PCD. To change this behavior, follow these steps using the selected serial interface (I2C or SPI): 1. Read the version register. 2. Use the version register content to select one of the following sequences: – If "Software Identification" = 01h and "Software Version" = 01h, follow the sequence in Table 5-28. – If "Software Identification" = 01h and "Software Version" = 02h , follow the sequence in Table 5-29. 3. If you do not want to support all data rates up to 847 kbps, then change the Data Rate Capability byte (Data 0 of Step 3. Write Access) according to Table 5-30. 4. Perform the steps in Table 5-28 or Table 5-29. Table 5-28. Data Rate Setting Sequence (Version = 0101h) ADDRESS BITS ADDRESS BITSACCESS TYPE DATA 0 DATA 115 to 8 7 to 0 1. Write Access 0xFF 0xE0 0x4E 0x00 2. Write Access 0xFF 0xFE 0x80 0x00 3. Write Access 0x2A 0xA4 0xC4(1) 0x00 4. Write Access 0x28 0x14 0x00 0x00 5. Write Access 0xFF 0xE0 0x00 0x00 (1) Data Rate Capability according to Table 5-30. 0xC4: all data rates up to 847 kbps are supported. Table 5-29. Data Rate Setting Sequence (Version = 0201h) ADDRESS BITS ADDRESS BITSACCESS TYPE DATA 0 DATA 115 to 8 7 to 0 1. Write Access 0xFF 0xE0 0x4E 0x00 2. Write Access 0xFF 0xFE 0x80 0x00 3. Write Access 0x2A 0x7C 0xC4(1) 0x00 4. Write Access 0x28 0x14 0x00 0x00 5. Write Access 0xFF 0xE0 0x00 0x00 (1) Data Rate Capability according to Table 5-30. 0xC4: all data rates up to 847 kbps are supported. Table 5-30. Data Rate Capability DATA RATA CAPABILITY BYTE

DESCRIPTION

0 0 0 0 0 0 0 0 PICC supports only 106-kbps in both directions (default). 1 x x x 0 x x x Same data rate from PCD to PICC and from PICC to PCD compulsory x x x 1 0 x x x PICC to PCD, data rate supported is 212 kbps x x 1 x 0 x x x PICC to PCD, data rate supported is 424 kbps x 1 x x 0 x x x PICC to PCD, data rate supported is 847 kbps x x x x 0 x x 1 PCD to PICC, data rate supported is 212 kbps x x x x 0 x 1 x PCD to PICC, data rate supported is 424 kbps x x x x 0 1 x x PCD to PICC, data rate supported is 847 kbps

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5.6 NDEF Memory

This device implements 3KB of SRAM memory that must be written with the NDEF Application data. Table 5-31 shows the mandatory structure. The data can be accessed through the RF interface only after the NDEF memory is correctly initialized through the serial interface (I2C or SPI). While writing into the NDEF memory, the RF interface must be disabled by clearing the Enable RF bit in the General Control register. After the NDEF memory is properly initialized, the RF interface can be enabled be setting the Enable RF bit in the General Control register to 1. When the RF interface is enabled, the basic NDEF structure is checked for correctness. If an error in the structure is detected, the NDEF Error IRQ is triggered, and the RF interface remains disabled (the Enable RF bit in the General Control register is cleared to 0). If the NDEF application data must be modified through the serial interface after the RF interface is enabled, it is recommended to read the RF Busy bit in the Status register. If the RF interface is busy, defer disabling the RF interface until the RF transaction is completed (indicated by RF Busy bit = 0). Figure 5-11 shows the recommended flow how to control the access to the NDEF memory. The address range for the NDEF memory is 0x0000 to 0x0BFF. Table 5-31. NDEF Application Data (Mandatory) 2B - CCLen 1B - Mapping version 2B - MLe = 000F9h 2B - MLc = 000F6h Capability Container 1B - Tag = 04h Selectable by File ID 1B - Len = 06hNDEF Application = E103h The NDEF file2B - File Identifier NDEF File Ctrl TLV control TLV isSelectable by Name = 2B - Max file size mandatoryD2_7600_0085_0101h 6B - Val 1B - Read access 1B - Write access 2B - LenNDEF File Mandatory NDEFxB - Binary NDEF file content fileSelectable by File ID yB - Unused if Len < Max file size in File Ctrl TLV= xxyyh Copyright © 2015, Texas Instruments Incorporated Detailed Description 31 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

SLASE81 –JUNE 2015 www.ti.com Table 5-32. NDEF Application Data (Includes Proprietary Sections) 2B - CCLen 1B - Mapping version 2B - MLe = 000F9h 2B - MLc = 000F6h 1B - Tag = 04h 1B - Len = 06h The NDEF file2B - File Identifier NDEF File Ctrl TLV control TLV is 2B - Max file size mandatory6B - Val 1B - Read access 1B - Write access 1B - Tag = 05hCapability Container 1B - Len = 06hSelectable by File ID 2B - File Identifier= E103h Proprietary File Ctrl TLV (1) 2B - Max file size 6B - Val 1B - Read access 1B - Write access Zero or moreNDEF Application ⋮ proprietary file control TLVsSelectable by Name = 1B - Tag = 05h D2_7600_0085_0101h 1B - Len = 06h 2B - File IdentifierProprietary File Ctrl TLV (N) 2B - Max file size 6B - Val 1B - Read access 1B - Write access 2B - LenNDEF File Mandatory NDEFxB - Binary NDEF file content fileSelectable by File ID yB - Unused if Len < Max file size in File Ctrl TLV= xxyyh 2B - LenProprietary File (1) OptionalxB - Binary proprietary file content proprietary fileSelectable by File ID yB - Unused if Len < Max file size in File Ctrl TLV= xxyyh 2B - LenProprietary File (N) OptionalxB - Binary proprietary file content proprietary fileSelectable by File ID yB - Unused if Len < Max file size in File Ctrl TLV= xxyyh

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(through serial interface) Modify NDEF memory (through serial interface) RF interface active (no modifications serial interface)through Wait for approximately 1 to 2 ms or End of Read or Write interruptEnd of Enable RF = 0 Yes Yes No No RF Busy = 0? Modifications serial interface required? through Enable RF = 1 RF430CL330H-Q1 www.ti.com SLASE81 –JUNE 2015 Figure 5-11. Recommended NDEF Memory Flow Copyright © 2015, Texas Instruments Incorporated Detailed Description 33 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

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5.6.1 NDEF Error Check

With the RF interface is enabled, the basic NDEF structure is automatically checked for correctness. If any of the following conditions are true, the error check fails, an NDEF error IRQ is triggered, and the RF interface remains disabled.

• CCLEN is less than 0x000F or greater than 0xFFFE.
• MLe value is less than 0xF. Note, for best performance the MLe value should be programmed to 0x00F9.
• MLc is equal to zero. Note, for best performance the MLc value should be programmed to 0x00F6.
• TLV tag does not equal 0x4.
• TLV length does not equal 0x6.
• File ID equals 0, or 0xE102, or 0xE103, or 0x3F00, or 0x3FFF, or 0xFFFF.
• Max NDEF size is less than 0x5 or greater than 0xFFFE.
• Read access is greater than 0 and less than 0x80.
• Write access is greater than 0 and less than 0x80. Also, the proprietary TLVs are checked. The check fails if any of the following conditions are true.
• TLV tag does not equal 0x05.
• TLV length does not equal 0x6.
• File ID equals 0, or 0xE102, or 0xE103, or 0x3F00, or 0x3FFF, or 0xFFFF.
• Max NDEF size is less than 0x5 or greater than 0xFFFE.
• Read access is greater than 0 and less than 0x80.
• Write access is greater than 0 and less than 0x80.

5.6.2 Typical Use Scenario

A typical use scenario is as follows: 1. Write capability container and messages into the NDEF memory (starting from address 0) using the serial interface. 2. Enable interrupts (especially End of Read and End of Write). 3. Configure the interrupt pin INTO as needed and enable the RF interface. 4. Wait for interrupt signaled by INTO. 5. Disable RF interface (but keep INTO settings unchanged). 6. Read interrupt flag register to determine interrupt sources. 7. Clear interrupt flags. INTO returns to inactive state. 8. Read and modify NDEF memory as needed. 9. Enable RF interface again (keeping INTO settings unchanged) and continue with Step 4.

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5.7 Identification

5.7.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The device-specific errata sheet describes these markings. For a link to the errata sheet for the device in this data sheet, see Section 7.2.

5.7.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific errata sheet describes these markings. For a link to the errata sheet for the device in this data sheet, see Section 7.2.

5.7.3 JTAG Identification

This device does not provide JTAG-compliant boundary scan test.

5.7.4 Software Identification

The Version register (see Section 5.4.6) stores the software version number. Copyright © 2015, Texas Instruments Incorporated Detailed Description 35 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

9 SCMS/CS

11 SO/SCL

External Reset (optional) SI SCK CS SO Interrupt Outputn/a for SPI VCC SPI Mode Select SPI Mode Select 1VCC 2ANT1 3ANT2 4RST 5E0 6E1 7E2 8 INTO External Reset (optional) I2C Address Select SDA SCL I2C Address Select I2C Address Select Interrupt Output select I2C n/a for I2C VCC RF430CL330H-Q1 SLASE81 –JUNE 2015 www.ti.com

6 Applications, Implementation, and Layout

6.1 Application Diagrams

Figure 6-1 and Figure 6-2 show sample application diagrams for I2C and SPI operation, respectively. NOTE: For recommended capacitance values, see Recommended Operating Conditions. Figure 6-1. Example Application Diagram (I2C Operation) NOTE: For recommended capacitance values, see Recommended Operating Conditions. Figure 6-2. Example Application Diagram (SPI Operation)

6.2 References

ISO/IEC 14443-2: 2001, Part 2: Radio frequency interface power and signal interface ISO/IEC 14443-3: 2001, Part 3: Initialization and anticollision ISO/IEC 14443-4: 2001, Part 4: Transmission protocols ISO/IEC 18092, NFC Communication Interface and Protocol-1 (NFCIP-1) ISO/IEC 21481, NFC Communication Interface Protocol-2 (NFCIP-2) NDEF NFC Forum Spec, NFC Data Exchange Format Specification

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7 Device and Documentation Support

7.1 Device Support

7.1.1 Development Support

7.1.1.1 Getting Started and Next Steps

For more information on the RF430 family of devices and the tools and software that are available to help with your development, visit the Tools & Software for NFC / RFID page. The Dynamic Near Field Communication (NFC) Type 4B Tag design (TIDM-DYNAMICNFCTAG) outlines the required components, layout considerations, and provides firmware examples to implement NFC into applications such as Bluetooth/Wi-Fi pairing, equipment configuration and diagnostics, or as a general purpose NFC data interface. The documentation, hardware, and example code provided allows the designer to quickly implement NFC functionality with an MSP430™ MCU or other MCU of choice.

7.1.2 Device and Development Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all RF430 MCU devices and support tools. Each commercial family member has one of three prefixes: RF, P, or X (for example, RF430CL330H). TI recommends two of three possible prefix designators for its support tools: RF and X. These prefixes represent evolutionary stages of product development from engineering prototypes (with X for devices and tools) through fully qualified production devices and tools (with RF for devices tools). Device development evolutionary flow: X – Experimental device that is not necessarily representative of the electrical specifications of the final device P – Final silicon die that conforms to the electrical specifications of the final device but has not completed quality and reliability verification RF – Fully qualified production device Support tool development evolutionary flow: X – Development-support product that has not yet completed TI internal qualification testing. RF – Fully-qualified development-support product X and P devices and X development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." RF devices and RF development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X and P) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RGE) and temperature range (for example, T). Figure 7-1 provides a legend for reading the complete device name for any family member. Copyright © 2015, Texas Instruments Incorporated Device and Documentation Support 37 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

Processor Family RF = Embedded RF Radio X = Experimental Silicon P = Prototype Device

430 MCU Platform TI’s Low-Power Microcontroller Platform

Device Type C = Fixed Function L = Low Power Wireless Technology Device Designator Various Levels of Integration Within a Series Optional: Revision A = Device Revision Optional: Temperature Range S = 0°C to 50 C C to 70 C I = –40 C to 85 C T = –40 C to 105 C C = 0° ° ° ° ° ° Packaging www.ti.com/packaging Optional: Tape and Reel T = Small Reel R = Large Reel No Markings = Tube or Tray Optional: Additional Features -EP = Enhanced Product ( 40°C to 105°C) -HT = Extreme Temperature Parts ( 55°C to 150°C) -Q1 = Automotive Qualified RF 430 CL 330 H A I RGE R XX Processor Family Device Designator Optional: Temperature Range

430 MCU Platform

Optional: Revision Optional: Tape and Reel Wireless Technology Optional: Additional Features H = High Frequency RF430CL330H-Q1 SLASE81 –JUNE 2015 www.ti.com Figure 7-1. Device Nomenclature

7.2 Documentation Support

The following documents describe the RF430CL330H device. Copies of these documents are available on the Internet at www.ti.com. SLAZ540 RF430CL330H Device Erratasheet. Describes the known exceptions to the functional specifications for the RF430CL330H device. SLOA187 Automating Bluetooth(R) Pairing With Near-Field Communications (NFC). This collaborative document is a follow up to a previously released specification by the NFC Forum titled NFC Forum Connection Handover Specification, which began to define the structure and sequence of interactions that enable two NFC-enabled devices to establish a connection using other wireless communication technologies. This application report explains how to implement the NFC Forum/Bluetooth SIG specification in an embedded application using the RF430CL330H dynamic NFC transponder.

7.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

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7.4 Trademarks

MSP430, E2E are trademarks of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc. Wi-Fi is a registered trademark of Wi-Fi Alliance. All other trademarks are the property of their respective owners.

7.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

7.6 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws.

7.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2015, Texas Instruments Incorporated Device and Documentation Support 39 Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

SLASE81 –JUNE 2015 www.ti.com

8 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

40 Mechanical, Packaging, and Orderable Information Copyright © 2015, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Links: RF430CL330H-Q1

www.ti.com 2-Dec-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples RF430CL330HTPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 CL330Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 2-Dec-2015 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF RF430CL330H-Q1 :

• Catalog: RF430CL330H NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

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