RF112 NXP | Alldatasheet
Document overview
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Technical content
Features
- Zero I/F operation in 2.4GHz (2.4-2.5GHz) Low and 5GHz (4.9-6GHz) High Industrial, Scientific, and Medical (ISM) Bands – Three independently operating RF sub-systems. – One dual band 1x2 MIMO transceiver, TRX – One dual band observation receiver, RO1 – One high band observation receiver, RO2 – Aggregate support for 1x Transmit, 4x Receive antenna operation
- Receiver features – Direct conversion, low noise and high dynamic range receive chain – High speed AGC interface (RSSI detector and RX gain control) to baseband – Analog baseband filters (20, 40 and 80 MHz modulation bandwidth) with on-chip calibration – Analog differential I/Q interface to baseband IC
- Transmitter features – Direct conversion with adjustable gain transmit chain – Analog baseband filter (20, 40 and 80 MHz modulation bandwidth) with on-chip calibration – Analog differential I/Q interface to baseband
- Flexible frequency generation system – 40 MHz crystal or external oscillator for frequency reference – Adjustable crystal load to tune for minimum frequency error – 4X multiplied input reference that can be routed to an output differential pair to be used as a low jitter
160 MHz reference by other devices in the system
– Independent synthesizers for each sub-system driven by a common reference
- Two interfaces for configuration and bi-directional data exchanges with the baseband IC – A low complexity high-speed custom LVDS bus (LLCP) – A traditional low-speed I2C bus
- Programmable digital core for transceiver control and calibration
- Auxiliary ADC support for calibration and external functions (voltage and temperature measurements)
- 64 pin QFN package NXP Semiconductors Document Number RF112 Data Sheet: Technical Data Rev. 1 Draft B, 05/2024 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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1 Introduction
analog baseband interfaces the bands cannot be used concurrently. Figure 1. RF112 Transceiver Simplified model chip has independent synthesizers for each sub-system driven from a common reference.
gain in receive mode should be controlled by the baseband IC. The receive chain has low noise and high dynamic range. The analog baseband filters have on-chip calibration and supports 20, 40, or 80 MHz modulation bandwidth. An internal crystal oscillator is implemented to enable usage of a low cost crystal. The reference frequency can be fine- tuned to minimize the frequency error. A LVDS clock output is included to provide a reference clock to the baseband chip. An auxiliary ADC is implemented for calibration purposes and to serve various external functions like power and temperature measurements. The two interfaces, a traditional low-speed I2C, and a low complexity high-speed custom LVDS buses are available for configuration and bi-directional data exchanges with the baseband. The high-speed LLCP interface can be used to provide a continuous stream of RF envelope detector samples after the LNA in each receiver chain. This allows the receiver AGC algorithm, located on the baseband chip, to observe the wideband signal level and optimize the receiver gain for best performance. The interface allows quick updates of the transmitter and receiver gains. This figure shows top level block diagram of the RF112 Transceiver. Introduction RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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Figure 2. RF112 Transceiver block diagram the time, to keep the LO-phase relations fixed after chip power-on. observation receiver synthesizers are kept running all the time. configuration, but with reduced performance.
and transmitters and of the other observation receiver. Figure 3. RF112 Digital Block Diagram
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2 Pin assignments
2.1 RF112 transceiver QFN layout diagrams
This figure shows the complete view of the RF112 QFN diagram.
65 GND
Figure 4. RF112 Transceiver QFN layout
2.2 Pinout list
This table provides the pinout listing for the RF112 Transceiver by bus. Table 1. Pinout list by bus
1 I VDD_RX1
3 I VDD_RX1
20 O VDD_BB1
Table continues on the next page...
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Table 1. Pinout list by bus (continued)
19 O VDD_BB1
21 O VDD_BB1
22 O VDD_BB1
39 I VDD_TRX2
45 I VDD_TRX2
30 O VDD_BB2
29 O VDD_BB2
31 O VDD_BB2
32 O VDD_BB2
11 I VDD_RO1
13 I VDD_RO1
16 O VDD_BB1
15 O VDD_BB1
17 O VDD_BB1
18 O VDD_BB1
37 I VDD_RO2
Table continues on the next page...
34 O VDD_BB2
33 O VDD_BB2
35 O VDD_BB2
36 O VDD_BB2
28 I VDD_BB2
25 I VDD_BB2
26 I VDD_BB2
27 I VDD_BB2
Table continues on the next page...
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- A 100 Ohms resistor should be placed between this pad and the other polarity pad.
- In normal mode should be pulled to ground.
- Application requires pull-down 10 +/-1% KOhm resistor.
- This pin can be left unconnected since they are configured as inputs with internal pull-down at reset.
- The 65th pin serves as a ground and thermal pad.
3 Electrical characteristics
3.1 Overall DC electrical characteristics
This section describes the ratings, conditions, and other characteristics.
3.1.1 Absolute maximum ratings
This table provides the absolute maximum ratings. Table 2. Absolute maximum ratings 1,2 Table continues on the next page...
Electrical characteristics
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 11
Table 2. Absolute maximum ratings 1,2 (continued)
- Functional operating conditions are given in this table are stress ratings only, and functional operation at the maximums is
not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
- Exposing device to Absolute Maximum Ratings conditions for long periods of time may affect reliability or cause permanent
3.1.2 Recommended operating conditions
This table provides the recommended operating conditions for this chip. Table 3. Recommended operating conditions Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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Table 3. Recommended operating conditions (continued)
40 MHz
Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 13
3.1.3 Power Sequencing
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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1.8 V VDD_DIG_IO
VDD_DIG_CORE Analog Supply Seconds Volts 0-5 ms 1.67 V 0.9 V Figure 5. RF112 Transceiver power sequencing
3.2 General specification
3.3 Receiver specification
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 15
5 th order, Butterworth Gain control fc = 10 to 40 MHz dcccxt dcccxt RXBB_OUT_I_P RXBB_OUT_Q_P RXBB_OUT_Q_N RXBB_OUT_I_N V2I RSSI RX_HB_IN HB LO I HB LO Q RX mixer HB LNA V2I RSSI RX_LB_IN LB LO I LB LO Q RX mixer LB LNA Figure 6. Block diagram of one receive chain. DC offset compensation algorithm has to be run in the baseband. observation receiver has no LB chain.
3.3.1 RxRF RSSI
20 MSps using sample clocks derived from the 160 MHz synthesizer, synchronized for
of 500-1000 ns in a periodic pattern. synthesizer, down-sampling and filtering is performed in the digital core. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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3.3.2 Rx BB interface
The Rx BB output shall be connected to the ADC input in the baseband chip as shown in below: BUF PCB TRX BB ADC agnd vlnp vcmout vinnR 1 R 1 R ESD R FSD R on R on R on R on R in_on R in_on R cm2 R cm2 R cm3 R cm3 R ESD C 1 C 1 C INFIX C INSW C INSWC INFIX RXBB_OUT_I_P avdd Sampling Capacitor Sampling Capacitor Sampling Switch Sampling Switch agnd agnd agnd RXBB_OUT_I_N Figure 7. Connection of Rx BB output of transceiver chip (TRX) to ADC input of mode voltage of the ADC is set by the Rx BB output buffer. ideal matching network with no losses. Table 4. Receiver specification correction and demodulation (data-aided equalization enabled). Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 17
Table 4. Receiver specification (continued)
4900 MHz, ChBW:
80 MHz, PVT
5300 MHz, ChBW:
6000 MHz, ChBW:
80 MHz, PV
RX total gain Gain into 100 Ω load. Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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given values are the products of Δ gd and the nominal channel BW, fchBW . Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 19
40 MHz channel
3.4 Transmitter specification
reconstruction filter, see figure below. the LO leakage remains low for all output power levels. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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Reconstr, filter 5 th order, Butterworth Ic = 10 to 40 MHz Mixer load Driver PA HB LO I HB LO Q HB TXBB_IN_I_P TX_HB_OUT TXBB_IN_Q_P TXBB_IN_Q_N TXBB_IN_I_N Mixer load TX mixer TX mixer Driver PA LB LO I LB LO Q LB TX_LB_OUT Figure 8. Detailed block diagram of the transmit chains
3.4.1 Tx BB interface
Figure 9. Tx BB interface BB input common mode and input signal level requirements. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 21
This table shows the transmitter specification. Unless otherwise specified, all values assume that the receivers are disabled. All RF signal levels are referred to the output of an ideal matching network with no losses. Table 5. Transmitter specification TX EVM RMS value over all subcarriers. All values are applicable at both -6 dBm and -26 dBm. Ideal IQ correction and demodulation (data-aided equalization enabled). Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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Table 5. Transmitter specification (continued) Figure 11 to Figure 15, also see spectrum maskFigure 10. Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 23
i.e. the given values are the products of Δ gd and the nominal channel BW, fchBW .
40 MHz channel BW
1.000 GHz ≤ f <
3.000 GHz
3.000 GHz ≤ f <
4.200 GHz
4.200 GHz ≤ f <
4.500 GHz
4.500 GHz ≤ f ≤
5.150 GHz
5.150 GHz < f <
6.500 GHz
6.500 GHz ≤ f <
7.500 GHz
Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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7.500 GHz ≤ f <
12.75 GHz
TX noise floor Spurs excluded.
100 MHz from the
Figure 10. Spectrum Mask RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 25
frequency (MHz) -43 dBr 20 30 10.25 9.75 -31 dBr -23 dBr 0 dBr Figure 11. Transmit spectrum mask, high band, 20MHz band width Figure 12. Transmit spectrum mask, low band, 20 MHz band width – at low output power limited by TX noise floor see examples in dashed ----. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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frequency (MHz) -43 dBr -41.2 dBr Pout = -24 dBm -39.2 dBrPout = -26 dBm P out = -24 dBm P out = -26 dBm 80 120 40.5 39.5 -31 dBr -23 dBr 0 dBr Figure 15. Transmit spectrum mask, high band, 80MHz band width – at low output power limited by TX noise floor see examples in dashed ----.
3.5 Isolation
This table shows the minimum isolation between RF pins. Table 6. isolation between RF pins Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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Table 6. isolation between RF pins (continued)
3.6 Frequency generation specification
Several LO-signals and clocks have to be generated independently in RF112 Transceiver. phases will be the same when returning to the same frequency after a frequency change. architecture is shown in the figure below. Figure 16. LO and clock generation block diagram generated from a high frequency VCO running at four or eight times the LO frequency. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 29
The observation receiver LOs are generated from synthesizers in the 2 to 4 GHz range followed by WBPLLs. The dual observation receivers use a ratio between the synthesizer and WBPLL of 3/2 or 3/4, while the HB only observation receiver uses a ratio of 5/2 to minimize the frequency overlap of the two VCOs. There are no requirements on phase coherence for the observation receivers. The figure below shows the Graphical illustration of the frequency planning. Y-axis has no relevance. TRX: fVCO = 19200.0 - 24000.0 MHz RO1 HB RO1 HB RO2 LB RO1 fVCO /2 1 6 3 3 .3 M H z 8 0 0 .0 M H z 8 3 3 .3 M H z9 8 0 .0 M H z 12 0 0 .0 M H z 19 6 0 .0 M H z 2 4 0 0 .0 M H z 2 9 4 0 .0 M H z 3 6 0 0 .0 M H z 3 9 2 0 .0 M H z 4 8 0 0 .0 M H z 4 9 0 0 .0 M H z 5 8 8 0 .0 M H z 7 2 0 0 .0 M H z 7 8 4 0 .0 M H z 9 6 0 0 .0 M H z 9 8 0 0 .0 M H z 6 0 0 0 .0 M H z 6 8 6 0 .0 M H z 8 4 0 0 .0 M H z 8 8 2 0 .0 M H z 1 0 8 0 0 .0 M H z 1 6 0 0 .0 M H z 1 6 6 6 .7 M H z 2 0 0 0 .0 M H z 2 0 8 3 .3 M H z 2 4 0 0 .0 M H z 2 5 0 0 .0 M H z 3 2 0 0 .0 M H z 3 3 3 3 .3 M H z 4 0 0 0 .0 M H z 416 6 .7 M H z 4 8 0 0 .0 M H z 5 0 0 0 .0 M H z 5 6 0 0 .0 M H z 5 8 3 3 .3 M H z 6 4 0 0 .0 M H z 6 6 6 6 .7 M H z 7 2 0 0 .0 M H z 7 5 0 0 .0 M H z 8 0 0 0 .0 M H z 8 3 3 3 .3 M H z 8 8 0 0 .0 M H z 9 16 6 .7 M H z 1 0 4 0 0 .0 M H z 1 0 8 3 3 .3 M H z 2 4 0 0 .0 M H z 3 0 0 0 .0 M H z 4 8 0 0 .0 M H z 6 0 0 0 .0 M H z 7 2 0 0 .0 M H z 9 0 0 0 .0 M H z 9 6 0 0 .0 M H z 2 0 0 0 .0 M H z 3 2 6 6 .7 M H z 4 0 0 0 .0 M H z 8 0 0 0 .0 M H z 8 16 6 .7 M H z 9 8 0 0 .0 M H z 1 0 0 0 0 .0 M H z 6 5 3 3 .3 M H z fVCO /4 fVCO /2 3 VCO /2 5f VCO /2 7f VCO /2 9f VCO /22f VCO 3f VCO 4f VCO 5f VCOfVCO 5f VCO /8 5f VCO /4 3f VCO /2 7f VCO /4 9f VCO /4 5f VCO /2 11f VCO /4 13f VCO /4f VCO /2 2f VCOfVCO 3f VCO /2 fVCO /4 3f VCO /8 f VCO /2fVCO /8 LB HB 2f VCO 3f VCO 5f VCO /2fVCO fVCO = 3200.0 - 4000.0 MHz RO2 fVCO = 1960.0 - 2400.0 MHz 0 1000 3000 4000 5000 6000 Frequency (MHz) 7000 8000 9000 10000 110002000 3f VCO /4 Figure 17. Graphical illustration of the frequency planning. Y-axis has no relevance. must be input through or generated by the crystal. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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40 MHz 0.9 V CMOS input clock LLCP XO XO Xl LVDS_160M_IO_P LVDS_160M_IO_N Clk IO RESTN Mode DILL x440 MHz 160 MHz Figure 18. Generation of synthesizer references and digital clocks This table shows the frequency generation specification. Table 7. Frequency generation specification
24.0 GHz
2400 MHz
4000 MHz
Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 31
Table 7. Frequency generation specification (continued)
50 MHz)
160 MHz
Table continues on the next page... RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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0.467 V1,2
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 33
Figure 19. LVDS Load Termination
- Please see the figure below that defines the Vcm and the VPP_SE versus VPP_DIFF
Figure 20. LVDS Signal Swing
3.7 Digital Interface
critical control, and one Lightweight LVDS Communication Protocol (LLCP) interface.
3.7.1 LLCP Interface Characteristics
decoding across both data and strobe pair. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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gain_data APB SLAVE MUX BASEBAND SoC LLCP INTERFACE RF112 LLCP INTERFACE READ RESP OR READ RSSI STREAM 8b10b DECODER DATA STROBE DECODER 8b10b ENCODER DATA STROBE ENCODER DOUT
640 Msps
320 Msps
Figure 21. LLCP communication interface
3.7.1.1 LLCP DC electrical characteristics
This table provides the DC electrical characteristics for the LLCP interface. Table 8. LLCP DC electrical characteristics (VDD_DIG_IO = 1.8V)4
- Test condition: Rload=100Ohm between padp and padn.
- Test condition: Rload=100Ohm between padp and padn
- For recommended operating conditions, see Table 3
- See figure "LLCP Input Waveform".
3.7.1.2 LLCP AC Timing Specifications
This table provides the LLCP AC electrical characteristics for LLCP interface. Table 9. LLCP AC Electrical Characteristics RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 35
- Test condition: Rload=100Ohm between padp and padn. 2. Measurement levels are 20-80% from output voltage. 3. See figure "LLCP LVDS Output Waveform" below. 4. See figure "Output Offset Voltage imbalance waveform" below. NOTE Skew between Data and Strobe: LLCP data and strobe pairs should be routed as 100 Ohm differential pairs with matched routing length to ensure equivalent propagation time for each differential signal. Propagation time mismatch should be checked at receiver; mismatched propagation delay beyond ±80ps between data and strobe signals might exceed capabilities of on-die timing compensation circuits and prevent correct operation of interface. -Vod +Vod Vocm typ = 1.2 VTtlh Tthl 250 mV to 450 mV -250 mV to -450 mV 0 mV differentialVid = |padp-padn| padn padp 80 % 80 % 20 % 20 %
Figure 22. LLCP LVDS Output Waveform Figure 23. LLCP Input Waveform RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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Figure 24. Output Offset Voltage Imbalance Waveform
3.8 Device start-up
The RF112 Transceiver is not equipped with any on-chip power-on-reset functionality. must not be released until the quality of that clock can be guaranteed. Table 10. Start-up specification LLCP (running at 100 Mbps) interfaces. calibration is reported in a register that can be polled over the LLCP or I2C interfaces. RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 37
The 160 MHz differential clock IO output can be enabled with a firmware command over the LLCP or I2C interfaces subsequent to DLL calibration.
3.9 Specification of auxiliary functions
3.9.1 Auxiliary ADC
The auxiliary ADC will be used for internal calibration and during test. Internal signals are routed to the AUX ADC via the analog test bus. External signals can be applied to the AUX ADC via the ATEST1 to ATEST4 pins, without using the analog testbus. The AUX ADC MUX has inputs directly connected to the ATEST pads. Both single-ended and differential external signals can be connected to the AUX ADC. This table shows an auxiliary ADC specification. Table 11. Auxiliary ADC specification
2 LSB
0.7 MHz
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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3.9.2 Temperature sensor
Temperature information is available in the regulators as a temperature dependent voltage. Most regulators have the possibility to apply a buffered version of this voltage onto the analog testbus. The voltage can then be measured with the AUX ADC, which makes it possible to measure the temperature at different locations on the chip. Output value can be processed by calibration unit to provide values in Celsius. This table shows the temperature sensor specification. Table 12. Temperature sensor specification LSB is referred to register content which is a 14-bit averaged ADC value. Output value LSB is referred to register content which is a 14-bit averaged ADC value.
4 Package information
4.1 Mechanical dimensions
table shows the package specification of the chip. Table 13. Package specification Table continues on the next page...
Package information
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 39
Table 13. Package specification (continued)
25 K/W
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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Figure 25. Mechanical dimensions of the RF112 RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024 NXP Semiconductors 41
5 Orderable part information
Table 14. Part encoding
6 Application
design for some specific pins.
6.1 External components
6.1.1 Crystal
the crystal, see the section Recommended operating conditions.
6.1.2 De-coupling
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6.2 PCB design
Table 15. PCB trace requirements VDD_TRX2 Maximum trace length until all three traces are joined < 1mm. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. XO Place crystal close to XI and XO ports. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor.
7 Revision history
This table summarizes revisions to this document. Table 16. Revision history A 09/2021 Initial NDA release. 1, Draft B 05/2024 • Replaced RF112L0H with RF112 everywhere in the document.
- Updated 'Features' section.
- Removed 'Table 1'.
- Updated 'Introduction' section.
- Removed one comment in 'Table 4'.
- Updated 'Section 3'.
- Updated 'Table 4'.
- Updated 'Section 3.3'.
- Updated 'Figure 6' caption.
- Updated 'Table 18'.
- Updated 'Figure 22'.
- Updated 'Figure 18'.
Revision history
RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024
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