RES11A40QDDFRQ1

RES11A-Q1 TI | Alldatasheet

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Technical content

RES11A-Q1 Automotive, Matched, Thin-Film Resistor Dividers With 1kΩ Inputs

1 Features

• AEC-Q200 Qualified for automotive applications: – Temperature: –40°C to +125°C
• Ratio = RIN : RG, RIN = 1kΩ (nominal)
• Highly precise ratio tolerance: ±0.05% (maximum)
• Low drift: ±2ppm/°C TCRratio (maximum)
• Functional safety-capable – Documentation available to aid functional safety system design

2 Applications

• Precision voltage divider, precision level translation
• Gain and attenuating amplifiers
• Difference amplifiers with high CMRR
• Discrete instrumentation amps with high gain accuracy
• Fully differential amplifiers with high gain accuracy
• Pinpoint comparator threshold setting

3 Description

The RES11A-Q1 is a matched pair of resistive dividers, implemented in thin-film SiCr with Texas Instruments' modern, high-performance, analog CMOS process. The device has a nominal input resistance of 1k Ω, for low thermal and current noise, and is available in several nominal ratios to meet a wide array of system needs. Use the RES11A-Q1 in an inverse gain configuration by simply rotating the device placement by 180°. This feature supports layout reuse and increases flexibility for applications such as discrete instrumentation or difference amplifier implementations. The RES11A-Q1 series features high ratio-matching precision, with the measured ratio of each divider within ± 0.05% (±500ppm) of the nominal. This precision is maintained over the temperature range, with a maximum ratio drift of only ±2ppm/°C. Additionally, the biased long-term stability of the device has been proven through thorough characterization. The RES11A-Q1 is automotive qualified under AEC- Q200 temperature grade 1. The temperature range is specified from –40°C to +125°C. The device is offered in an 8 ‑pin, SOT‑23-THIN package, with a body size of 2.9mm × 1.6mm (body size is a nominal value and does not include pins).

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) RES11A-Q1 DDF (SOT-23-THIN, 8) 2.9mm × 2.8mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Device Information PART NUMBER NOMINAL RATIO RES11A10-Q1 1:1 RES11A15-Q1 1:1.5 RES11A16-Q1 1:1.667 RES11A20-Q1 1:2 RES11A25-Q1 1:2.5 RES11A30-Q1 1:3 RES11A40-Q1 1:4 RES11A50-Q1 1:5 RES11A90-Q1 1:9 RES11A00-Q1 1:10 RIN2 RG2 RIN1 RG1 Substrate RIN1 RMID1 RG1 GND/SUB GND/SUB RIN2 RMID2 RG2 Functional Block Diagram Common-mode Rejection Ratio (dB) Devices (%) 85 90 95 100 105 110 115 120 125 130 10% 15% 20% 25% 30% RES11A40, G = 4 Excellent Ratio Matching for Best CMRR RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. DDF Package, 8-Pin SOT-23-THN (Top View) Table 4-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. GND/SUB 4, 8 Ground Substrate bias connection. Only bias one GND/SUB pin. Float the other GND/SUB pin to prevent current return paths from forming through the substrate. See also Section 7.4. RG1 3 Input Gain resistor connection for divider 1 RG2 5 Input Gain resistor connection for divider 2 RIN1 1 Input Input resistor connection for divider 1 RIN2 7 Input Input resistor connection for divider 2 RMID1 2 Output Center tap of divider 1 RMID2 6 Output Center tap of divider 2 www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: RES11A-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCM Maximum sustained common mode voltage (any pin to GND/SUB) –85 85 V ∆VDMAX Maximum instantaneous overload voltage per divider (RINx pin to RGx pin)(2) (3) RES11A10 –77.0 77.0 V RES11A15 –64.2 64.2 RES11A16 –63.0 63.0 RES11A20 –57.8 57.8 RES11A25 –89.9 89.9 RES11A30 –102.7 102.7 RES11A40 –96.3 96.3 RES11A50 –94.6 94.6 RES11A90 –128.4 128.4 RES11A00 –135 135 TA Ambient temperature –55 150 °C TJ Junction temperature –55 150 °C Tstg Storage temperature –55 175 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Maximum instantaneous voltage permitted under transient conditions. Avoid sustained operation at these voltage levels because the resulting self-heating causes TJ to exceed 150°C. (3) Refer to Section 7.4.1 and Section 8.3 for more information about per-resistor voltage and current limitations.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q200-002 ±1200 V RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VRECMAX Maximum sustained divider voltage, dc (10 years at TA = 25°C)(1) (2) RES11A10 –17.9 17.9 V RES11A15 –14.9 14.9 RES11A16 –14.3 14.3 RES11A20 –13.4 13.4 RES11A25 –20.8 20.8 RES11A30 –23.8 23.8 RES11A40 –22.4 22.4 RES11A50 –21.4 21.4 RES11A90 –29.8 29.8 RES11A00 –32.8 32.8 Maximum sustained divider voltage, ac (≥50Hz, 10 years at TA = 25°C)(1) (2) RES11A10 –24.4 24.4 VRMS RES11A15 –20.4 20.4 RES11A16 –20.0 20.0 RES11A20 –18.3 18.3 RES11A25 –28.5 28.5 RES11A30 –32.6 32.6 RES11A40 –30.6 30.6 RES11A50 –30.0 30.0 RES11A90 –40.7 40.7 RES11A00 –44.8 44.8 TA Ambient temperature –40 125 °C (1) Assumes RθJA = 156.2°C/W. Applies whether the specified voltage is applied across a single divider, or both dividers simultaneously. Adhere to the limitations in Absolute Maximum Ratings. (2) Refer to GUID-B2B50001-4032-4B8B-9DC6-7BD6A1AAB503#GUID-B2B50001-4032-4B8B-9DC6-7BD6A1AAB503 and GUID- D2FC8D84-6C94-418C-9C88-DE8CD853B18A#GUID-D2FC8D84-6C94-418C-9C88-DE8CD853B18A for more information about per- resistor voltage and current limitations.

5.4 Thermal Information

THERMAL METRIC(1) RES11A-Q1 UNITDDF (SOT-23-THIN)

8 PINS

RθJA Junction-to-ambient thermal resistance 156.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 77.0 °C/W RθJB Junction-to-board thermal resistance 73.7 °C/W ψJT Junction-to-top characterization parameter 4.5 °C/W ψJB Junction-to-board characterization parameter 73.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: RES11A-Q1

5.5 Electrical Characteristics

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INITIAL RESISTANCE Gnom Nominal ratio (RGx / RINx) RES11A10 1 V/V RES11A15 1.5 RES11A16 1.667 RES11A20 2 RES11A25 2.5 RES11A30 3 RES11A40 4 RES11A50 5 RES11A90 9 RES11A00 10 tD1 Ratio tolerance of divider 1(1) (5) (RG1 / RIN1) / Gnom – 1 RES11A10 –500 ±59 500 ppm RES11A15 –500 ±41 500 RES11A16 –500 ±97 500 RES11A20 –500 ±52 500 RES11A25 –500 ±66 500 RES11A30 –500 ±62 500 RES11A40 –500 ±76 500 RES11A50 –500 ±107 500 RES11A90 –500 ±72 500 RES11A00 –500 ±117 500 tD2 Ratio tolerance of divider 2(1) (5) (RG2 / RIN2) / Gnom – 1 RES11A10 –500 ±68 500 ppm RES11A15 –500 ±37 500 RES11A16 –500 ±81 500 RES11A20 –500 ±40 500 RES11A25 –500 ±50 500 RES11A30 –500 ±58 500 RES11A40 –500 ±70 500 RES11A50 –500 ±81 500 RES11A90 –500 ±93 500 RES11A00 –500 ±55 500 tM Matching tolerance of dividers 1 and 2(5) tD2 – tD1 RES11A10 –1000 ±29 1000 ppm RES11A15 –1000 ±31 1000 RES11A16 –1000 ±42 1000 RES11A20 –1000 ±41 1000 RES11A25 –1000 ±42 1000 RES11A30 –1000 ±32 1000 RES11A40 –1000 ±38 1000 RES11A50 –1000 ±67 1000 RES11A90 –1000 ±89 1000 RES11A00 –1000 ±65 1000 tabs Absolute tolerance (per resistor)(2) (5) (Rx / Rxnom) – 1(3) –12 ±2 12 % Absolute tolerance span MAX (tabsRIN1, tabsRG1, tabsRIN2, tabsRG2) – MIN (tabsRIN1, tabsRG1, tabsRIN2, tabsRG2) 65 ppm RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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5.5 Electrical Characteristics (continued)

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESISTANCE DRIFT TCRabs Absolute temperature coefficient of resistance (per resistor)(4) (ΔRx / Rx(25°C)) / ΔTA TA = –40C to +125°C 18 ppm/°C TA = –40C to –15C 35 ppm/°C TA = –15C to +65°C 23 ppm/°C TA = 65C to 125°C 3.5 ppm/°C TCRratio Divider temperature coefficient of resistance (per divider)(4) ΔtDx / ΔTA, TA = –40C to +125°C –2 ±0.2 2 ppm/°C TCMM Matching temperature coefficient of resistance(4) (5) ΔtM / ΔTA, TA = –40C to +125°C ±0.05 ppm/°C VCRabs Absolute voltage coefficient of resistance (per resistor)(2) (4) (5) ΔRx / ΔVRx, VDx = –VRECMAX to VRECMAX ±0.24 Ω/V VCRratio Divider voltage coefficient of resistance (per divider)(4) (5) ΔtDx / ΔVDx, VDx = –VRECMAX to VRECMAX ±0.4 ppm/V VCRM Matching voltage coefficient of resistance(4) (5) (ΔtD2 – ΔtD1) / ΔVDx, VDx = –VRECMAX to VRECMAX ±0.24 ppm/V ARBITRARY MATCHING RG mismatch between dividers, absolute(5) (RG2 – RG1) / RGnom ±20 ppm RG mismatch between dividers, ratiometric(5) (RG1 / RG2) – 1, and (RG2 / RG1) – 1 ±20 ppm ((RG1 / RIN2) / Gnom) – 1, and (RG2 / RIN1) / Gnom) – 1 ±86 (RG1 / (RG2 + RIN2)) / (Gnom/(Gnom+1)) – 1, and (RG2 / (RG1 + RIN1)) / (Gnom/(Gnom+1)) – 1 ±32 RIN mismatch between dividers, absolute(5) (RIN2 – RIN1) / RINnom ±28 ppm RIN mismatch between dividers, ratiometric(5) (RIN1 / RIN2) – 1, and (RIN2 / RIN1) – 1 ±27 ppm (RIN1 / RG2) × (Gnom) – 1, and (RIN2 / RG1) × (Gnom) – 1 ±86 (RIN1 / (RG2 + RIN2)) × (Gnom+1) – 1, and (RIN2 / (RG1 + RIN1)) × (Gnom+1) – 1 ±68 End-to-end mismatch between dividers, absolute(5) ((RG2 + RIN2) – (RG1 + RIN1)) / (RINnom + RGnom) ±18 ppm tE2E End-to-end mismatch between dividers, ratiometric(5) ((RG2 + RIN2) / (RG1 + RIN1)) – 1 ±18 ppm IMPEDANCE CIN Pin capacitance(4) RINx to GND/SUB 2.5 pFRGx to GND/SUB 1.6 RMIDx to GND/SUB 3.5 Crosstalk (RMID1 to RMID2)(4) Substrate biased to GND f = 10kHz –100 dB f = 1MHz –64 Substrate floating f = 10kHz –98 f = 1MHz –62 –3dB bandwidth(4) Substrate biased to GND(6) RES11A10 17 MHz RES11A15, RES11A16 14 MHz RES11A20, RES11A25, RES11A30, RES11A40 10.5 MHz RES11A50, RES11A90, RES11A00 9.4 MHz www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: RES11A-Q1

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMRR Common-mode rejection ratio (7) RES11A10 66.0 102.0 dB RES11A15 68.0 96.2 RES11A16 68.5 98.6 RES11A20 69.5 99.1 RES11A25 70.9 99.6 RES11A30 72.0 101.7 RES11A40 74.0 98.5 RES11A50 75.6 102.1 RES11A90 80.0 98.4 RES11A00 80.8 105.0 (1) Relation of RG1 / RIN1 or RG2 / RIN2 to nominal ratio. (2) Relation of RG1, RIN1, RG2, or RIN2 to nominal resistance. (3) The specification is the result of this expression, given as a percentage (multiplied by 100%). (4) Specified by characterization. (5) Error term is zero-mean. Treat the typical value reported here as one standard deviation (±1σ) for error analysis purposes. (6) If higher bandwidth is required, leaving the substrate floating or using a guard buffer to drive the substrate can modestly increase bandwidth. (7) The specification is the calculated CMRR when implemented in a difference amplifier configuration with an ideal op-amp, such that the only source of common-mode error is the resistor network. See the Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note for more information. Effects over frequency are not included. If the circuit is configured in an attenuating gain, this result changes accordingly. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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5.6 Typical Characteristics

at TA = 25°C (unless otherwise noted) tD1 (ppm) Devices (%) -150 -100 -50 0 50 100 150 RES11A40 RES11A40-Q1 ATE n = 1411, 1 lot Figure 5-1. tD1 Distribution tD2 (ppm) Devices (%) -50 -25 0 25 50 75 100 125 150 175 200 225 250 RES11A40 RES11A40-Q1 ATE n = 1411, 1 lot Figure 5-2. tD2 Distribution tM (ppm) Devices (%) -50 -25 0 25 50 75 100 125 150 175 200 225 250 RES11A40 RES11A40-Q1 ATE n = 1411, 1 lot Figure 5-3. tM Distribution Absolute Tolerance Span (ppm) Devices (%) 0 10 20 30 40 50 60 70 80 90 100 10% 12% All ratios Extended validation n = 314 Figure 5-4. Absolute Tolerance Span Distribution All ratios Extended validation n = 628 Figure 5-5. tDx Distribution tM (ppm) Devices (%) -100 -80 -60 -40 -20 0 20 40 60 80 100 10% 12% 14% All ratios Extended validation n = 314 Figure 5-6. tM Distribution www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: RES11A-Q1

5.6 Typical Characteristics (continued)

at TA = 25°C (unless otherwise noted) Temperature (C) Change in RIN (%) -50 -25 0 25 50 75 100 125 -2.5 -1.5 -0.5 0.5 1.5 RES11A10 RES11A15 RES11A16 RES11A20 RES11A25 RES11A30 RES11A40 RES11A50 RES11A90 RES11A00 Best fit, normalized to RINx(25°C) Figure 5-7. RINx vs Temperature Temperature (C) Change in RG (%) -50 -25 0 25 50 75 100 125 -2.5 -1.5 -0.5 0.5 1.5 RES11A10 RES11A15 RES11A16 RES11A20 RES11A25 RES11A30 RES11A40 RES11A50 RES11A90 RES11A00 Best fit, normalized to RGx(25°C) Figure 5-8. RGx vs Temperature tDx Drift Error (ppm/°C) Dividers (%) 10% 12% 14% 16% 18% 20% 22% RES11A10-Q1 n = 58, 1 lot Figure 5-9. TCRratio Temperature Coefficient Distribution tM Drift Error (ppm/°C) Devices (%) 10% 12% 14% 16% 18% RES11A10-Q1 n = 29, 1 lot Figure 5-10. TCRM Temperature Coefficient Distribution tDx Drift Error (ppm/°C) Dividers (%) 10% 12% 14% 16% RES11A16-Q1 n = 62, 1 lot Figure 5-11. TCRratio Temperature Coefficient Distribution tM Drift Error (ppm/°C) Devices (%) 10% 12% 14% 16% 18% RES11A16-Q1 n = 31, 1 lot Figure 5-12. TCRM Temperature Coefficient Distribution RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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at TA = 25°C (unless otherwise noted) tDx Drift Error (ppm/°C) Dividers (%) 10% 12% 14% 16% RES11A40-Q1 n = 186, 3 lots Figure 5-13. TCRratio Temperature Coefficient Distribution tM Drift Error (ppm/°C) Devices (%) 10% 12% 14% 16% 18% RES11A40-Q1 n = 93, 3 lots Figure 5-14. TCRM Temperature Coefficient Distribution Temperature (°C) Change in tD (ppm) -55 -25 5 35 65 95 125 150 -40 -35 -30 -25 -20 -15 -10 RES11A30-Q1 Normalized to tDx(25°C), n = 54, 1 lot Figure 5-15. tD vs Temperature Temperature (°C) Change in tM (ppm) -55 -25 5 35 65 95 125 150 RES11A30-Q1 n = 27, 1 lot Figure 5-16. tM vs Temperature Voltage (V) Resistance () 5 10 15 20 25 30 35 40 969.75 970 970.25 970.5 970.75 971 RIN1 Calculated RIN2 Calculated RIN1 Measured RIN2 Measured RES11A40-Q1 Normalized to Rx(5V), n = 1 Figure 5-17. RINx vs Divider Voltage Voltage (V) Resistance () 5 10 15 20 25 30 35 40 3878.5 3879 3879.5 3880 3880.5 3881 3881.5 3882 3882.5 3883 3883.5 RG1 Calculated RG2 Calculated RG1 Measured RG2 Measured RES11A40-Q1 Normalized to Rx(5V), n = 1 Figure 5-18. RGx vs Divider Voltage www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: RES11A-Q1

at TA = 25°C (unless otherwise noted) Voltage (V) Resistance () 5 10 15 20 25 30 35 40 -0.1 -0.075 -0.05 -0.025 0.025 0.05 0.075 0.1 0.125 0.15 RIN1 Error RIN2 Error RES11A40-Q1 RINx actual – RINx predicted, normalized to Rx(5V) Figure 5-19. RINx Actual-to-Expected Error vs Divider Voltage Voltage (V) Resistance () 5 10 15 20 25 30 35 40 -0.5 -0.25 0.25 0.5 RG1 Error RG2 Error RES11A40-Q1 RGx actual – RGx predicted, normalized to Rx(5V) Figure 5-20. RGx Actual-to-Expected Error vs Divider Voltage Voltage (V) Ratio Error, tDx (ppm) 5 10 15 20 25 30 35 40 -150 -120 -90 -60 -30 tD1 Measured tD2 Measured tD1 Calculated tD2 Calculated RES11A40-Q1 Normalized to tDx(5V), n = 1 Figure 5-21. tDx vs Divider Voltage Voltage (V) Ratio Mismatch, tM (ppm) 5 10 15 20 25 30 35 40 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 tM Measured tM Calculated RES11A40-Q1 Normalized to tM(5V), n = 1 Figure 5-22. tM vs Divider Voltage Temperature (°C) Device Rated Power (mW) -50 -25 0 25 50 75 100 125 150 100 150 200 250 300 350 400 RES11A10 RES11A15 RES11A16 RES11A20 RES11A25 RES11A30 RES11A40 RES11A50 RES11A90 RES11A00 RθJA = 156.2°C/W IRx = dc continuous bias limit Figure 5-23. Device Rated Power vs Temperature Temperature (°C) Divider Voltage (V) -50 -25 0 25 50 75 100 125 150 RES11A10 RES11A15 RES11A16 RES11A20 RES11A25 RES11A30 RES11A40 RES11A50 RES11A90 RES11A00 VDIV1 = VDIV2 = VRECMAX Figure 5-24. Maximum Recommended Divider Voltage vs Ambient Temperature RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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at TA = 25°C (unless otherwise noted) Frequency (MHz) Normalized Gain (dB) 0.5 1 10 50 -15 -12 RES11A10 RES11A15 RES11A16 RES11A20 RES11A25 RES11A30 RES11A40 RES11A50 RES11A90 RES11A00 VRINx = VTEST, VRGx = 0V Figure 5-25. Bandwidth vs Frequency, RINx Frequency (MHz) Normalized Gain (dB) 0.5 1 10 50 -15 -12 RES11A10 RES11A15 RES11A16 RES11A20 RES11A25 RES11A30 RES11A40 RES11A50 RES11A90 RES11A00 VRGx = VTEST, VRINx = 0V Figure 5-26. Bandwidth vs Frequency, RGx Frequency (Hz) Crosstalk (dB) -140 -120 -100 -80 -60 -40 -20 100 1k 10k 100k 1M 10M Floating Substrate Grounded Substrate RES11A40-Q1 Figure 5-27. Crosstalk vs Frequency Frequency (Hz) Common-mode Rejection Ratio (dB) 100 105 10 100 1000 10000 100000 RES11A40-Q1 Difference amplifier with OPA210 Figure 5-28. CMRR vs Frequency www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: RES11A-Q1

6 Parameter Measurement Information

6.1 DC Measurement Configurations

An example of the circuit configuration used for dc measurements is shown in Figure 6-1. Voltage VDx refers to the voltage across a given divider, such as V D1 for divider 1. Voltage V Rx refers to the voltage across a given resistor, such as VRIN1 for RIN1 or VRG1 for RG1. RES11A-Q1 RIN1 RG2 RIN2RG1 – VD1 VRIN1 VRG1 Figure 6-1. DC Measurement Terminology for Divider 1 When the RES11A-Q1 is used to set the gain of an op amp (shown in Figure 6-2 ), the ratio of the resistors in a divider sets the amplifier gain such that V OUT = –V IN × R G / R IN. Discrete difference-amplifier and instrumentation-amplifier circuits are variations on this use case. Typical and maximum parameter values for ratio tolerance (t D1, t D2) are expressed in terms of R Gx / R INx to simplify calculations for these circuits. See Section 7.3.1 for more detailed discussion of these error terms. GND VIN RIN RG VOUT Figure 6-2. Amplifier Gain Circuit Another valid use case of the RES11A-Q1 is a simple voltage divider. An example is shown in Figure 6-3. For this implementation, the midpoint voltage VMID is equal to the input voltage VD multiplied by RIN / (RIN + RG). VMID RG RIN GND VD Figure 6-3. Voltage-divider circuit While calculation of the error for a voltage divider use case is slightly more complex, the gain error of a voltage divider circuit constructed with the RES11A-Q1 is always less than that of an amplifier gain circuit implemented with the same device. Put another way, the values of t D1 or tD2 specified for the RES11A-Q1 in gain circuits are overly conservative for voltage-divider circuits. Refer to Section 8.1.2 for detailed discussion and examples. Figure 6-4 shows the circuit configuration used for CMRR calculations. For an ideal amplifier with no offset and infinite CMRR, the effective circuit CMRR is entirely a function of the matching of the resistors. See Section 8.1.3.1 and the Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note for more information. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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VIN– RIN1 RG2 RIN2RG1 VOUT GND Figure 6-4. CMRR Calculation Reference Schematic

6.2 AC Measurement Configurations

Figure 6-5 shows the circuit configuration used for capacitance measurements. For the RES11A-Q1, a 1M Ω RKNOWN resistance and 10pF C KNOWN capacitance are used. The circuit creates an impedance divider; the resulting gain-vs-frequency relationship is used to calculate the parasitic capacitance in parallel with the resistor under test (in this case, RIN1). Calibration with an empty socket is performed to account for board parasitics. The ac source is swept from 100Hz to 50MHz. Network Analyzer RES11A-Q1 RIN1 RG2 RIN2RG1 GND GNDRKNOWN CKNOWN GND VSOURCE GND GND/SUB Figure 6-5. Capacitance Measurement Reference Schematic Figure 6-6 shows the circuit configuration that is used for bandwidth measurements. The ac source is swept from 100kHz to 500MHz. Network Analyzer RES11A-Q1 RIN1 RG2 RIN2RG1 GND GND GND GND VSOURCE GND/SUB Figure 6-6. Bandwidth Measurement Reference Schematic www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: RES11A-Q1

Figure 6-7 shows the circuit configuration used for crosstalk measurements. The ac source is swept from 100Hz to 100MHz. Network Analyzer RES11A-Q1 RIN1 RG2 RIN2RG1+ GND GND GND GND VSOURCE GND/SUB Figure 6-7. Crosstalk Measurement Reference Schematic

6.3 Error Notation and Units

This document uses the form Paramactual = Param nominal × 1 + t Param (1) to describe the error of many of the RES11A-Q1 parameters in a ratiometric manner. This expression expands to Paramactual = Param nominal + Paramnominal × t Param (2) Thus, the difference or absolute error between the actual and nominal value of a given parameter is Paramactual – Param nominal = Param nominal × t Param (3) Paramactual shares the same units as Paramnominal, such as V/V or Ω/Ω when describing circuit gain, while t Param is unitless by default. Because the error tolerances of the RES11A-Q1 are so low, t Param errors are typically expressed in units of ppm, by multiplying the error by 10 6. To convert tParam from ppm back to a unitless decimal value for error calculations, divide the tValue by 106. Refer to Section 7.3.1 for an example of this. As many of the RES11A-Q1 error terms (such as gain error and gain temperature coefficients) scale according to the nominal gain, this notation provides a convenient way to standardize values across the various RES11A- Q1 ratios. When converting ratiometric errors to absolute errors (or vice versa) for error analysis calculations, be cautious of notation and remember to scale t Param errors by Paramnominal when appropriate. Section 9.7 includes a list of the various error terms that appear throughout the document, and a summary or definition of each. In some cases, such as when describing divider ratio or gain, the same equation applies to both divider 1 and divider 2. In this case, a notation of Param x is used, where x is either 1 or 2. For example, when generically describing ratio error, Gx = G nom × 1 + t Dx (4) For the ratio error of divider 2 specifically, G2 = G nom × 1 + t D2 (5) RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The RES11A-Q1 consists of four precision thin-film SiCr resistors, arranged to form two matched dividers. The device has two input resistors, R IN1 and R IN2, both nominally 1kΩ. The device also has two gain resistors, R G1 and RG2, with values that depend on the nominal ratio (R Gx / R INx) of the RES11A-Q1 device in question. The resistors are arranged with RIN1 and RG1 in series to form the first divider, and RIN2 and RG2 in series to form the second divider. Two GND pins are also provided to bias the device substrate.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Ratiometric Matching for Low Gain Error

The RES11A-Q1 is commonly used to establish the feedback path and set the gain of an amplifier circuit, or as a voltage divider to level-shift input signals. In both cases, the ratio of the resistors of the circuit describe the nominal circuit transfer function. Because the resistors of a given RES11A-Q1 are interdigitated and come from the same area of a silicon wafer, many of the absolute error terms of the resistors cancel out when calculating the actual or effective circuit transfer function. Detailed mathematical analyses and proofs are provided in Section 7.3.1.1, but for most use cases, the error terms reported in Electrical Characteristics are directly used to calculate the associated maximum and typical circuit gain error. The RES11A-Q1 is specified with a maximum divider ratio tolerance of 500ppm, effectively meaning that the relationship between the actual divider ratio G x and nominal ratio G nom of a given divider x is described by the following: Gx = G nom × 1+tDx (6) such that tDx ≤ 500ppm. For example, a RES11A40-Q1 has a nominal gain of G nom = 4. If a particular unit has tD1 = 130ppm and tD2 = –40ppm, the effective gains G1 and G2 are calculated as G1 = G nom × 1+tD1 = 4 × 1+0.00013 = 4.00052 (7) G2 = G nom × 1+tD2 = 4 × 1–0.00004 = 3.99984 (8) The RES11A-Q1 is specified with a maximum divider matching tolerance of 1000ppm, meaning that the relationship between the ratio of divider 1 (G1) and ratio of divider 2 (G2) is described by the following: tM = t D2 – t D1 = G2 – G 1 Gnom (9) By definition, |tM| ≤ 1000ppm. As a result of the interdigitation of the two dividers, the actual typical magnitude of tM is about an order of magnitude less than this maximum value, depending on the specific RES11A-Q1 device. This value is used to approximate the common-mode rejection ratio (CMRR) when implementing a difference www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: RES11A-Q1

amplifier circuit. For example, typical t M for the RES11A40-Q1 is approximately 38ppm, and the typical CMRR is 98.5dB.

7.3.1.1 Absolute and Ratiometric Tolerances

The resistors of the RES11A-Q1 are described by the following equations: RIN1 = R INnom × 1+tabsRIN1 = R INnom × 1+tRIN1 × 1+tSiCr (10) RIN2 = R INnom × 1+tabsRIN2 = R INnom × 1+tRIN2 × 1+tSiCr (11) RG1 = R Gnom × 1+tabsRG1 = R Gnom × 1+tRG1 × 1+tSiCr (12) RG2 = R Gnom × 1+tabsRG2 = R Gnom × 1+tRG2 × 1+tSiCr (13) RINnom and RGnom are the nominal values of each resistor. The parameter tabs is an error term that describes the absolute tolerance of the RES11A-Q1 resistor in question, such that |t abs| ≤ 12%. For example, a nominally 1k Ω resistor with tabs = 10% actually measures 1.1k Ω. This error is analogous to the specified absolute tolerance of most single-element resistors, or the end-to-end tolerance of more specialized resistor dividers. Note The RES11A-Q1 is not a laser-trimmed device. Each ratio of the RES11A-Q1 features a unique die specifically optimized for that ratio, providing the precise matching and consistent thermal characteristics necessary to achieve extremely low drift. The absolute tolerance is dominated by the variation in the SiCr resistivity, tSiCr. The four resistors of a given RES11A-Q1 are interdigitated and come from the same area of the wafer; therefore, tSiCr is effectively the same for each of the four resistors, although tSiCr varies on a part-to-part basis. The following examples show that when each divider is considered in ratiometric terms, the tSiCr error terms drop out. Parameter tRx is an residual error term that describes the remaining effective tolerance of each resistor of the given RES11A-Q1 device after accounting for the universal tSiCr. RGx RINx = RGnom × 1+tRGx × 1+tSiCr RINnom × 1+tRINx × 1+tSiCr RGnom × 1+tRGx RINnom × 1+tRINx = G nom × 1+tRGx 1+tRINx = G x (14) RINx RINx + R Gx = RINnom × 1+tRINx × 1+tSiCr RINnom × 1+tRINx × 1+tSiCr + R Gnom × 1+tRGx × 1+tSiCr RINnom × 1+tRINx RINnom × 1+tRINx + R Gnom × 1+tRGx (15) The individual values of t RG1, tRG2, tRIN1, and tRIN2 describe the tolerance of each individual resistor, but are not independent variables in a Gaussian sense. Rather, the matching of these values to each other (by design) is used to achieve highly stable ratiometric relationships between the resistors, giving an effective ratio with an extremely low error. The limits of tDx for the RES11A-Q1 are enforced by precise parametric testing in production, with Kelvin connections used to better reject potential sources of error. Because the resulting t D1 and t D2 values are more randomized error terms, t D1 and t D2 can be treated as independent Gaussian distributions, making these variables much more useful for error analyses. Single-element resistors do not have an equivalent to t Dx, because no part-to-part matching is considered other than the gradeout limit. In other divider data sheets, the equivalent of tDx is often called ratio tolerance. Because any devices that do not meet these criteria are screened out at final test, these equations can technically be used with Equation 14 to prove additional relationships (such as effective maximum limits) between the values of tRx for a given device. This exercise ultimately gives overly conservative results, however. For more realistic statistical analysis with root-sum-of-squares methods, the Arbitrary Matching section of the Electrical Characteristics table provides measured standard deviations for some additional resistor-to-resistor RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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7.3.2 Ratiometric Drift

The ratiometric matching of the RES11A-Q1 provides a benefit not just for initial conditions, but also when considering parametric drift. The resistors must be considered individually, in absolute terms, and ratiometrically to each other, in matched terms. The absolute temperature coefficients of each resistor show strong correlation, with the coefficient of R IN1 comparable to that of R IN2 and the coefficient of R G1 comparable to that of R G2. The absolute temperature coefficient (in Ω/°C) of each R G is approximately G nom times greater than that of the comparable R IN; therefore, the normalized absolute temperature coefficient (in ppm/°C) of every resistor is approximately the same. The resistors of the RES11A-Q1 are interdigitated, and occupy a small footprint; thus, the die temperature of the device is effectively common to each of the four resistors. As the temperature changes, each resistor experiences a similar temperature rise. The resistors have very similar temperature coefficients; therefore, the ratio of R G to R IN is well preserved. For example, the RES11A40-Q1 has a typical absolute temperature coefficient of approximately 18ppm/°C for R IN or R G. When considered in ratiometric terms, the typical temperature coefficient of t D1 or t D2 is ±0.2ppm/°C, and the temperature coefficient of t M is ±0.05ppm/°C. Ambient temperature, humidity, heatsinking, board cleanliness, and other related factors can impact the settling time of the RES11A-Q1, so validation testing is performed in a low-humidity environment with rigorous board cleaning procedures.

7.3.2.1 Long-Term Stability

Biased long-term drift testing was performed on the automotive-grade RES11A-Q1 using a temperature- controlled oil bath. The devices under test were first soldered to the bias boards using a reflow oven, per J-STD-020E, then were cleaned in an ultrasonic bath. The boards underwent an additional bake step before placement in the oil bath. The ambient bath temperature was fixed at 46°C and each divider was biased to a fixed voltage of 15V. Devices were allowed to soak for 45 minutes, to achieve thermal equilibrium, before measurements commenced. An integration circuit was used to measure current through each divider, and thus identify any changes in end- to-end resistance. A delta measurement between the midpoint pins of the dividers provided a high-resolution measurement of divider-to-divider shifts for the same DUT, allowing approximation of shifts in t M. Additional measurements between the midpoints and ground were performed, to be used in conjunction with the previous measurements for calculation of shifts in t Dx. The bias voltage was also measured for each channel. These measurements were implemented using multiplexed digital multimeters (DMMs). RES11A-Q1 RIN1 RIN2 RG2RG1 – VBIAS1 IVC1 Bias VIVC1 – VMID1-MID2 VMID2 – VBIAS2 IVC2 Bias VIVC2 – VMID1 Figure 7-1. RES11A-Q1 Long-term Drift Schematic (Simplified) Measurements were recorded at intervals ranging from 15 minutes to 24 hours, with run durations from 1000hrs to 3600hrs. In some instances, measurement data collection was interrupted due to external factors, such as mandatory system updates to the computer used for the measurements. In these instances, the bias voltage and temperature control were not disturbed due to the use of uninterruptible power supply (UPS) backups for the biasing circuitry; there was simply an absence of recorded data from the DMMs. Plots presented are normalized to the respective run mean. www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: RES11A-Q1

Time (hrs) Change In tD (ppm) 0 500 1000 1500 2000 2500 3000 -20 -15 -10 Figure 7-2. RES11A40-Q1 Long-term Drift, tD Time (hrs) Change In tM (ppm) 0 500 1000 1500 2000 2500 3000 -20 -15 -10 20 Figure 7-3. RES11A40-Q1 Long-term Drift, tM Accurate measurement of errors in the single-digit ppm range requires careful consideration of circuit parasitics. Noise sources can easily contaminate or dominate measurements. While external filters at the measurement nodes assist with high-frequency noise, the thermal noise of the filter resistors contributes low-frequency noise, so a series of design and architectural tradeoffs are required. Ongoing development of biasing boards, procedures, and facilities continues to increase the effective resolution of these measurements. Time (hrs) Change In tD (ppm) 0 500 1000 1500 2000 2500 3000 3500 Figure 7-4. RES11A10-Q1 Long-term Drift, tD Figure 7-5. RES11A10-Q1 Long-term Drift, tM Time (hrs) Change In tD (ppm) 0 100 200 300 400 500 600 700 800 900 1000 Figure 7-6. RES11A00-Q1 Long-term Drift, tD RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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7.3.3 Predictable Voltage Coefficient

The voltage coefficients of the RES11A-Q1 are largely related to self-heating, where the power dissipated in the device raises the die temperature. As previously mentioned, the commonality of this temperature rise leads to a comparable shift in each resistor, such that the divider ratio is well preserved. Applying voltage V across resistor R results in the loss of a corresponding power dissipation of P = V 2 / R , in the form of heat in the device die. This heat leads to a localized increase in the junction temperature, which in turn causes the same parametric shifts previously discussed in the context of temperature coefficients. TCR is specified as a function of ambient temperature; therefore, use the effective junction-to-ambient thermal resistance to determine the effective temperature rise and calculate the nominal or expected shift. Rexpected = R initial + VR2 R × R θJA effective × TCR abs × R initial (16) If two dividers are biased simultaneously, the power dissipation of both dividers must be summed before calculating the associated junction temperature rise using the junction-to-ambient thermal resistance. The following figures show a data set from one RES11A40-Q1 unit tested at various voltages. Voltage (V) Resistance () 5 10 15 20 25 30 35 40 969.75 970 970.25 970.5 970.75 971 RIN1 Calculated RIN2 Calculated RIN1 Measured RIN2 Measured Figure 7-7. RIN Resistance vs Divider Voltage Voltage (V) Resistance () 5 10 15 20 25 30 35 40 3878.5 3879 3879.5 3880 3880.5 3881 3881.5 3882 3882.5 3883 3883.5 RG1 Calculated RG2 Calculated RG1 Measured RG2 Measured Figure 7-8. RG Resistance vs Divider Voltage The difference of the expected value of R from the actual value of R describes the actual-to-expected mismatch error of R, due to non-temperature-related effects on the voltage coefficient. Similar to the logarithmic conformity error of a logarithmic amplifier or the integrated nonlinearity error of an ADC, this error describes the deviations of the actual device behavior from the predictable behavior. While the absolute magnitude of the shift varies, the slope or trend is predictable. Note that measurement noise and leakages can easily increase the measured error; follow best practices such as cleaning and baking circuit boards after assembly to minimize external errors and improve repeatability. The change in the measured value of R is divided by the change in bias voltage V R to calculate the effective voltage coefficient of resistance. For example, the voltage coefficient of RIN1 is ΔRIN1 divided by ΔVRIN1. Voltage coefficient (Ω/V) = Rfinal – R initial VR(final) – V R(initial) (17) www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: RES11A-Q1

Voltage (V) Change In Resistance () 5 10 15 20 25 30 35 40 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 RIN1 Error RIN2 Error RG1 Error RG2 Error Figure 7-9. Resistor Actual-to-expected Mismatch vs Divider Voltage, Absolute Voltage (V) Change In Resistance (ppm) 5 10 15 20 25 30 35 40 -100 -80 -60 -40 -20 100 RIN1 Error RIN2 Error RG1 Error RG2 Error Figure 7-10. Resistor Actual-to-expected Mismatch vs Divider Voltage, Normalized This exercise is repeated for each R x, tD1, tD2, and tM, to calculate the voltage coefficients associated with each parameter. For example, the RES11A-Q1 has a typical absolute voltage coefficient of approximately ±0.24Ω/V for RIN and R G. When considered in ratiometric terms, the typical voltage coefficient of t D1 or t D2 is ±0.4ppm/V, and the voltage coefficient of tM is ±0.24ppm/V.

7.3.4 Ultra-Low Noise

Noise in resistors can be evaluated in two separate regions: low-frequency flicker noise and wideband thermal noise. Flicker, or 1/f noise, is extremely important for systems that require signal gain at frequencies less than 100Hz. The flicker noise for thin-film resistors, including the RES11A-Q1, is lower than that of thick-film resistor processes. Thermal noise typically dominates in the region greater than 1kHz, and increases as resistor magnitude increases. Noise is modeled as a voltage source in series with the resistor. For a resistive divider such as the RES11A-Q1, the thermal noise as measured at the center tap of two resistors RIN and RG is equivalent to the thermal noise of a resistor with value RIN || RG: eN = 4kBTR (18) where:

• eN is the thermal noise density in nV/√Hz
• T is the absolute temperature in kelvins (K)
• kB is the Boltzmann constant, 1.381 × 10-23J/K
• R = RIN || RG As an example, for the RES11A40-Q1 at 25°C: eN = 4kBTR = 4 × 1.38E − 23 J K × 278K × 1kΩ ∥ 4kΩ = 3.5nV/ Hz (19)

7.4 Device Functional Modes

The RES11A-Q1 is typically used with two independently biased resistor dividers. R IN1 and RG1 in series form a resistive divider, with RIN2 and RG2 in series forming another divider. However, the two dividers do not have to be used independently. The resistors can be connected in series or in parallel like any other resistor. Use one of the two GND pins to bias the part substrate. Connect the substrate to signal ground or a similar low-impedance bias point or plane for best noise rejection. While two GND/SUB connection pins are available on the device, connect only one of these to the ground plane. The two GND pins are internally connected through the substrate, which is not intended to conduct significant currents. Connect only one GND pin at a time and leave the other pin floating to prevent current return paths from developing through the substrate. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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7.4.1 Per-Resistor Limitations

The maximum voltage and current supported by the RES11A-Q1 depends on the device ratio, circuit configuration, and environmental conditions. Firstly, all implementations must respect the 150°C maximum junction temperature limitation. Depending on the ambient temperature T A, maximum power dissipation limits can vary based on the mission profile. Check compliance as follows; note the effective value of R θJA is impacted by board design, system thermal dissipation, and airflow. RθJA × IRIN1 2 × R IN1 + IRG1 2 × R G1 + IRIN2 2 × R IN2 + IRG2 2 × R G2 + T A ≤ 150°C (20) If the RES11A-Q1 is used in a conventional divider configuration such that I RIN1 = I RG1 = I D1 and I RIN2 = I RG2 = ID2, this simplifies to RθJA × ID1 2 × RIN1 + R G1 + I D2 2 × RIN2 + R G2 + T A ≤ 150°C (21) Each resistor of the RES11A-Q1 has several associated maximum nominal current values, depending on the circuit conditions, as summarized in the following table. These values incorporate guardbands to account for the absolute tolerance range of each divider. Although every RES11A-Q1 has a nominal R IN impedance of 1kΩ, not every ratio variant achieves this impedance with the same implementation, causing variations in the exact per-resistor limitations from ratio to ratio. 1. Instantaneous overload limit: maximum instantaneous current value for short-term stress. Exceeding this limit results in an overcurrent condition that is able to damage the device if the condition is sustained. While bench testing shows the RES11A-Q1 is able to survive very high short-term stresses, the device is not characterized at or after experiencing these extremes, and such operation is not encouraged. 2. DC continuous bias limit: maximum sustained current for long-term bias in dc or near-dc circuits, such as reference voltage generation and scaling. If this limit is exceeded, the device is operating outside the Recommended Operating Conditions, which for long-term operation theoretically causes parametric drift outside of the data-sheet specifications. This limit applies to most applications of the RES11A-Q1. 3. AC continuous bias limit: maximum sustained RMS current for long-term bias in ac circuits, such as resolver drivers, where the input signal is a sinusoid of 50Hz or greater. If this limit is exceeded, the device is operating outside the Recommended Operating Conditions, which for long-term operation theoretically causes parametric drift outside of the data-sheet specifications. Table 7-1. Maximum Current Limit per Ratio PART NUMBER SHORT-TERM OVERLOAD LIMIT (mA) DC CONTINUOUS BIAS LIMIT(1) mA) AC CONTINUOUS BIAS LIMIT(1) (mA) RIN RG RIN RG RIN RG (1) Assumes a continuous bias for 10 years at TA = 25°C www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: RES11A-Q1

In most gain and divider applications, I RIN1 = I RG1 = I D1 and I RIN2 = I RG2 = I D2. In these circuits, the maximum value of I Dx must remain at or less than the lesser of the values of I RINx or I RGx permitted by Table 7-1. This requirement applies to both short-term overload and long-term operating conditions. For ease of use, the Absolute Maximum Ratings and Recommended Operating Conditions tables present this information as a calculated maximum voltage across the divider. In circuits where the resistors are used in more unconventional ways, such that I RIN1 ≠ I RG1 or I RIN2 ≠ I RG2, compare the expected currents of each resistor against Table 7-1 on an individual basis to verify the device operating condition is valid. This requirement includes scenarios where the divider midpoint is driven by a low-impedance source, rather than measured by a high-impedance sensor, such as an amplifier. In some cases, external circuit elements such as a bidirectional zener diode helps protect the device from overstress conditions. See also Section 8.3. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Amplifier Feedback Circuit

The RES11A-Q1 is typically used to implement the feedback path of an operational amplifier, and thus set the circuit gain. This circuit is configured as either inverting or noninverting, with the input voltage being applied to that respective amplifier input, and is generically drawn in the following figure. GND VIN RY RX VOUT Figure 8-1. Inverting Amplifier Configuration GND VIN RY RX VOUT – Figure 8-2. Noninverting Amplifier Configuration For the inverting circuit configuration: GInv = RX RY (22) VOUT = –V IN × G Inv (23) For the noninverting circuit configuration: GNoninv = 1 + RX RY (24) VOUT = V IN × G Noninv (25) Typically, RX = RG and RY = RIN, allowing noninverting gains from 2 to 11 to be achieved. Inverting gains range Gx = G nom 1 + t Dx (26) www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: RES11A-Q1

8.1.1.1 Amplifier Feedback Circuit Example

Consider the following example. Divider 1 of the RES11A-Q1 is used in an inverting configuration, and divider 2 is used in a noninverting configuration. Both channels have the same input signal V IN, but the circuits have differing transfer functions of VOUT1 = VIN × (–G1) and VOUT2 = VIN × (1 + G2). GND VIN RIN2 RG2 VOUT2 GND VIN RIN1 RG1 VOUT1 Figure 8-3. Amplifier Gain Example Circuit The following table shows the calculated results for several example conditions to illustrate the effects of the various errors. The impact of amplifier offset or input bias currents on V OUTx is not considered. Each row represents a different hypothetical condition for VIN, Gnom, tD1, and tD2. Table 8-1. Amplifier Gain Example Circuit Conditions, Using RES11A-Q1 VIN Gnom tD1 tD2 G1 G2 VOUT1 VOUT2 1V 4 0ppm 0ppm 4 4 –4V 5V 1V 4 100ppm –10ppm 4.00040 3.99996 –4.00040 4.99996 1V 4 40ppm –80ppm 4.00016 3.99968 –4.00016 4.99968 1V 4 –80ppm 40ppm 3.99968 4.00016 –3.99968 5.00016

8.1.2 Voltage Divider Circuit

As alluded in Section 6.1, the RES11A-Q1 is typically used as an input signal level-shifter or voltage divider. This circuit is generically drawn in the following figure. RX RY GND VIN VOUT Figure 8-4. Generic Voltage Divider Circuit GVD = RY RY + R X (27) VOUT = V IN × G VD (28) GVDx = G VDnom 1 + t VDx (29) RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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Often, RG and RIN act as RX and RY respectively in this circuit. Substituting these terms gives a transfer function of: GVDx = RINx RINx + R Gx = 1 Gx + 1 (30) Because GVDx is a direct function of G x, the ratio tolerance error tVDx of these voltage-divider circuits is a direct function of tDx. Typical and maximum parameter values for t VDx in this configuration are calculated from a given tDx value as follows: tVDx = – G nom × t Dx Gnom × t Dx + G nom + 1 (31) For example, if a RES11A40-Q1 with t D1 = 130ppm is used in this configuration, the associated t VD1 error is –104ppm. The sign change occurs because a positive t Dx error means R G > R Gnom or R IN < R INnom. Since the resulting GVDx is less than the nominal value, the error term is negative. For the alternative case where the positions of R G and RIN are swapped, such that R X = RIN and RY = RIN, the transfer function is: GVDx = RGx RINx + R Gx = Gx Gx + 1 (32) The error of this transfer function is described by: tVDx = tDx Gnom × t Dx + G nom + 1 (33) If the same RES11A40-Q1 with tD1 = 130ppm is used in this alternative configuration, the associated tVD1 error is 26ppm. A sign change does not occur because a positive t Dx error means RG > RGnom or RIN < RINnom. Because the result GVDx is greater than the nominal value, the error term is again positive.

8.1.2.1 Voltage Divider Circuit Example

Consider the following example. Dividers 1 and 2 of the RES11A-Q1 are both arranged as voltage dividers, but the relative positions of RG1 and RIN2 are swapped, as are the positions of RIN1 and RG2. Both channels have the same input signal VIN, but have differing transfer functions of VOUT1 = VIN × G1 / (1 + G1) and VOUT2 = VIN × 1 / (1 + G2). RES11A-Q1 RIN1 RG2 RIN2RG1 –VIN VOUT1 VOUT2 GND Figure 8-5. Voltage Divider Example Circuit The following tables show the calculated results for several examples to illustrate the effects of the various errors. Each row in the tables represents a different hypothetical condition. The final rows of each table show the results when substituting the absolute maximum and minimum limits of t Dx. The final percent error EOUTx is calculated as: www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: RES11A-Q1

EOUTx = VOUTx – V OUTnom VOUTnom (34) Table 8-2. Calculated Errors for Voltage Divider Example, Divider 1 VIN Gnom GVDnom VOUT1nom tD1 tVD1 GVD1 VOUT1 EOUT1 5V 4 1/5 1V 60ppm –48ppm 0.19999 0.99995 –48ppm 5V 4 1/5 1V –80ppm 64ppm 0.20001 1.00006 64ppm 10V 4 1/5 2V 60ppm –48ppm 0.19999 1.99990 –48ppm 10V 4 1/5 2V –80ppm 64ppm 0.20001 2.00013 64ppm 10V 4 1/5 2V 500ppm –400ppm 0.19992 1.99920 –400ppm 10V 4 1/5 2V –500ppm 400ppm 0.20008 2.00080 400ppm Table 8-3. Calculated Errors for Voltage Divider Example, Divider 2 VIN Gnom GVDnom VOUT2nom tD2 tVD2 GVD2 VOUT2 EOUT2 5V 4 4/5 4V 75ppm 15ppm 0.80001 4.00006 15ppm 5V 4 4/5 4V –130ppm –26ppm 0.79998 3.99990 –26ppm 10V 4 4/5 8V 75ppm 15ppm 0.80001 8.00012 15ppm 10V 4 4/5 8V –130ppm –26ppm 0.79998 7.99979 –26ppm 10V 4 4/5 8V 500ppm 100ppm 0.80008 8.00080 100ppm 10V 4 4/5 8V –500ppm –100ppm 0.79992 7.99920 –100ppm As the examples show, the final error E OUTx of the transfer function for each divider is equivalent to the corresponding effective voltage divider error t VDx. In all cases, the magnitude of t VDx is less than the magnitude of tDx.

8.1.2.2 Voltage-Divider Circuit Drift

As discussed in Section 8.1.2, the voltage-divider circuit error tVDx of the RES11A-Q1 is related to the gain-circuit error tDx by one of the two following expressions (depending on the placement of RG and RIN): GVDx = RINx RINx + R Gx = G VDnom 1 + t VDx tVDx = – G nom × t Dx Gnom × t Dx + G nom + 1 (35) GVDx = RGx RINx + R Gx = G VDnom 1 + t VDx tVDx = tDx Gnom × t Dx + G nom + 1 (36) Therefore, the change in the voltage divider transfer function G VDx with temperature is a direct function of the change in t Dx with temperature. Multiplying the temperature coefficient TCR ratio by the change in ambient temperature gives the change in t Dx, which is in turn substituted in the appropriate equation above to calculate the change in tVDx. The change in tVDx directly describes the change in GVDx. As an example, consider a RES11A40-Q1 with Gnom = 4 and a circuit configuration as shown in Figure 8-4, with RX = RG1 and RY = RIN1. Assume tD1 is initially 85ppm and increases by 5ppm due to a 25°C increase in ambient temperature. The initial value of tVD1, before the temperature change, is calculated as: tVD1 = – G nom × t D1 Gnom × t D1 + G nom + 1 = –4 × 0.000085 4 × 0.000085 + 4 + 1 = –0.000068 = –68ppm (37) The new value of tVD1 after the temperature change is calculated as: tVD1 = – G nom × t D1 Gnom × t D1 + G nom + 1 = –4 × 0.000090 4 × 0.000090 + 4 + 1 = –0.000072 = –72ppm (38) In this first scenario, the shift in tD1 of 5ppm causes a shift in tVD1 of –4ppm. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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If the circuit configuration is inverted so that R X = RIN1 and RY = RG1, then the initial value of t VD1 is calculated as: tVD1 = tD1 Gnom × t D1 + G nom + 1 = 0.000085 4 × 0.000085 + 4 + 1 = 0.000017 = 17ppm (39) The new value of tVD1 after the temperature change is calculated as: tVD1 = tD1 Gnom × t D1 + G nom + 1 = 0.000090 4 × 0.000090 + 4 + 1 = 0.000018 = 18ppm (40) In this second scenario, the shift in tD1 of 5ppm causes a shift in tVD1 of only 1ppm.

8.1.3 Discrete Difference Amplifier

The RES11A-Q1 is commonly used to implement a simple difference amplifier. The ratiometric matching between the two resistor dividers improves CMRR performance and gain drift for the circuit, when compared to a similar implementation using unmatched discrete resistors. The basic circuit is shown in Figure 8-6. VOUT = VIN+ − VIN− × RG RIN + V REF (41) VIN+ ADC RES11A-Q1 OPA392 VIN– GND VREF RIN1 RG2 RIN2RG1 VOUT Figure 8-6. Discrete Difference Amplifier Using RES11A-Q1

8.1.3.1 Difference-Amplifier Common-Mode Rejection Analysis

In this simple difference amplifier configuration, the nominal CMRR is calculated as: CMRR = 20 × log 10 AD ACM (42) The term A D is the differential gain of the circuit, and the term A CM is the common-mode gain of the circuit. These are defined as the following: AD × = VOUT VD = 0.5 × RG1 RG1 + R IN1 + RG2 RG2 + R IN2 RIN2 RG2 + R IN2 (43) ACM = VOUT VCM = RG1 RG1 + R IN1 − RG2 RG2 + R IN2 RIN2 RG2 + R IN2 (44) www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: RES11A-Q1

Therefore, CMRR = 20 × log 10 2× RG1 × RIN2 + R G2 − RG2 × RIN1 + R G1 RG1 × RIN2 + R G2 + R G2 × RIN1 + R G1 (45) When this expression is evaluated with the definitions given in Section 7.3.1, assuming the worst-case scenario of the most unbalanced divider matching possible: CMRR = 20 × log 10 Gnom +1+ t Rx2 1− Gnom 4× t Rx (46) tRx2 << 1; therefore, the worst-case CMRR is approximated as: CMRR = 20 × log 10 Gnom +1 4× t Rx (47) By definition, the parameter tM describes the effective error that is otherwise equivalent to 4 × tx for an unmatched divider network, and so the maximum value of tM can be used to calculate the same worst-case result. Likewise, the typical value of tM can be used to approximate the typical CMRR. CMRR = 20 × log 10 Gnom +1 tM (48) For example, the worst-case CMRR for a RES11A40-Q1 device with G = 4 is approximately 74.0dB, with a typical CMRR of approximately 98.5dB. In comparison, implementation of a comparable G = 4 difference amplifier with unmatched 0.1%-tolerance resistors results in a worst-case CMRR of approximately 62dB. In a difference amplifier configuration, the CMRR of the op amp contributes error as well. The op-amp CMRR is considered in parallel with the CMRR of the resistor network, as per the following equation: CMRRTOTAL = 1 CMRRAMP + 1 CMRRRESISTORS (49) Additional mismatches in the divider end-to-end resistances reduce the effective CMRR of a difference amplifier. While the low absolute tolerance span of the RES11A-Q1 (65ppm typical) helps reduce these concerns, parasitic trace resistances can lead to additional mismatches that impact the CMRR specs. Bench results from a difference amplifier implementation of the RES11A40-Q1 and the OPA210 are presented for various deliberate input-impedance mismatches. Input Frequency (Hz) Common-mode Rejection Ratio (dB) 100 105 10 100 1000 10000 100000

0 Mismatch

0.25 Mismatch

0.5 Mismatch

1 Mismatch

2 Mismatch

5 Mismatch

Figure 8-7. Effect of Input Impedance Mismatch on Common-mode Rejection Ratio RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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8.1.3.2 Difference-Amplifier Gain Error Analysis

The transfer function Equation 41 assumes that RG1 = RG2 and RIN1 = RIN2. Without this assumption, the transfer function of the difference amplifier is better described by the following: VOUT = V IN+ × RG1 RG1 + R IN1 RG2 + R IN2 RIN2 – V IN– × RG2 RIN2 + V REF (50) If the end-to-end values of R G2 + RIN2 and RG1 + RIN1 are sufficiently matched, the correspond terms cancel out in the above equation. The end-to-end mismatch specification of the RES11A-Q1 describes the typical error of this in ratiometric terms; for brevity, this error term is denoted as tE2E. RG2 + R IN2 RG1 + R IN1 = 1 + t E2E (51) VOUT = V IN+ × RG1 RIN2 1 + t E2E – V IN– × RG2 RIN2 + V REF (52) The ratio error of R G2 / R IN2 is described by t D2. The ratio error of R G1 / R IN2 is described by the RG mismatch between dividers, ratiometric specification; for brevity, this error term is denoted as tD2D. RG2 RIN2 = 1 + t D2 × G nom (53) RG2 RIN1 = 1 + t D2D × G nom (54) The effective transfer function is thus VOUT = V IN+ × G nom × 1 + t E2E 1 + t D2D – V IN– × G nom × 1 + t D2 + V REF (55) For further analysis, the input voltages VIN+ and VIN– are first expressed as a common-mode input voltage (V CM) and a differential input voltage (VDIFF). VCM = VIN+ + V IN– 2 (56) VDIFF = V IN+ – V IN– (57) Equation 55 is expressed in terms of VCM and VDIFF as VOUT = V CM × RG1 RIN1 + R G1 – RG2 RIN2 + R G2 RIN2 RIN2 + R G2 + V DIFF × RG1 RIN1 + R G1 + RG2 RIN2 + R G2 2 × RIN2 RIN2 + R G2 (58) VOUT = V CM × RG1 RIN2 × RIN2 + R G2 RIN1 + R G1 – RG2 RIN2 + VDIFF 2 × RG1 RIN2 × RIN2 + R G2 RIN1 + R G1 + RG2 RIN2 (59) VOUT = V CM × G nom × 1 + t D2D × 1 + t E2E – 1 + t D2 + VDIFF 2 × G nom × 1 + t D2D × 1 + t E2E + 1 + t D2 (60) The gain error with respect to V CM or to V DIFF is calculating by taking a partial derivative of Equation 60 with respect to the given variable. ∂ VOUT ∂ VCM = G nom × 1 + t D2D × 1 + t E2E – 1 + t D2 (61) www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: RES11A-Q1

∂ VOUT ∂ VDIFF = Gnom 2 × 1 + t D2D × 1 + t E2E + 1 + t D2 (62) Because the error tolerance terms (1 + t D2D) and (1 + t E2E) are multiplicative, and t D2D and t E2E are both are zero-mean with a standard deviation in the sub-200ppm range, the error contribution of t D2D × t E2E is less than 0.01ppm and is assumed to be negligible. The result is an algebraic sum of three terms, all considered as independent zero-mean Gaussian values, such that: tERReffective 1 = tD2D tE2E tD2 (63) By substituting the typical values of t D2D, tE2E, and t D2, root sum of squares error analysis is performed on the resulting terms to describe a typical error for the transfer function. Consider an example where a RES11A50-Q1 is used, such that G nom = 5. Assume t D2 = 81ppm, t E2E = 18ppm, and tD2D = 86ppm. Using Equation 63, tERReffective is calculated as ±120ppm, and is used to calculate ∂VOUT with respect to V CM and to V DIFF. The former is the common-mode gain error, while the latter is composed of the desired nominal gain term (Gnom) and an undesired gain error. ∂ VOUT ∂ VCM = G nom × t ERReffective = G nom × ±120ppm = ±600ppm (64) ∂ VOUT ∂ VDIFF = Gnom 2 × 2 + t ERReffective = G nom ± 300ppm (65) Multiplication of the t ERReffective error by the desired process control value, such as × 6 for a six-sigma approach, gives conservative maximum bounds. Because the ±1 σ values reported in Electrical Characteristics already include guardbanding and account for mean shifts, in many cases a lower process control value (such as five-sigma) is sufficient. For example, solving the previous expressions for CMRR yields only 78.5dB, whereas the actual typical CMRR for the RES11A50-Q1 is 102.1dB. The discrepancy arises because the measurement resolution of tD1, tD2, tM, and CMRR is higher than that of t D2D and tE2E, and therefore the reported values of the latter parameters include additional guardbanding. Additionally, the conservative modeling approach assumes tD2D, tE2E, and t D2 are uncorrelated, whereas for many devices there are weak correlations (such as t D2D and tE2E having different polarities) that cause the actual observed error to be lower than the modeled error.

8.1.4 Discrete Instrumentation Amplifiers

Use the RES11A-Q1 in conjunction with a dual-channel operational amplifier to implement a discrete instrumentation amplifier (INA). The ratiometric matching between the two resistor dividers improves CMRR performance for the circuit when compared to a similar implementation using unmatched discrete resistors, and results in better over-temperature and over-aging gain drift characteristics. INAs are often used instead of difference amplifiers when high input impedance and low bias currents are needed, such as when measuring bridge sensors. Discrete INAs are often configured as a differential-input differential-output circuit; see Figure 8-8 . While not shown, if needed, use an additional discrete difference amplifier stage (requiring a second RES11A-Q1 and another op-amp channel) to convert the differential output voltage to a single-ended voltage (for example, when driving a single-ended ADC). This extra stage also adds an additional offset and provides additional gain, effectively mimicking the common three-amplifier INA architecture. VOUT+ − VOUT− = VIN+ − VIN− × 1+ RG RIN (66) RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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8.1.5 Fully Differential Amplifier

The RES11A-Q1 can be used to set the gain of a fully differential amplifier, such as the THP210. The ratiometric matching between the two resistor dividers leads to improved gain matching and CMRR performance for the circuit, when compared to a similar implementation using unmatched discrete resistors. Figure 8-10 shows a generic schematic representation of a fully differential amplifier driving a differential ADC, with a RES11A-Q1 used to set the amplifier gain. VOUT+ − VOUT− = VIN+ − VIN− × RG RIN (68) VIN+ ADC RES11A-Q1 VIN– RG2 RIN1 RG1RIN2 VOUT+ THP210 VOUT– – + Figure 8-10. Fully-differential Amplifier Gain Setting Using RES11A-Q1

8.1.6 Unconventional Circuits

The two matched dividers of a RES11A-Q1 are typically used independently of each other, as two well-matched channels. The resistors are also useful in less conventional orientations, where resistors from both channels are linked to achieve a wider range of transfer functions and effective "gains". While voltage dividers or amplifier feedback paths are obvious candidates for this use, more unique applications such as "unbalanced" instrumentation amplifier circuits also benefit from this approach.

8.1.6.1 Single-Channel Voltage Divider

As discussed in Section 8.1.2, the RES11A-Q1 is commonly used as an input signal level-shifter or voltage divider. Typically, RG and R IN act as R X and R Y respectively (or vice versa) in this circuit, and are arranged with the two dividers of the RES11A-Q1 acting as independent channels. If unconventional values of G VD are required, combine the four resistors of a single RES11A-Q1 in various series and parallel combinations to achieve the desired effective gain, though the device channel count is effectively reduced from two to one. The following tables showcase some of the permutations of possible RES11A-Q1 connections, and reports the transfer function associated with each. Because the value of G VD is always less than 1, for readability, the value given in the tables is GVD –1 or 1 / GVD. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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8.1.6.2 Single-Channel Amplifier Gain

The RES11A-Q1 is often used to implement the feedback network of an amplifier and set the circuit gain, as discussed in Section 8.1.1. Typically, RG and RIN act as RX and RY respectively (or vice versa) in this circuit, and dividers 1 and 2 are arranged as two independent channels. If, however, unconventional values of GInv or GNoninv are required, combining the four resistors of a single RES11A-Q1 in various series and parallel combinations achieves this requirement, but at the expense of a reduction in channel count. The following tables showcase some of the permutations of possible RES11A-Q1 connections, and report the G Inv transfer function associated with each. To calculate GNoninv for each scenario, simply add 1 to the magnitude of the given GInv. Table 8-6. Effective Transfer Function GInv for Some RES11A-Q1 Resistor Permutations, Adjusting RY RX RIN RIN1 RIN1 RIN1 RG RG1 RG1 RG1 RY RG RG1 + RIN2 RG1 + RG2 RG1 + RG2 + RIN2 RIN RIN1 + RIN2 RIN1 + RG2 RIN1 + RG2 + RIN2 GR11 EFFECTIVE TRANSFER FUNCTION GInv Table 8-7. Effective Transfer Function GInv for Some RES11A-Q1 Resistor Permutations, Adjusting RX RX RG RG1 + RIN2 RG1 + RG2 RG1 + RG2 + RIN2 RIN RIN1 + RIN2 RIN1 + RG2 RIN1 + RG2 + RIN2 RY RIN RIN1 RIN1 RIN1 RG RG1 RG1 RG1 GR11 EFFECTIVE TRANSFER FUNCTION GInv 1 1 2 2 3 1 2 2 3 2 2 3 4 5 0.5 1 1.5 2 3 3 4 6 7 0.3333 0.6667 1.3333 1.6667 4 4 5 8 9 0.25 0.5 1.25 1.5 5 5 6 10 11 0.2 0.4 1.2 1.4 9 9 10 18 19 0.1111 0.2222 1.1111 1.2222 10 10 11 20 21 0.1 0.2 1.1 1.2 For example, consider an inverting amplifier circuit constructed with R X = R G1 + R G2 and R Y = R IN1. Using a RES11A00-Q1 device with Gnom = 10 for this implementation gives an effective transfer function G INV = RX / RY = (10kΩ + 10kΩ) / 1kΩ = 20kΩ / 1kΩ = 20. Therefore, VOUT = –VIN × GINV = VIN × –20. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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Figure 8-13. VOUT = –20 × VIN, Effective Circuit GND VIN RIN1 RG1 VOUT RG2 Figure 8-14. VOUT = –20 × VIN, Implemented With RES11A00-Q1

8.1.6.2.1 Gain Scaling the RES60A-Q1 With the RES11A-Q1

The RES60A-Q1 is a precision matched resistor divider, optimized for extremely high-voltage applications. The RES60A-Q1 is often used in battery management system (BMS) applications to measure pack voltages. While multiple RES60A-Q1 ratios are available, additional effective ratios are achieved by finely scaling the divider output using a low-offset buffer amplifier and RES11A-Q1. The low ratiometric errors of the RES11A-Q1 minimize additional gain error contributions to the signal chain, while maximizing the input full-scale range (FSR) of downstream ADCs. RHV RLV GND VBATT VMID + RIN RG GND VOUT Figure 8-15. Battery Pack Measurement with RES60A-Q1 and RES11A-Q1 VMID = V BATT × RLV RHV + R LV = VBATT GR60 + 1 (69) VOUT = V MID RIN RG + 1 = V MID GR11 + 1 = V BATT 1 + G R11 GR11 × GR60 + 1 (70) For brevity, the effective transfer function of the RES60A-Q1, RES11A-Q1, and amplifier circuit is summarized as GSF. GSF = GR11 × GR60 + 1 1 + G R11 (71) VOUT = V BATT × 1 GSF (72) Table 8-8 shows the effective voltage divider scaling factor G SF associated with various RES60A-Q1 and RES11A-Q1 combinations. While not shown for brevity, the possible gain permutations discussed in Section 8.1.6.2 are also applicable here. www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: RES11A-Q1

Table 8-8. Effective Scaling Factor GSF for the RES60A-Q1 and RES11A-Q1 Combinations GR60 145 210 315 410 500 610 1000 GR11 EFFECTIVE SCALING FACTOR GSF

8.1.7 Unconventional Instrumentation Amplifiers

The basic instrumentation amplifier circuits shown in Figure 8-8 and Figure 8-9 place the two R IN resistors of the RES11A-Q1 in series between the two amplifiers inverting input pins. Instead, combine these resistors in parallel, or connect only one of the two R IN resistors and leave the other resistor floating, to achieve a wider variety of effective circuit gains. Another option is the unbalanced INA, where the feedback paths of the two input amplifiers have different effective gains. With the RES11A-Q1, this configuration is achieved by using series or parallel combinations of the divider elements to achieve a different effective feedback resistance for one amplifier. With the normal or balanced INA approach, if the input signal VCM is not near midsupply, the amplifiers run out of headroom and rail out as the input approaches one of the power-supply voltages. By implementing asymetric gains, the dynamic range of the circuit is maximized, though at the minor expense of bandwidth and phase mismatches (largely trivial for dc and low-frequency applications). While the transfer function and stability and error analyses of the circuit are relatively complex, the unbalanced INA nevertheless is a useful tool for this scenario. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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8.2 Typical Application

8.2.1 Common-Mode Shifting Input Stage

The RES11A-Q1 can be used to implement a common-mode attenuator at the high-impedance inputs of an instrumentation amplifier (INA). This configuration extends the usable signal range, so long as the maximum differential voltage limitation of each resistor divider is respected. Figure 8-16 shows an example of a high-side current-sense circuit where a differential voltage, VSHUNT, develops across a sense resistor with an undesirably high common-mode voltage V CM. V REF is used to shift input common-mode voltages V MID1 and V MID2 to levels within the specified input common-mode range of the INA. The amplifier output, VOUT, is a scaled function of VSHUNT, such that nominally: VOUT = V SHUNT × RIN RG + R IN + R EQUIV (73) VOUT can be gained up further by the INA stage, to make maximal use of the effective resolution of a downstream ADC. In practice R EQUIV is optional; however, if R EQUIV = R SHUNT, this resistance equalizes the nominal impedance between V CM and each of the INA high-impedance inputs, thus improving CMRR performance. Select an INA with input bias currents I B1 and IB2 << ISTATIC1 and ISTATIC2, such as the INA333 or INA823. Select a RES11A-Q1 device with a sufficiently high divider series resistance so that ISTATIC1 and ISTATIC2 << ILOAD. RSHUNT VBUS GND RG1 REQUIV RIN1 VREF GND RG2 RIN2 GND ISTATIC1 ISTATIC2 ILOADILOAD + ISTATIC2ILOAD + ISTATIC1 + ISTATIC2 INA VMID1 VMID2 VOUT ILOAD VSHUNT Figure 8-16. RES11A-Q1 Common-Mode Shifting Circuit To achieve a desired nominal input common-mode voltage, VMID1TARGET, set VREF as follows: VREF = V MID1TARGET × RG + R IN + R EQUIV RG + R EQUIV − VCM × RG + R IN + R EQUIV RG + R EQUIV − 1 (74) www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: RES11A-Q1

8.2.1.1 Design Requirements

Consider a level-shifting application where a high-side current shunt measurement from an 18V supply rail must be measured by a 3.3V amplifier and ADC. PARAMETER DESIGN GOAL Input VBUS 18V ILOAD 300mA (maximum) RSHUNT 1Ω ADC full-scale range (target VOUT) 3.3V Possible VREF voltages 3.3V, 0V

8.2.1.2 Detailed Design Procedure

The design parameters are used with the aforementioned equations to select a nominal target G. When the possible VREF voltages available in the system are considered, VREF = 0V with G = 9 is found to result in a V MID1 value of 1.8V, well within the input common-mode range of a 3.3V rail-to-rail amplifier such as the OPA392. When the corresponding RES11A90-Q1 is employed, the loss terms I STATIC1 and ISTATIC2 are nominally 1.80mA and 1.77mA for I LOAD = 300mA, resulting in an effective floor of 1.77mA for I LOAD. For simplicity, the error contributions of the INA stage VOS and IB are ignored. For the INA stage, an integrated TI instrumentation amplifier (IA) can be used. Alternatively, a discrete approach can be implemented using another RES11A-Q1 device or devices, and one or more op amps. For this example, an IA stage is constructed with two channels of a OPA4392 and a second RES11A90-Q1 (RIN3, R G3, R IN4, and RG4). This stage is in turn cascaded with a difference amplifier stage, constructed with the third amplifier channel and a RES11A00-Q1 (RIN5, R G5, R IN6, and R G6). The level-shifting stage gain of 10 –1, multiplied by the instrumentation amplifier stage gain of 10, results in an effective unity-gain transfer function for V SHUNT. Therefore, the differential output voltage for this stage is approximately 0.3V, with amplifier outputs of 1.936V and 1.634V. After the final difference amplifier stage gain of G = 10, the common-mode voltage drops out and the maximum value of the resulting V OUT is nominally 3.0V, compatible with a single-ended 3.3V ADC such as the ADS7046. If desired, the fourth channel of the OPA4392 can be used to buffer this output signal and serve as a dedicated ADC driver. RSHUNT VBUS GND RG1 REQUIV RIN1 GND RG2 RIN2 GND ISTATIC1 ISTATIC2 ILOADILOAD + ISTATIC2ILOAD + ISTATIC1 + ISTATIC2 VMID1 VMID2 ILOAD VSHUNT OPA392 RIN4 RIN3 OPA392 RG4 RG3 RIN6 RG5 GND RIN5 OPA392 RG6 OPA392 VOUT Figure 8-17. High-Side Current Shunt Common-Mode Shifting Circuit RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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8.2.1.3 Application Curves

VS1 3.3 RI N3 1k RI N4 1k RG3 9k ISTATIC1 ISTATIC2 RG1 9k RG2 9k RIN1 1k RIN2 1k + + U2 OPAx392 + + U1 OPAx392 RG4 9k RI N6 1k + + U3 OPAx392 RG6 10k + + U4 OPAx392 REQUIV 1 Figure 8-18. Circuit Model in TINA-TI Shunt Current (mA) Divider Current (mA) 0 30 60 90 120 150 180 210 240 270 300 1.76 1.765 1.77 1.775 1.78 1.785 1.79 1.795 1.8 1.805 1.81 ISTATIC2 ISTATIC1 Figure 8-19. Simulation Result for ISTATIC Shunt Current (mA) Divider Midpoint Voltage (V) 0 30 60 90 120 150 180 210 240 270 300 1.76 1.765 1.77 1.775 1.78 1.785 1.79 1.795 1.8 1.805 1.81 VMID2 VMID1 Figure 8-20. Simulation Result for VMID Shunt Current (mA) Output Voltage (V) 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOUT Figure 8-21. Simulation Result for VOUT www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: RES11A-Q1

8.3 Power Supply Recommendations

The ratio of a given RES11A-Q1 device dictates the maximum differential voltage rating for the resistor dividers of the device. See the Absolute Maximum Ratings and Recommended Operating Conditions for device-specific values under transient and sustained divider bias conditions, respectively. Section 7.4.1 discusses per-resistor limitations in greater detail. If the device voltage is expect to exceed the maximum sustained divider voltage rating, consider additional protective circuit elements. Avoid using external current-limiting resistors in series, as these unbalance the divider and cancel out many of the ratiometric and over-temperature benefits of the RES11A-Q1. The easiest way to protect a RES11A-Q1 divider from overload conditions is to place a reverse-biased or bidirectional zener diode in parallel with the divider, to clamp the effective divider voltage without drawing any leakage current through the divider. Choose a diode with a breakdown voltage approximately equal to the maximum divider voltage.

8.4 Layout

8.4.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

• Reduce parasitic coupling by running input traces as far away from supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. For differential circuits, match the length of the input traces as best possible.
• Keep high impedance input signals away from noisy traces.
• Make sure system supply voltages are adequately filtered.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
• Only connect one of the two GND/SUB pins to the ground plane, to prevent the formation of current return paths through the device substrate. Float the other GND/SUB pin. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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8.4.2 Layout Examples

In the following examples, the RES11A-Q1 is shown with a VSSOP amplifier and 0402-size decoupling capacitors. Figure 8-22. Single-Layer Difference Amplifier Implementation Figure 8-23. Single-Layer Instrumentation Amplifier Implementation Figure 8-24. Front-and-Back Instrumentation Amplifier Implementation Figure 8-25. Front-and-Back, Differential-Output Instrumentation Amplifier Implementation www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: RES11A-Q1

For Figure 8-26, two RES11A-Q1 devices (bottom side) and one dual-channel op-amp (top side) are used. Figure 8-26. Front-and-Back Dual Difference Amplifiers Implementation RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

9.1.1.1 PSpice® for TI

PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create subsystem designs and prototype solutions before committing to layout and fabrication, reducing development cost and time to market.

9.1.1.2 TINA-TI™ Simulation Software (Free Download)

TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Design and simulation tools web page, TINA-TI simulation software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software or TINA-TI software be installed. Download the free TINA-TI simulation software from the TINA-TI™ software folder.

9.1.1.3 TI Reference Designs

TI reference designs are analog solutions created by TI’s precision analog applications experts. TI reference designs offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI reference designs are available online at https://www.ti.com/reference-designs.

9.1.1.4 Analog Filter Designer

Available as a web-based tool from the Design and simulation tool web page, the Analog Filter Designer allows the user to design, optimize, and simulate complete multistage active filter solutions within minutes. www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: RES11A-Q1

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

• RES21A-Q1 Automotive, Matched, Thin-Film Resistor Dividers With 10kΩ Inputs
• RES31A-Q1 Automotive, Matched, Thin-Film Resistor Dividers With 100kΩ Inputs
• RES60A-Q1 Automotive, 1400VDC, Precision Resistive Divider
• Texas Instruments, Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note
• Texas Instruments, THP210 Ultra-Low Offset, High-Voltage, Low-Noise, Precision, Fully-Differential Amplifier data sheet
• Texas Instruments, OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current, Rail-to-Rail I/O, e-trim™ Operational Amplifiers data sheet

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. TINA™ is a trademark of DesignSoft, Inc. PSpice® is a registered trademark of Cadence Design Systems, Inc. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains common TI terms, acronyms, and definitions. Divider The series combination of a matched RG and RIN resistor. Two resistors, RGx and RINx, connected in series form a given divider x. The midpoint of divider x is measured at pin MIDx. The RES11A- Q1 has two divider channels, divider 1 (RG1 + RIN1) and divider 2 (RG2 + RIN2). Gnom The nominal gain or ratio of a given divider. Calculated as RGnom / RINnom. Each orderable of the RES11A-Q1 has a different associated divider ratio, and thus a different Gnom. Gx The actual, measured gain or ratio of a given divider x when the divider gain error is considered. Calculated as RGx / RINx. GVDnom The nominal or ideal voltage-divider circuit gain of a given divider. Calculated as either RGnom / (RINnom + RGnom) or as RINnom / (RINnom + RGnom), depending on circuit configuration. GVDx The actual, measured voltage-divider circuit gain for a divider x when the divider gain error is considered. Calculated as either RGx / (RINx + RGx) or as RINx / (RINx + RGx), depending on circuit configuration. RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 www.ti.com

46 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: RES11A-Q1

tDx The normalized gain error associated with a given divider x. When calculating effective gain, Gx = Gnom × (1 + tDx). For an ideal divider, tDx = 0 and Gx = Gnom. tM The mismatch of the two divider gain errors for a given RES11A-Q1 device. Calculated as tM = tD2 – tD1. Equivalent to (G2 – G1) / Gnom. Used for simplified CMRR calculations. tVDx The normalized voltage-divider circuit gain error associated with a given divider x. When calculating effective voltage-divider circuit gain, GVDx = GVDnom × (1 + tVDx). For an ideal circuit, tVDx = 0 and GVDx = GVDnom. VDx The voltage applied across a given divider x. VRx The voltage applied across a given resistor Rx. For example, VRIN1 describes the voltage across RIN1. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2023) to Revision B (October 2025) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com RES11A-Q1 SLPS755B – OCTOBER 2023 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: RES11A-Q1

www.ti.com 15-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) RES11A00QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R100Q RES11A10QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R110Q RES11A15QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R115Q RES11A16QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R116Q RES11A20QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R120Q RES11A25QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R125Q RES11A30QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R130Q RES11A40QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R140Q RES11A50QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R150Q RES11A90QDDFRQ1 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 R190Q (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 15-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF RES11A-Q1 :

• Catalog : RES11A NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant RES11A00QDDFRQ1 SOT-23- THIN RES11A10QDDFRQ1 SOT-23- THIN RES11A15QDDFRQ1 SOT-23- THIN RES11A16QDDFRQ1 SOT-23- THIN RES11A20QDDFRQ1 SOT-23- THIN RES11A25QDDFRQ1 SOT-23- THIN RES11A30QDDFRQ1 SOT-23- THIN RES11A40QDDFRQ1 SOT-23- THIN RES11A50QDDFRQ1 SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2025 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant RES11A90QDDFRQ1 SOT-23- THIN Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) RES11A00QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A10QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A15QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A16QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A20QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A25QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A30QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A40QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A50QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 RES11A90QDDFRQ1 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 4X 0 -15 4X 4 -15 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6)

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

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