RES11A25-Q1

RES11A-Q1 TI | Alldatasheet

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Technical content

RES11A-Q1 Automotive, Matched, Thin-Film Resistor Dividers With 1-kΩ Inputs

1 Features

• AEC-Q200 Qualified for automotive applications: – Temperature: –40°C to +125°C
• High ratio matching precision: ±0.05 % (maximum)
• Low drift: ±2 ppm/°C TCR (maximum)

2 Applications

• Precision voltage divider, precision level translation
• Gain and attenuating amplifiers
• Difference amplifiers with high CMRR
• Discrete instrumentation amps with high gain accuracy
• Fully differential amplifiers with high gain accuracy
• Pinpoint comparator threshold setting

3 Description

The RES11A-Q1 is a matched pair of resistive dividers, implemented in thin-film SiCr with Texas Instruments' modern, high-performance, analog CMOS process. The device has a nominal input resistance of 1 k Ω, for low thermal and current noise, and is available in several nominal ratios to meet a wide array of system needs. Use the RES11A-Q1 in an inverse gain configuration by simply rotating the device placement by 180°. This feature supports layout reuse and increases flexibility for applications such as discrete instrumentation or difference amplifier implementations. The RES11A-Q1 series features high ratio-matching precision, with the measured ratio of each divider within ±0.01% (typical) of the nominal. This precision is maintained over the temperature range, with a maximum ratio drift of only ±2 ppm/°C. Additionally, the biased long-term stability of the device has been proven through thorough characterization. The RES11A-Q1 is automotive qualified under AEC- Q200 temperature grade 1. The temperature range is specified from –40°C to +125°C. The device is offered in an 8 ‑pin, SOT‑23-THIN package, with a body size of 2.9 mm × 1.6 mm (body size is a nominal value and does not include pins).

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) RES11A-Q1 DDF (SOT-23-THIN, 8) 2.9 mm × 2.8 mm (1) For more information , see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Device Information PART NUMBER NOMINAL RATIO RES11A10-Q1 1:1 RES11A15-Q1 (1) 1:1.5 RES11A16-Q1 (1) 1:1.667 RES11A20-Q1 (1) 1:2 RES11A25-Q1 (1) 1:2.5 RES11A30-Q1 (1) 1:3 RES11A40-Q1 1:4 RES11A50-Q1 (1) 1:5 RES11A90-Q1 1:9 RES11A00-Q1 1:10 (1) Preview information (not Advanced Information). RIN2 RG2 RIN1 RG1 Substrate RIN1 RMID1 RG1 GND/SUB GND/SUB RIN2 RMID2 RG2 Functional Block Diagram Common-mode Rejection Ratio (dB) Devices (%) 75 85 95 105 115 125 135 145 10% 12% 14% 16% 18% 20% 22% 24% 26% 28% RES11A40, G=4 Excellent Ratio Matching for Best CMRR ADVANCE INFORMATION RES11A-Q1 SLPS755 – OCTOBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

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4 Pin Configuration and Functions

1 RIN18 GND/SUB

2 RMID17 RIN2

3 RG16 RMID2

4 GND/SUB5 RG2

Figure 4-1. DDF Package, 8-Pin SOT-23-THN (Top View) Table 4-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. GND/SUB 4, 8 Ground Substrate bias connection RG1 3 Input Gain resistor connection for divider 1 RG2 5 Input Gain resistor connection for divider 2 RIN1 1 Input Input resistor connection for divider 1 RIN2 7 Input Input resistor connection for divider 2 RMID1 2 Output Center tap of divider 1 RMID2 6 Output Center tap of divider 2 Note Only one GND/SUB pin should be biased. The other GND/SUB pin should float, to prevent current return paths from forming through the substrate. See Section 6.4 for more information. www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: RES11A-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCM Maximum common mode voltage (any pin to GND/SUB) ±85 V ∆VOVLD Maximum overload voltage per divider (RINx pin to RGx pin, TA = 25°C) RES11A10 24.4 V RES11A15 20.3 RES11A16 19.9 RES11A20 18.3 RES11A25 28.4 RES11A30 32.5 RES11A40 30.5 RES11A50 29.9 RES11A90 40.7 RES11A00 44.7 ∆VMAX Maximum sustained voltage per divider (RINx pin to RGx pin, 10 years at TA = 125°C) (2) RES11A10 16.7 V RES11A15 18.7 RES11A16 19.3 RES11A20 18.3 RES11A25 22.2 RES11A30 23.7 RES11A40 26.5 RES11A50 29.0 RES11A90 37.5 RES11A00 39.3 Maximum sustained voltage per divider (RIN1 pin to RG1 pin and RIN2 pin to RG2 pin, 10 years at TA = 125°C) (3) RES11A10 11.8 V RES11A15 13.2 RES11A16 13.7 RES11A20 14.5 RES11A25 15.7 RES11A30 16.7 RES11A40 18.7 RES11A50 20.5 RES11A90 26.5 RES11A00 27.8 TA Ambient temperature –55 150 °C TJ Junction temperature –55 150 °C Tstg Storage temperature –55 175 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Worst-case evaluation such that TJ ≤ 150°C. Assumes tabs = –12%, RθJA = 156.2 °C/W, and that the specified voltage is applied across only one of the two dividers. (3) Worst-case evaluation such that TJ ≤ 150°C. Assumes tabs = –12%, RθJA = 156.2 °C/W, and that the specified voltage is applied across both dividers simultaneously. RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±TBD V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±2000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Maximum sustained current through RINx (RINx pin to RMIDx pin, 10 years at 25°C) RES11A10 ±8.93 mA RES11A15 ±8.93 RES11A16 ±8.93 RES11A20 ±8.93 RES11A25 ±7.44 RES11A30 ±8.93 RES11A40 ±8.93 RES11A50 ±8.93 RES11A90 ±8.93 RES11A00 ±7.44 Maximum sustained current through RGx (RGx pin to RMIDx pin, 10 years at 25°C) RES11A10 ±8.93 mA RES11A15 ±5.95 RES11A16 ±5.36 RES11A20 ±4.47 RES11A25 ±5.95 RES11A30 ±5.95 RES11A40 ±4.47 RES11A50 ±3.57 RES11A90 ±2.98 RES11A00 ±2.98 TA Specified temperature –40 125 °C www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: RES11A-Q1

5.4 Thermal Information

THERMAL METRIC(1) RES11A-Q1 UNITDDF (SOT-23-THIN)

8 PINS

RθJA Junction-to-ambient thermal resistance 156.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 77.0 °C/W RθJB Junction-to-board thermal resistance 73.7 °C/W ψJT Junction-to-top characterization parameter 4.5 °C/W ψJB Junction-to-board characterization parameter 73.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESISTANCE Gnom Nominal ratio (RGx / RINx) RES11A10 1 V/V RES11A15 1.5 RES11A16 1.667 RES11A20 2 RES11A25 2.5 RES11A30 3 RES11A40 4 RES11A50 5 RES11A90 9 RES11A00 10 tD1 Ratio tolerance of divider 1 (1) (RG1 / RIN1) / Gnom – 1 (3) RES11A10 ±0.01 ±0.05 RES11A15 TBD ±0.05 RES11A16 TBD ±0.05 RES11A20 TBD ±0.05 RES11A25 TBD ±0.05 RES11A30 TBD ±0.05 RES11A40 ±0.01 ±0.05 RES11A50 TBD ±0.05 RES11A90 ±0.01 ±0.05 RES11A00 ±0.01 ±0.05 tD2 Ratio tolerance of divider 2 (1) (RG2 / RIN2) / Gnom – 1 (3) RES11A10 ±0.01 ±0.05 RES11A15 TBD ±0.05 RES11A16 TBD ±0.05 RES11A20 TBD ±0.05 RES11A25 TBD ±0.05 RES11A30 TBD ±0.05 RES11A40 ±0.01 ±0.05 RES11A50 TBD ±0.05 RES11A90 ±0.01 ±0.05 RES11A00 ±0.01 ±0.05 RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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5.5 Electrical Characteristics (continued)

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tM Matching tolerance of dividers 1 and 2 (RG1 / RIN1) / (RG2 / RIN2) – 1 (3) RES11A10 TBD ±0.1 RES11A15 TBD ±0.1 RES11A16 TBD ±0.1 RES11A20 TBD ±0.1 RES11A25 TBD ±0.1 RES11A30 TBD ±0.1 RES11A40 –0.0028 ±0.1 RES11A50 TBD ±0.1 RES11A90 TBD ±0.1 RES11A00 TBD ±0.1 TCR Matched temperature coefficient of resistance (ratio)(1) (5) ppm/°CTA = 0C to 70°C –0.2 TA = –40C to +125°C –0.2 tabs Absolute tolerance (per resistor) (2) –3 ±12 % Absolute temperature coefficient of resistance (per resistor)(2) (5) TA = –40C to +125°C ΔRINx / ΔTA ±20 ppm/°C ΔRGx / (ΔTA × Gnom) ±20 VCR Voltage coefficient of resistance (5) (7) ±0.1 ppm/V Long-term drift (5) TBD hours, unbiased TBD ppm/ √moTBD hours, TBD bias condition TBD IMPEDANCE CIN Pin capacitance (4) RINx, RGx to GND/SUB 1.6 pF RMIDx to GND/SUB 3.2 RINx to RGx 3.2 RMID1 to RMID2 3.2 RIN1 to RIN2 3.2 RG1 to RG2 3.2 Crosstalk (RMID1 to RMID2) (5) Substrate biased to GND, f = 10 kHz –80 dB Substrate floating, f = 10 kHz –75 –3-dB bandwidth (4) Substrate biased to GND TBD MHz Substrate floating TBD CMRR Common-mode rejection ratio (5) RES11A10 66.0 TBD dB RES11A15 68.0 TBD RES11A16 68.5 TBD RES11A20 69.5 TBD RES11A25 70.9 TBD RES11A30 72.0 TBD RES11A40 74.0 105.1 RES11A50 75.6 TBD RES11A90 80.0 TBD RES11A00 80.8 TBD Thermal EMF TBD μV/°C www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: RES11A-Q1

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENVIRONMENTAL TEST RATINGS Shelf (storage) stability 1000 hrs, 125C, unbiased TBD ppm Temperature cycling 1000 cycles, -55C to 125C TBD ppm Moisture resistance 1000 hrs, 85C, 85% RH, unbiased TBD ppm Biased humidity 1000 hrs, 85C, 85% RH, TBD bias TBD ppm Operational life 1000 hrs, 125C, TBD bias TBD ppm Terminal strength MIL-STD-202, Method 211 TBD ppm Mechanical shock MIL-STD-202, Method 213 TBD ppm Vibration MIL-STD-202, Method 204 TBD ppm Resistance to soldering heat MIL-STD-202, Method 210 TBD ppm Thermal shock TBD ppm Solderability J-STD-002 PASS Flammability UL-94 PASS Flame retardance AEC-Q200-01 PASS (1) Relation of RG1 / RIN1 or RG2 / RIN2 to nominal ratio. (2) Relation of RG1, RIN1, RG2, or RIN2 to nominal resistance. (3) The specification is the result of this expression, given as a percentage (multiplied by 100%). (4) Specified by design. (5) Specified by characterization. (6) The specification is the calculated CMRR when implemented in a difference amplifier configuration with an ideal op-amp, such that the only source of common-mode error is the resistor network. Over-frequency effects are not included. If the circuit is configured in an attenuating gain, this result will change. (7) Does not include thermal effects or self-heating in the divider. RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6 Detailed Description

6.1 Overview

The RES11A-Q1 consists of four precision thin-film SiCr resistors, arranged to form two matched dividers. The device has two input resistors, RIN1 and RIN2, both nominally 1 k Ω. The device also has two gain resistors, RG1 and RG2, with values that depend on the nominal ratio (R GX / R INX) of the RES11A-Q1 device in question. The resistors are arranged with RIN1 and RG1 in series to form the first divider, and RIN2 and RG2 in series to form the second divider. Two GND pins are also provided to bias the device substrate.

6.2 Functional Block Diagram

6.3 Feature Description

6.3.1 Ratiometric Matching

The resistors of the RES11A-Q1 are described by the following equations: RIN1 = R INnom × 1±tabs = R INnom × 1±tRIN1 × 1±tSiCr (1) RIN2 = R INnom × 1±tRIN2 × 1±tSiCr (2) RG1 = R Gnom × 1±tRG1 × 1±tSiCr (3) RG2 = R Gnom × 1±tRG2 × 1±tSiCr (4) RINnom and R Gnom are the nominal values of each resistor. The parameter tabs is an error term that describes the absolute tolerance of the RES11A-Q1 device in question, such that | tabs| ≤ 12%. The absolute tolerance is dominated by the variation in the SiCr resistivity, tSiCr. Because the four resistors of a given RES11A-Q1 are interdigitated and come from the same area of the wafer, tSiCr is effectively the same for each of the four resistors, although tSiCr varies on a part-to-part basis. When each divider is considered in ratiometric terms, these error terms drop out, as shown in the following examples. The remaining parameter tRX is an error term that describes the remaining effective tolerance of each resistor of the given RES11A-Q1 device after accounting for the universal tSiCr. RG1 RIN1 = RGnom × 1±tRG1 × 1±tSiCr RINnom × 1±tRIN1 × 1±tSiCr RGnom × 1±tRG1 RINnom × 1±tRIN1 = G nom × 1±tRG1 1±tRIN1 = G 1 (5) RG2 RIN2 = RGnom × 1±tRG2 × 1±tSiCr RINnom × 1±tRIN2 × 1±tSiCr RGnom × 1±tRG2 RINnom × 1±tRIN2 = G nom × 1±tRG2 1±tRIN2 = G 2 (6) RG1 RIN1 + R G1 = RGnom × 1±tRG1 × 1±tSiCr RINnom × 1±tRIN1 × 1±tSiCr + R Gnom × 1±tRG1 × 1±tSiCr RGnom × 1±tRG1 RINnom × 1±tRIN1 + R Gnom × 1±tRG1 (7) RG2 RIN2 + R G2 = RGnom × 1±tRG2 × 1±tSiCr RINnom × 1±tRIN2 × 1±tSiCr + R Gnom × 1±tRG2 × 1±tSiCr RGnom × 1±tRG2 RINnom × 1±tRIN2 + R Gnom × 1±tRG2 (8) www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: RES11A-Q1

The RES11A-Q1 is specified with a maximum divider ratio tolerance of 0.05%, meaning that the relationship between the actual divider ratio GX and nominal ratio Gnom of a given divider X is described by the following: GX = G nom × 1±tDX (9) such that tDX ≤ 0.05%. Because any devices that do not meet these criteria are screened out at final test, these equations can be used with Equation 5 and Equation 6 to prove the effective bounds of tRX. Therefore, despite the device absolute end-to-end tolerance bounds of ± 12%, the effective error tolerances of each resistor (for ratiometric applications) are within approximately ±0.025%, for the worst-case tRX. The RES11A-Q1 is specified with a maximum divider matching tolerance of 0.1%, meaning that the relationship between the ratio of divider 1 (G1) and ratio of divider 2 (G2) is described by the following: G2 = 1±t M (10) By definition, | tM| ≤ 0.1%. Again, the previous equations relate tM to the parameters tDX and tRX. As a result of the interdigitation of the two dividers, the actual typical value of tM is approximately 0.0028%, depending on the specific RES11A-Q1 device. This value is used to calculate the common-mode rejection ratio (CMRR) when implementing a difference amplifier circuit.

6.3.2 Ultra-Low Noise

Noise in resistors can be evaluated in two separate regions: low-frequency flicker noise and wideband thermal noise. Flicker, or 1/f noise, is extremely important for systems that require signal gain at frequencies less than 100 Hz. Thermal noise typically dominates in the region greater than 1 kHz, and increases as resistor magnitude increases. Noise is modeled as a voltage source in series with the resistor. For a resistive divider such as the RES11A-Q1, the thermal noise as measured at the center tap of two resistors, RIN and RG, is equivalent to the thermal noise of a resistor with value RIN || RG: e N = 4k B TR (11) where:

• eN is the thermal noise density in nV/√Hz
• T is the absolute temperature in kelvins (K)
• kB is the Boltzmann constant, 1.381 × 10-23 J/K
• R = RIN || RG As an example, for the RES11A40-Q1 at 25°C: e N = 4k B TR = 4 × 1.38 E − 23 J K × 278 K × 1 k Ω ∥ 4 k Ω = 3.5 nV/ Hz (12)

6.4 Device Functional Modes

The RES11A-Q1 is typically used with the two independently biased resistor dividers. R IN1 and R G1 in series form a resistive divider, with R IN2 and R G2 in series forming another divider. However, the two dividers do not have to be used independently. The resistors can be connected in series or in parallel like any other resistor. Use one of the two GND pins to bias the part substrate. Connect the substrate to signal ground or a similar low-impedance bias point or plane for best noise rejection. While two GND/SUB connection pins are available on the device, connect only one of these to the ground plane. The two GND pins are internally connected through the substrate, which is not intended to conduct significant currents. Connect only one GND pin at a time, and leave the other pin floating, to prevent current return paths from developing through the substrate. RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Discrete Difference Amplifier

The RES11A-Q1 is commonly used to implement a simple difference amplifier. The ratiometric matching between the two resistor dividers improves CMRR performance and gain drift for the circuit, when compared to a similar implementation using unmatched discrete resistors. The basic circuit is shown in Figure 7-1. VOUT = VIN+ − VIN− × RG RIN + V REF (13) VIN+ ADC RES11A-Q1 OPA392 VIN– GND VREF RIN1 RG2 RIN2RG1 VOUT Figure 7-1. Discrete Difference Amplifier Using RES11A-Q1

7.1.1.1 Difference Amplifier Common-Mode Rejection Analysis

In this simple difference amplifier configuration, the nominal CMRR is calculated as: CMRR = 20 × log 10 AD ACM (14) The term A D is the differential gain of the circuit, and the term A CM is the common-mode gain of the circuit. These are defined as the following: AD × = VOUT VD = 0.5 × RG1 RG1 + R IN1 + RG2 RG2 + R IN2 RIN2 RG2 + R IN2 (15) ACM = VOUT VCM = RG1 RG1 + R IN1 − RG2 RG2 + R IN2 RIN2 RG2 + R IN2 (16) www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: RES11A-Q1

Therefore, CMRR = 20 × log 10 2× RG1 × RIN2 + R G2 − RG2 × RIN1 + R G1 RG1 × RIN2 + R G2 + R G2 × RIN1 + R G1 (17) When this expression is evaluated with the definitions given in Section 6.3.1, assuming the worst-case scenario of the most unbalanced divider matching possible, CMRR = 20 × log 10 Gnom +1+ t RX2 1− Gnom 4× t RX (18) Because tRX2 << 1, the worst-case CMRR is approximated as CMRR = 20 × log 10 Gnom +1 4× t RX (19) By definition, the parameter tM describes the effective error that is otherwise equivalent to 4 × tX for an unmatched divider network, and so the maximum value of tM can be used to calculate the same worst-case result. Likewise, the typical value of tM can be used to approximate the typical CMRR. CMRR = 20 × log 10 Gnom +1 tM (20) For example, the worst-case CMRR for a RES11A40-Q1 device with G = 4 is approximately 74.0 dB, with a typical CMRR of approximately 105.1 dB . In comparison, implementation of a comparable G = 4 difference amplifier with unmatched 0.1%-tolerance resistors results in a worst-case CMRR of approximately 62 dB. In a difference amplifier configuration, the CMRR of the op amp contributes error as well. The op-amp CMRR is considered in parallel with the CMRR of the resistor network, as per the below. CMRRTOTAL = 1 CMRRAMP + 1 CMRRRESISTORS (21)

7.1.2 Discrete Instrumentation Amplifiers

The RES11A-Q1 can be used to in conjunction with a dual-channel operational amplifier to implement a discrete instrumentation amplifier (INA). The ratiometric matching between the two resistor dividers improves CMRR performance for the circuit, when compared to a similar implementation using unmatched discrete resistors, and results in better overtemperature and over-aging gain drift characteristics. INAs are often used instead of difference amplifiers when a high input impedance and low bias currents are needed, such as when measuring bridge sensors. Discrete INAs are often configured as a differential-input differential-output circuit, as shown in Figure 7-2. While not shown, an additional discrete difference amplifier stage (requiring a second RES11A-Q1 and another op-amp channel) can be used to convert the differential output voltage to a single-ended voltage if needed (for example, when driving a single-ended ADC). This extra stage can also add an additional offset and provide additional gain, effectively mimicking the common three-amplifier INA architecture. VOUT+ − VOUT− = VIN+ − VIN− × 1+ RG RIN (22) RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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7.1.2.1 Instrumentation Amplifier Common-Mode Rejection Analysis

The differential-input, differential-output instrumentation amplifier shown in Figure 7-2 has a common-mode gain of ACM = 1 V/V. The differential gain is described by the following (assuming an ideal amplifier): AD = RG1 + R G2 RIN1 + R IN2 + 1 = G nom × 1±tRG1 + 1±tRG2 1±tRIN1 + 1±tRIN2 + 1 (24) Because the worst-case-stage CMRR occurs when the differential gain is lowest, and the common-mode gain is unity, the minimum CMRR is evaluated as: AD ACM = G nom × 1–tRG1 + 1–tRG2 1+tRIN1 + 1+tRIN2 + 1 = G nom × 1.9995 2.0005 + 1 (25) For example, for an instrumentation amplifier with RES11A90-Q1, the worst-case CMRR is: AD ACM = G nom × 1–tRG1 + 1–tRG2 1+tRIN1 + 1+tRIN2 + 1 = 9 V/V × 1.9995 2.0005 + 1 = 9.9955 V/V (26)

7.1.3 Fully-differential Amplifier

The RES11A-Q1 can be used to set the gain of a fully-differential amplifier, such as the THP210. The ratiometric matching between the two resistor dividers leads to improved gain matching and CMRR performance for the circuit, when compared to a similar implementation using unmatched discrete resistors. Figure 7-4 shows a generic schematic representation of a fully-differential amplifier driving a differential ADC, with a RES11A-Q1 used to set the amplifier gain. VOUT+ − VOUT− = VIN+ − VIN− × RG RIN (27) VIN+ ADC RES11A-Q1 VIN– RG2 RIN1 RG1RIN2 VOUT+ THP210 VOUT– – + Figure 7-4. Fully-differential Amplifier Gain Setting Using RES11A-Q1 RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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7.2 Typical Application

7.2.1 Common-Mode Shifting Input Stage

The RES11A-Q1 can be used to implement a common-mode attenuator at the high-impedance inputs of an instrumentation amplifier (INA). This configuration extends the usable signal range, so long as the maximum differential voltage limitation of each resistor divider is respected. Figure 7-5 shows an example of a high-side current-sense circuit where a differential voltage, V SHUNT, develops across a sense resistor with an undesirably high common-mode voltage V CM. V REF is used to shift input common-mode voltages V MID1 and V MID2 to levels within the specified input common-mode range of the INA. The amplifier output, VOUT, is a scaled function of VSHUNT, such that nominally: VOUT = V SHUNT × RIN RG + R IN + R EQUIV VOUT can be gained up further by the INA stage, to make maximal use of the effective resolution of a downstream ADC. In practice R EQUIV is optional; however, if R EQUIV = R SHUNT, this resistance equalizes the nominal impedance between V CM and each of the INA high-impedance inputs, thus improving CMRR performance. Select an INA with input bias currents I B1 and IB2 << ISTATIC1 and ISTATIC2, such as the INA333 or INA823. Select a RES11A-Q1 device with a sufficiently high divider series resistance so that ISTATIC1 and ISTATIC2 << ILOAD. RSHUNT VRAIL GND RG1 REQUIV RIN1 VREF GND RG2 RIN2 GND ISTATIC1 ISTATIC2 ILOADILOAD + ISTATIC2ILOAD + ISTATIC1 + ISTATIC2 INA VMID1 VMID2 VOUT ILOAD VSHUNT Figure 7-5. RES11A-Q1 Common-Mode Shifting Circuit To achieve a desired nominal input common-mode voltage, VMID1TARGET, set VREF as follows: VREF = V MID1TARGET × RG + R IN + R EQUIV RG + R EQUIV − VCM × RG + R IN + R EQUIV RG + R EQUIV − 1 (28) www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: RES11A-Q1

7.2.1.1 Design Requirements

Consider a level-shifting application where a high-side current shunt measurement from an 18-V supply rail must be measured by a 3.3-V amplifier and ADC. PARAMETER DESIGN GOAL Input VRAIL 18 V ILOAD 300 mA (maximum) RSHUNT 1 Ω ADC full-scale range (target VOUT) 3.3 V Possible VREF voltages 3.3 V, 0 V

7.2.1.2 Detailed Design Procedure

The design parameters are used with the aforementioned equations to select a nominal target G. When the possible VREFvoltages available in the system are considered, VREF = 0 V with G = 9 is found to result in a V MID1 value of 1.8 V, well within the input common-mode range of a 3.3 ‑V rail-to-rail amplifier such as the OPA392. When the corresponding RES11A90-Q1 is employed, the loss terms I STATIC1 and ISTATIC2 are nominally 1.80 mA and 1.77 mA for I LOAD = 300 mA, resulting in an effective floor of 1.77 mA for I LOAD. For simplicity, the error contributions of the INA stage VOS and IB are ignored. For the INA stage, an integrated TI instrumentation amplifier (IA) can be used. Alternatively, a discrete approach can be implemented using another RES11A-Q1 device or devices, and one or more op amps. For this example, an IA stage is constructed with two channels of a OPA4392 and a second RES11A90-Q1 (RIN3, R G3, R IN4, and RG4). This stage is in turn cascaded with a difference amplifier stage, constructed with the third amplifier channel and a RES11A00-Q1 (RIN5, R G5, R IN6, and R G6). The level-shifting stage gain of 10 –1, multiplied by the instrumentation amplifier stage gain of 10, results in an effective unity-gain transfer function for V SHUNT. Therefore, the differential output voltage for this stage is approximately 0.3 V, with amplifier outputs of 1.936 V and 1.634 V. After the final difference amplifier stage gain of G = 10, the common-mode voltage drops out and the maximum value of the resulting V OUT is nominally 3.0 V, compatible with a single-ended 3.3 ‑V ADC such as the ADS7046. If desired, the fourth channel of the OPA4392 can be used to buffer this output signal and serve as a dedicated ADC driver. RSHUNT VRAIL GND RG1 REQUIV RIN1 GND RG2 RIN2 GND ISTATIC1 ISTATIC2 ILOADILOAD + ISTATIC2ILOAD + ISTATIC1 + ISTATIC2 VMID1 VMID2 ILOAD VSHUNT OPA392 RIN4 RIN3 OPA392 RG4 RG3 RIN6 RG5 GND RIN5 OPA392 RG6 OPA392 VOUT Figure 7-6. High-Side Current Shunt Common-Mode Shifting Circuit RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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7.2.1.3 Application Curves

VS1 3.3 RI N3 1k RI N4 1k RG3 9k ISTATIC1 ISTATIC2 RG1 9k RG2 9k RIN1 1k RIN2 1k + + U2 OPAx392 + + U1 OPAx392 RG4 9k RI N6 1k + + U3 OPAx392 RG6 10k + + U4 OPAx392 REQUIV 1 Figure 7-7. Circuit Model in TINA-TI Figure 7-8. Simulation Results www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: RES11A-Q1

7.3 Power Supply Recommendations

The ratio of a given RES11A-Q1 device dictates the maximum differential voltage rating for the resistor dividers of the device. See the Absolute Maximum Ratings and Recommended Operating Conditions for device-specific values.

7.4 Layout

7.4.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

• Reduce parasitic coupling by running input traces as far away from supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Keep high impedance input signals away from noisy traces.
• Make sure system supply voltages are adequately filtered.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
• Only connect one of the two GND/SUB pins to the ground plane, to prevent the formation of current return paths through the device substrate. Float the other GND/SUB pin.

7.4.2 Layout Examples

In the following examples, the RES11A-Q1 is shown with a VSSOP amplifier and 0402-size decoupling capacitors. Figure 7-9. Single-Layer Difference Amplifier Implementation Figure 7-10. Single-Layer Instrumentation Amplifier Implementation RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

8.1.1.1 PSpice® for TI

PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create subsystem designs and prototype solutions before committing to layout and fabrication, reducing development cost and time to market.

8.1.1.2 TINA-TI™ Simulation Software (Free Download)

TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software or TINA-TI software be installed. Download the free TINA-TI simulation software from the TINA-TI™ software folder.

8.1.1.3 TI Reference Designs

TI reference designs are analog solutions created by TI’s precision analog applications experts. TI reference designs offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI reference designs are available online at https://www.ti.com/reference-designs.

8.1.1.4 Filter Design Tool

The filter design tool is a simple, powerful, and easy-to-use active filter design program. The filter design tool allows the user to create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web-based tool from the Design tools and simulation web page, the filter design tool allows the user to design, optimize, and simulate complete multistage active filter solutions within minutes. RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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8.2 Documentation Support

8.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, THP210 Ultra-Low Offset, High-Voltage, Low-Noise, Precision, Fully-Differential Amplifier data sheet
• Texas Instruments, OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current, Rail-to-Rail I/O, e-trim™ Operational Amplifiers data sheet

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. TINA™ is a trademark of DesignSoft, Inc. PSpice® is a registered trademark of Cadence Design Systems, Inc. All trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2023 * Initial Draft

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: RES11A-Q1

10.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PRES11A00QDDFRQ1 SOT-23- PRES11A10QDDFRQ1 SOT-23- PRES11A150QDDFRQ1 SOT-23- PRES11A16QDDFRQ1 SOT-23- PRES11A20QDDFRQ1 SOT-23- PRES11A25QDDFRQ1 SOT-23- PRES11A30QDDFRQ1 SOT-23- PRES11A40QDDFRQ1 SOT-23- PRES11A50QDDFRQ1 SOT-23- PRES11A90QDDFRQ1 SOT-23- RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PRES11A00QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A10QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A15QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A16QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A20QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A25QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A30QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A40QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A50QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A90QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: RES11A-Q1

10.2 Mechanical Data

www.ti.com PACKAGE OUTLINE C TYP2.95 2.65

1.1 MAX

6X 0.65 8X 0.4 0.2 1.95 TYP0.20 0.08 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A NOTE 3 2.95 2.85 B 1.65 1.55 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A TYPICAL DETAIL A SCALE 4.000 RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4222047/B 11/2015 SYMM SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED www.ti.com RES11A-Q1 SLPS755 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: RES11A-Q1

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R ) TYP0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X RES11A-Q1 SLPS755 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com 27-Oct-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PRES11A40QDDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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