RES11A15

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RES11A Matched, Thin-Film Resistor Dividers With 1-kΩ Inputs DECEMBER 2023

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RES11A Matched, Thin-Film Resistor Dividers With 1-kΩ Inputs

1 Features

Wide temperature range: –40°C to +125°C
High ratio matching precision: ±0.05 % (maximum)
Low drift: ±2 ppm/°C TCR (maximum)

2 Applications

Precision voltage divider, precision level translation
Gain and attenuating amplifiers
Difference amplifiers with high CMRR
Discrete instrumentation amps with high gain accuracy
Fully differential amplifiers with high gain accuracy
Pinpoint comparator threshold setting

3 Description

The RES11A is a matched pair of resistive dividers, implemented in thin-film SiCr with Texas Instruments' modern, high-performance, analog CMOS process. The device has a nominal input resistance of 1 k Ω, for low thermal and current noise, and is available in several nominal ratios to meet a wide array of system needs. Use the RES11A in an inverse gain configuration by simply rotating the device placement by 180°. This feature supports layout reuse and increases flexibility for applications such as discrete instrumentation or difference amplifier implementations. The RES11A series features high ratio-matching precision, with the measured ratio of each divider within ± 120 ppm (typical) of the nominal. This precision is maintained over the temperature range, with a maximum ratio drift of only ±2 ppm/°C. Additionally, the biased long-term stability of the device has been proven through thorough characterization. The RES11A is specified with a temperature range from –40°C to +125°C. The device is offered in an 8‑pin, SOT ‑23-THIN package, with a body size of 2.9 mm × 1.6 mm (body size is a nominal value and does not include pins).

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) RES11A DDF (SOT-23-THIN, 8) 2.9 mm × 2.8 mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Device Information PART NUMBER NOMINAL RATIO RES11A10 1:1 RES11A15 (1) 1:1.5 RES11A16 (1) 1:1.667 RES11A20 (1) 1:2 RES11A25 (1) 1:2.5 RES11A30 (1) 1:3 RES11A40 1:4 RES11A50 (1) 1:5 RES11A90 1:9 RES11A00 1:10 (1) Preview information (not Advanced Information). RIN2 RG2 RIN1 RG1 Substrate RIN1 RMID1 RG1 GND/SUB GND/SUB RIN2 RMID2 RG2 Functional Block Diagram Common-mode Rejection Ratio (dB) Devices (%) 85 90 95 100 105 110 115 120 125 130 10% 15% 20% 25% 30% RES11A40, G = 4 Excellent Ratio Matching for Best CMRR RES11A SLPS785 – DECEMBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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4 Pin Configuration and Functions

1 RIN18 GND/SUB

2 RMID17 RIN2

3 RG16 RMID2

4 GND/SUB5 RG2

Figure 4-1. DDF Package, 8-Pin SOT-23-THN (Top View) Table 4-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. GND/SUB 4, 8 Ground Substrate bias connection. Only bias one GND/SUB pin. Float the other GND/SUB pin to prevent current return paths from forming through the substrate. See also Section 7.4. RG1 3 Input Gain resistor connection for divider 1 RG2 5 Input Gain resistor connection for divider 2 RIN1 1 Input Input resistor connection for divider 1 RIN2 7 Input Input resistor connection for divider 2 RMID1 2 Output Center tap of divider 1 RMID2 6 Output Center tap of divider 2 www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: RES11A

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCM Maximum common mode voltage (any pin to GND/SUB) ±135 V ∆VDMAX Maximum instantaneous overload voltage per divider (RINx pin to RGx pin) (2) RES11A10 ±77.0 V RES11A15 ±64.2 RES11A16 ±63.0 RES11A20 ±57.8 RES11A25 ±89.9 RES11A30 ±102.7 RES11A40 ±96.3 RES11A50 ±94.6 RES11A90 ±128.4 RES11A00 ±135 TA Ambient temperature –55 150 °C TJ Junction temperature –55 150 °C Tstg Storage temperature –55 175 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Maximum instantaneous voltage permitted under transient conditions. Avoid sustained operation at these voltage levels because the resulting self-heating causes TJ to exceed 150°C.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1200 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±2000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. RES11A SLPS785 – DECEMBER 2023 www.ti.com

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5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Maximum common-mode voltage (any pin to GND/SUB) ±120 V Maximum sustained current through RINx (RINx pin to RMIDx pin, 10 years at TA = 25°C) (1) RES11A10 ±8.93 ±12.2 mA RES11A15 ±8.93 ±12.2 RES11A16 ±8.93 ±12.5 RES11A20 ±8.93 ±12.2 RES11A25 ±7.44 ±10.2 RES11A30 ±8.93 ±12.2 RES11A40 ±8.93 ±12.2 RES11A50 ±8.93 ±12.5 RES11A90 ±8.93 ±12.2 RES11A00 ±7.44 ±10.2 Maximum sustained current through RGx (RGx pin to RMIDx pin, 10 years at TA = 25°C) (1) RES11A10 ±8.93 ±12.2 mA RES11A15 ±5.95 ±8.14 RES11A16 ±5.36 ±7.49 RES11A20 ±4.47 ±6.11 RES11A25 ±5.95 ±8.14 RES11A30 ±5.95 ±8.14 RES11A40 ±4.47 ±6.11 RES11A50 ±3.57 ±5.00 RES11A90 ±2.98 ±4.07 RES11A00 ±2.98 ±4.07 TA Ambient temperature –40 125 °C (1) Assumes RθJA = 156.2 °C/W. Applies whether the specified current is applied across a single divider, or both dividers simultaneously. For long-term use under static dc biases, keep the current less than or equal to the nominal value. For long-term use under dynamic conditions, keep the RMS current less than or equal to the maximum value. Adhere to the limitations in Absolute Maximum Ratings.

5.4 Thermal Information

THERMAL METRIC(1) RES11A UNITDDF (SOT-23-THIN)

8 PINS

RθJA Junction-to-ambient thermal resistance 156.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 77.0 °C/W RθJB Junction-to-board thermal resistance 73.7 °C/W ψJT Junction-to-top characterization parameter 4.5 °C/W ψJB Junction-to-board characterization parameter 73.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: RES11A

5.5 Electrical Characteristics

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INITIAL RESISTANCE Gnom Nominal ratio (RGx / RINx) RES11A10 1 V/V RES11A15 1.5 RES11A16 1.667 RES11A20 2 RES11A25 2.5 RES11A30 3 RES11A40 4 RES11A50 5 RES11A90 9 RES11A00 10 tD1 Ratio tolerance of divider 1 (1) (RG1 / RIN1) / Gnom – 1 RES11A10 ±500 ppm RES11A15 ±500 RES11A16 ±500 RES11A20 ±500 RES11A25 ±500 RES11A30 ±500 RES11A40 ±120 ±500 RES11A50 ±500 RES11A90 ±500 RES11A00 ±500 Voltage-divider circuit tolerance of divider 1 (1 + Gnom) × (RIN1 / (RIN1 + RG1)) – 1 RES11A10 ±500 ppm RES11A15 ±500 RES11A16 ±500 RES11A20 ±500 RES11A25 ±500 RES11A30 ±500 RES11A40 ±100 ±500 RES11A50 ±500 RES11A90 ±500 RES11A00 ±500 tD2 Ratio tolerance of divider 2 (1) (RG2 / RIN2) / Gnom – 1 RES11A10 ±500 ppm RES11A15 ±500 RES11A16 ±500 RES11A20 ±500 RES11A25 ±500 RES11A30 ±500 RES11A40 ±120 ±500 RES11A50 ±500 RES11A90 ±500 RES11A00 ±500 RES11A SLPS785 – DECEMBER 2023 www.ti.com

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5.5 Electrical Characteristics (continued)

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage-divider circuit tolerance of divider 2 (1 + Gnom) × (RIN2 / (RIN2 + RG2)) – 1 RES11A10 ±500 ppm RES11A15 ±500 RES11A16 ±500 RES11A20 ±500 RES11A25 ±500 RES11A30 ±500 RES11A40 ±100 ±500 RES11A50 ±500 RES11A90 ±500 RES11A00 ±500 tM Matching tolerance of dividers 1 and 2 tD2 – tD1 RES11A10 ±1000 ppm RES11A15 ±1000 RES11A16 ±1000 RES11A20 ±1000 RES11A25 ±1000 RES11A30 ±1000 RES11A40 ±85 ±1000 RES11A50 ±1000 RES11A90 ±1000 RES11A00 ±1000 tabs Absolute tolerance (per resistor) Absolute tolerance span MAX (tabsRIN1, tabsRG1, tabsRIN2, tabsRG2) – MIN (tabsRIN1, tabsRG1, tabsRIN2, tabsRG2) ±235 ppm RESISTANCE DRIFT Absolute temperature coefficient of resistance (per resistor) (4) (ΔRx / Rx(25°C)) / ΔTA TA = –40C to +125°C ±18 ppm/°C Divider temperature coefficient of resistance (per divider) (4) ΔtDx / ΔTA TA = –40C to +125°C –0.2 ±2 ppm/°C TCR Matching temperature coefficient of resistance (4) ΔtM / ΔTA TA = –40C to +125°C ±0.05 ppm/°C Absolute voltage coefficient of resistance (per resistor)(2) (4) ΔRINx / ΔVRINx VRINx = 0 V to VRINx = 40 V ±0.02 Ω/V ΔRGx / (ΔVRGx × Gnom) VRGx = 0 V to VRGx = 40 V ±0.02 Divider voltage coefficient of resistance (per divider) (4) ΔtDx / ΔVDx VDx = 0 V to VDx = 40 V ±2 ppm/V VCR Matching voltage coefficient of resistance (4) (ΔtD2 – ΔtD1) / ΔVDx VDx = 0 V to VDx = 40 V ±0.5 ppm/V IMPEDANCE CIN Pin capacitance (4) RINx to GND/SUB 2.2 pFRGx to GND/SUB 1.6 RMIDx to GND/SUB 3.3 Crosstalk (RMID1 to RMID2) (4) Substrate biased to GND f = 10 kHz –100 dB f = 1 MHz –64 Substrate floating f = 10 kHz –98 f = 1 MHz –56 www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: RES11A

at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –3-dB bandwidth (4) Substrate biased to GND 35 MHz Substrate floating 40 CMRR Common-mode rejection ratio (5) RES11A10 66.0 dB RES11A15 68.0 RES11A16 68.5 RES11A20 69.5 RES11A25 70.9 RES11A30 72.0 RES11A40 74.0 95.4 RES11A50 75.6 RES11A90 80.0 RES11A00 80.8 (1) Relation of RG1 / RIN1 or RG2 / RIN2 to nominal ratio. (2) Relation of RG1, RIN1, RG2, or RIN2 to nominal resistance. (3) The specification is the result of this expression, given as a percentage (multiplied by 100%). (4) Specified by characterization. (5) The specification is the calculated CMRR when implemented in a difference amplifier configuration with an ideal op-amp, such that the only source of common-mode error is the resistor network. See the Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note for more information. Effects over frequency are not included. If the circuit is configured in an attenuating gain, this result changes accordingly. RES11A SLPS785 – DECEMBER 2023 www.ti.com

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5.6 Typical Characteristics

at TA = 25°C (unless otherwise noted) tD1 (ppm) Devices (%) -150 -100 -50 0 50 100 150 RES11A40 RES11A40 n = 1411, 1 lot Figure 5-1. tD1 Distribution tD2 (ppm) Devices (%) -50 -25 0 25 50 75 100 125 150 175 200 225 250 RES11A40 RES11A40 n = 1411, 1 lot Figure 5-2. tD2 Distribution tM (ppm) Devices (%) -50 -25 0 25 50 75 100 125 150 175 200 225 250 RES11A40 RES11A40 n = 1411, 1 lot Figure 5-3. tM Distribution Absolute Tolerance Span (ppm) Devices (%) 0 25 50 75 100 125 150 175 200 225 250 RES11A40 RES11A40 n = 1411, 1 lot Figure 5-4. Absolute Tolerance Span Distribution Ambient Temperature (C) Device Power Dissipation (W) -60 -40 -20 0 20 40 60 80 100 120 140 160 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 RJA = 156.2 C/W Figure 5-5. Maximum Power Dissipation Temperature (°C) Resistor Mismatch (-ppm) -75 -50 -25 0 25 50 75 100 125 150 -25 -20 -15 -10 RG RIN RES11A40 Figure 5-6. Rx2 – Rx1 vs Temperature www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: RES11A

5.6 Typical Characteristics (continued)

at TA = 25°C (unless otherwise noted) Temperature (°C) Input Resistance, RIN () -75 -50 -25 0 25 50 75 100 125 150 979 979.5 980 980.5 981 981.5 982 982.5 983 Divider 1 Divider 2 RES11A40 Figure 5-7. RINx vs Temperature Temperature (°C) Gain Resistance, RG () -75 -50 -25 0 25 50 75 100 125 150 3916 3918 3920 3922 3924 3926 3928 3930 3932 Divider 1 Divider 2 RES11A40 Figure 5-8. RGx vs Temperature Temperature (°C) Divider 1 Ratio Error, tD1 (ppm) -75 -50 -25 0 25 50 75 100 125 150 -120 -100 -80 -60 -40 -20 Unit 1 Unit 2 Unit 3 RES11A40 Figure 5-9. tD1 vs Temperature RES11A40 Figure 5-10. tD2 vs Temperature tD1 Drift Error (ppm/°C) Devices (%) RES11A40 n = 92 Figure 5-11. tD1 Drift Distribution tD2 Drift Error (ppm/°C) Devices (%) RES11A40 n = 96 Figure 5-12. tD2 Drift Distribution RES11A SLPS785 – DECEMBER 2023 www.ti.com

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at TA = 25°C (unless otherwise noted) Temperature (°C) Ratio Mismatch, tM (ppm) -75 -50 -25 0 25 50 75 100 125 150 -100 -75 -50 -25 100 Unit 1 Unit 2 Unit 3 RES11A40 Figure 5-13. tM vs Temperature tM Drift Error (ppm/°C) Devices (%) RES11A40 n = 95 Figure 5-14. tM Drift Distribution Voltage (V) Resistance () 5 10 15 20 25 30 35 40 969.75 970 970.25 970.5 970.75 971 RIN1 Calculated RIN2 Calculated RIN1 Measured RIN2 Measured RES11A40 Normalized to Rx(5V) Figure 5-15. RINx vs Bias Voltage (V) Resistance () 5 10 15 20 25 30 35 40 3878.5 3879 3879.5 3880 3880.5 3881 3881.5 3882 3882.5 3883 3883.5 RG1 Calculated RG2 Calculated RG1 Measured RG2 Measured RES11A40 Normalized to Rx(5V) Figure 5-16. RGx vs Bias Voltage (V) Resistance () 5 10 15 20 25 30 35 40 -0.1 -0.075 -0.05 -0.025 0.025 0.05 0.075 0.1 0.125 0.15 RIN1 Error RIN2 Error RES11A40 RINx actual – RINx predicted, normalized to Rx(5V) Figure 5-17. RINx Actual-to-Expected Mismatch Error vs Bias Voltage (V) Resistance () 5 10 15 20 25 30 35 40 -0.5 -0.25 0.25 0.5 RG1 Error RG2 Error RES11A40 RGx actual – RGx predicted, normalized to Rx(5V) Figure 5-18. RGx Actual-to-Expected Mismatch Error vs Bias www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: RES11A

at TA = 25°C (unless otherwise noted) Voltage (V) Ratio Error, tDx (ppm) 5 10 15 20 25 30 35 40 -150 -120 -90 -60 -30 tD1 Measured tD2 Measured tD1 Calculated tD2 Calculated RES11A40 Normalized to tDx(5V) Figure 5-19. tDx vs Bias Voltage (V) Ratio Mismatch, tM (ppm) 5 10 15 20 25 30 35 40 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 tM Measured tM Calculated RES11A40 Normalized to tM(5V) Figure 5-20. tM vs Bias Frequency (Hz) Gain (dB) Phase (°) -36 -240 -30 -180 -24 -120 -18 -60 -12 0 -6 60 0 120 1M 10M 100M Gain (dB) Phase (°) RES11A40 VRINx = VTEST, VRGx = 0 V Figure 5-21. Bandwidth vs Frequency, RINx Frequency (Hz) Gain (dB) Phase (°) -40 -240 -35 -180 -30 -120 -25 -60 -20 0 -15 60 -10 120 1M 10M 100M Gain (dB) Phase (°) RES11A40 VRGx = VTEST, VRINx = 0 V Figure 5-22. Bandwidth vs Frequency, RGx Frequency (Hz) Crosstalk (dB) -140 -120 -100 -80 -60 -40 -20 100 1k 10k 100k 1M 10M Floating Substrate Grounded Substrate RES11A40 Figure 5-23. Crosstalk vs Frequency Frequency (Hz) Common-mode Rejection Ratio (dB) 100 105 10 100 1000 10000 100000 RES11A40 Difference amplifier with OPA210 Figure 5-24. CMRR vs Frequency RES11A SLPS785 – DECEMBER 2023 www.ti.com

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6 Parameter Measurement Information

6.1 DC Measurement Configurations

An example of the circuit configuration used for dc measurements is shown in Figure 6-1. Voltage VDx refers to the voltage across a given divider, such as V D1 for divider 1. Voltage V Rx refers to the voltage across a given resistor, such as VRIN1 for RIN1 or VRG1 for RG1. RES11A RIN1 RG2 RIN2RG1 – VD1 VRIN1 VRG1 Figure 6-1. DC Measurement Terminology for Divider 1 When the RES11A is used to set the gain of an op amp (shown in Figure 6-2 ), the ratio of the resistors in a divider sets the amplifier gain according to G = R G / RIN. Discrete-difference-amplifier and instrumentation- amplifier circuits are variations on this ratiometric use case. Typical and maximum parameter values for ratio tolerance (tD1, tD2) are expressed in terms of RGx / RINx to simplify calculations for these circuits. However, another valid use case of the RES11A is a simple voltage divider, where the midpoint voltage V MID is equal to the input voltage VD multiplied by RG / (RIN + RG), or by RIN / (RIN + RG) as shown in Figure 6-3. Typical and maximum parameter values for ratio tolerance of these voltage-divider circuits, expressed in terms of R INx / (RINx + RGx), are provided. GND VIN RIN RG VOUT Figure 6-2. Amplifier Gain Circuit VMID RG RIN GND VD Figure 6-3. Voltage-divider circuit Figure 6-4 shows the circuit configuration used for CMRR calculations. For an ideal amplifier with no offset and infinite CMRR, the effective circuit CMRR is entirely a function of the matching of the resistors. See Section 8.1.1.1 and the Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note for more information. VIN+ RES11A Ideal Amplifier VIN– RIN1 RG2 RIN2RG1 VOUT GND Figure 6-4. CMRR Calculation Reference Schematic www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: RES11A

6.2 AC Measurement Configurations

Figure 6-5 shows the circuit configuration used for capacitance measurements. For the RES11A, a 1 ‑MΩ RKNOWN resistance and 10 ‑pF C KNOWN capacitance are used. The circuit creates an impedance divider; the resulting gain-vs-frequency relationship is used to calculate the parasitic capacitance in parallel with the resistor under test (in this case, RIN1). Calibration with an empty socket is performed to account for board parasitics. The ac source is swept from 100 Hz to 50 MHz. Network Analyzer RES11A RIN1 RG2 RIN2RG1 GND GNDRKNOWN CKNOWN GND VSOURCE GND GND/SUB Figure 6-5. Capacitance Measurement Reference Schematic Figure 6-6 shows the circuit configuration that is used for bandwidth measurements. The ac source is swept from 100 kHz to 500 MHz. Network Analyzer RES11A RIN1 RG2 RIN2RG1 GND GND GND GND VSOURCE GND/SUB Figure 6-6. Bandwidth Measurement Reference Schematic Figure 6-7 shows the circuit configuration used for crosstalk measurements. The ac source is swept from 100 Hz to 100 MHz. Network Analyzer RES11A RIN1 RG2 RIN2RG1+ GND GND GND GND VSOURCE GND/SUB Figure 6-7. Crosstalk Measurement Reference Schematic RES11A SLPS785 – DECEMBER 2023 www.ti.com

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7 Detailed Description

7.1 Overview

The RES11A consists of four precision thin-film SiCr resistors, arranged to form two matched dividers. The device has two input resistors, R IN1 and R IN2, both nominally 1 k Ω. The device also has two gain resistors, RG1 and RG2, with values that depend on the nominal ratio (R Gx / RINx) of the RES11A device in question. The resistors are arranged with RIN1 and RG1 in series to form the first divider, and RIN2 and RG2 in series to form the second divider. Two GND pins are also provided to bias the device substrate.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Ratiometric Matching

The resistors of the RES11A are described by the following equations: RIN1 = R INnom × 1+tabs = R INnom × 1+tRIN1 × 1+tSiCr (1) RIN2 = R INnom × 1+tRIN2 × 1+tSiCr (2) RG1 = R Gnom × 1+tRG1 × 1+tSiCr (3) RG2 = R Gnom × 1+tRG2 × 1+tSiCr (4) RINnom and R Gnom are the nominal values of each resistor. The parameter tabs is an error term that describes the absolute tolerance of the RES11A device in question, such that | tabs| ≤ 12%. The absolute tolerance is dominated by the variation in the SiCr resistivity, tSiCr. The four resistors of a given RES11A are interdigitated and come from the same area of the wafer; therefore, tSiCr is effectively the same for each of the four resistors, although tSiCr varies on a part-to-part basis. The following examples show that when each divider is considered in ratiometric terms, these error terms drop out. Parameter tRx is an error term that describes the remaining effective tolerance of each resistor of the given RES11A device after accounting for the universal tSiCr. RGx RINx = RGnom × 1+tRGx × 1+tSiCr RINnom × 1+tRINx × 1+tSiCr RGnom × 1+tRGx RINnom × 1+tRINx = G nom × 1+tRGx 1+tRINx = G x (5) RINx RINx + R Gx = RINnom × 1+tRINx × 1+tSiCr RINnom × 1+tRINx × 1+tSiCr + R Gnom × 1+tRGx × 1+tSiCr RINnom × 1+tRINx RINnom × 1+tRINx + R Gnom × 1+tRGx (6) The RES11A is specified with a maximum divider ratio tolerance of 0.05%, meaning that the relationship between the actual divider ratio Gx and nominal ratio Gnom of a given divider x is described by the following: Gx = G nom × 1+tDx (7) www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: RES11A

such that tDx ≤ 0.05%. Because any devices that do not meet these criteria are screened out at final test, these equations can be used with Equation 5 to prove the effective bounds of tRx. Therefore, despite the device absolute end-to-end tolerance bounds of ± 12%, the effective error tolerances of each resistor (for ratiometric applications) are within approximately ±0.025%, for the worst-case tRx. The RES11A is specified with a maximum divider matching tolerance of 0.1%, meaning that the relationship between the ratio of divider 1 (G1) and ratio of divider 2 (G2) is described by the following: tM = t D2 – t D1 = G2 – G 1 Gnom (8) By definition, | tM| ≤ 0.1%. Again, the previous equations relate tM to the parameters tDX and tRX. As a result of the interdigitation of the two dividers, the actual typical magnitude of tM is significantly lower than this maximum value, depending on the specific RES11A device. This value is used to calculate the common-mode rejection ratio (CMRR) when implementing a difference amplifier circuit. For example, typical tM for the RES11A40 is approximately 85 ppm, and the typical CMRR is 95.4 dB.

7.3.2 Ratiometric Drift

The ratiometric matching of the RES11A provides a benefit not just for initial conditions, but also when considering parametric drift. The resistors must be considered individually, in absolute terms, and ratiometrically to each other, in matched terms. The absolute temperature coefficients of each resistor show strong correlation, with the coefficient of R IN1 comparable to that of R IN2 and the coefficient of R G1 comparable to that of R G2. The absolute temperature coefficient (in Ω/°C) of each R G is approximately G nom times greater than that of the comparable RIN; hence, the normalized absolute temperature coefficient (in ppm/°C) of every resistor is about the same. Because the resistors of the RES11A are interdigitated, and occupy a small footprint, the die temperature of the device is effectively common to each of the four resistors. As the temperature changes, each resistor experiences a similar temperature rise. Because the resistors have very similar temperature coefficients, the ratio of RG to RIN is well preserved. For example, the RES11A40 has a typical absolute temperature coefficient of approximately 18 ppm/°C for R IN or R G. When considered in ratiometric terms, the typical temperature coefficient of tD1 or tD2 is –0.2 ppm/°C, and the temperature coefficient of tM is 0.05 ppm/°C. RES11A SLPS785 – DECEMBER 2023 www.ti.com

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7.3.3 Predictable Voltage Coefficient

The voltage coefficients of the RES11A are almost entirely related to self-heating, where the power dissipated in the device raises the die temperature. As previously mentioned, the commonality of this temperature rise leads to a comparable shift in each resistor, such that the divider ratio is well preserved. Applying voltage V across resistor or divider R results in the loss of a corresponding power dissipation of P = V2 / R, in the form of heat in the device die. This heat leads to a localized increase in the junction temperature, which in turn causes the same parametric shifts previously discussed in the context of temperature coefficients. TCR is specified as a function of ambient temperature; therefore, use the effective junction-to-ambient thermal resistance to determine the effective temperature rise and calculate the nominal or expected shift. Rexpected = VR2 R × R θJA effective × TCR abs × R (9) Voltage (V) Resistance () 5 10 15 20 25 30 35 40 969.75 970 970.25 970.5 970.75 971 RIN1 Calculated RIN2 Calculated RIN1 Measured RIN2 Measured Figure 7-1. RIN Resistance vs Voltage Voltage (V) Resistance () 5 10 15 20 25 30 35 40 3878.5 3879 3879.5 3880 3880.5 3881 3881.5 3882 3882.5 3883 3883.5 RG1 Calculated RG2 Calculated RG1 Measured RG2 Measured Figure 7-2. RG Resistance vs Voltage The difference of the expected value of R from the actual value of R describes the actual-to-expected mismatch error of R, due to non-temperature-related effects on the voltage coefficient. Similar to the logarithmic conformity error of a logarithmic amplifier or the integrated nonlinearity error of an ADC, this error describes the deviations of the actual device behavior from the predictable behavior. While the absolute magnitude of the shift varies, the slope or trend is predictable. Voltage (V) Resistance () 5 10 15 20 25 30 35 40 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 RIN1 Error RIN2 Error RG1 Error RG2 Error Figure 7-3. Resistor Actual-to-expected Mismatch vs Voltage The measured value of R for low bias (measured by sourcing a very small current) is used with the actual value of R to calculate the effective voltage coefficient of resistance. www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: RES11A

Voltage coefficient (Ω/V) = Rbiased – R initial Vbias (10) This exercise is repeated for each R x, tD1, tD2, and tM, to calculate the voltage coefficients associated with each parameter. For example, the RES11A40 has a typical absolute voltage coefficient of approximately 0.02 Ω/V for RIN or RG. When considered in ratiometric terms, the typical voltage coefficient of t D1 or tD2 is 2 ppm/V, and the voltage coefficient of tM is 0.5 ppm/V.

7.3.4 Ultra-Low Noise

Noise in resistors can be evaluated in two separate regions: low-frequency flicker noise and wideband thermal noise. Flicker, or 1/f noise, is extremely important for systems that require signal gain at frequencies less than 100 Hz. Thermal noise typically dominates in the region greater than 1 kHz, and increases as resistor magnitude increases. Noise is modeled as a voltage source in series with the resistor. For a resistive divider such as the RES11A, the thermal noise as measured at the center tap of two resistors, RIN and RG, is equivalent to the thermal noise of a resistor with value RIN || RG: e N = 4k B TR (11) where:

eN is the thermal noise density in nV/√Hz
T is the absolute temperature in kelvins (K)
kB is the Boltzmann constant, 1.381 × 10-23 J/K
R = RIN || RG As an example, for the RES11A40 at 25°C: e N = 4k B TR = 4 × 1.38 E − 23 J K × 278 K × 1 k Ω ∥ 4 k Ω = 3.5 nV/ Hz (12)

7.4 Device Functional Modes

The RES11A is typically used with the two independently biased resistor dividers. R IN1 and RG1 in series form a resistive divider, with RIN2 and RG2 in series forming another divider. However, the two dividers do not have to be used independently. The resistors can be connected in series or in parallel like any other resistor. Use one of the two GND pins to bias the part substrate. Connect the substrate to signal ground or a similar low-impedance bias point or plane for best noise rejection. While two GND/SUB connection pins are available on the device, connect only one of these to the ground plane. The two GND pins are internally connected through the substrate, which is not intended to conduct significant currents. Connect only one GND pin at a time and leave the other pin floating to prevent current return paths from developing through the substrate. RES11A SLPS785 – DECEMBER 2023 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Discrete Difference Amplifier

The RES11A is commonly used to implement a simple difference amplifier. The ratiometric matching between the two resistor dividers improves CMRR performance and gain drift for the circuit, when compared to a similar implementation using unmatched discrete resistors. The basic circuit is shown in Figure 8-1. VOUT = VIN+ − VIN− × RG RIN + V REF (13) VIN+ ADC RES11A OPA392 VIN– GND VREF RIN1 RG2 RIN2RG1 VOUT Figure 8-1. Discrete Difference Amplifier Using RES11A

8.1.1.1 Difference-Amplifier Common-Mode Rejection Analysis

In this simple difference amplifier configuration, the nominal CMRR is calculated as: CMRR = 20 × log 10 AD ACM (14) The term A D is the differential gain of the circuit, and the term A CM is the common-mode gain of the circuit. These are defined as the following: AD × = VOUT VD = 0.5 × RG1 RG1 + R IN1 + RG2 RG2 + R IN2 RIN2 RG2 + R IN2 (15) ACM = VOUT VCM = RG1 RG1 + R IN1 − RG2 RG2 + R IN2 RIN2 RG2 + R IN2 (16) Therefore, www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: RES11A

CMRR = 20 × log 10 2× RG1 × RIN2 + R G2 − RG2 × RIN1 + R G1 RG1 × RIN2 + R G2 + R G2 × RIN1 + R G1 (17) When this expression is evaluated with the definitions given in Section 7.3.1, assuming the worst-case scenario of the most unbalanced divider matching possible, CMRR = 20 × log 10 Gnom +1+ t Rx2 1− Gnom 4× t Rx (18) Because tRx2 << 1, the worst-case CMRR is approximated as CMRR = 20 × log 10 Gnom +1 4× t Rx (19) By definition, the parameter tM describes the effective error that is otherwise equivalent to 4 × tx for an unmatched divider network, and so the maximum value of tM can be used to calculate the same worst-case result. Likewise, the typical value of tM can be used to approximate the typical CMRR. CMRR = 20 × log 10 Gnom +1 tM (20) For example, the worst-case CMRR for a RES11A40 device with G = 4 is approximately 74.0 dB, with a typical CMRR of approximately 95.4 dB. In comparison, implementation of a comparable G = 4 difference amplifier with unmatched 0.1%-tolerance resistors results in a worst-case CMRR of approximately 62 dB. In a difference amplifier configuration, the CMRR of the op amp contributes error as well. The op-amp CMRR is considered in parallel with the CMRR of the resistor network, as per the following equation: CMRRTOTAL = 1 CMRRAMP + 1 CMRRRESISTORS (21) Additional mismatches in the divider end-to-end resistances reduce the effective CMRR of a difference amplifier. While the low absolute tolerance span of the RES11A (235 ppm typical) helps reduce these concerns, parasitic trace resistances can lead to additional mismatches that impact the CMRR specs. Bench results from a difference amplifier implementation of the RES11A40 and the OPA210 are presented for various deliberate input-impedance mismatches. Input Frequency (Hz) Common-mode Rejection Ratio (dB) 100 105 10 100 1000 10000 100000 0- Mismatch 0.25- Mismatch 0.5- Mismatch 1- Mismatch 2- Mismatch 5- Mismatch Figure 8-2. Effect of Input Impedance Mismatch on Common-mode Rejection Ratio

8.1.2 Discrete Instrumentation Amplifiers

The RES11A can be used to in conjunction with a dual-channel operational amplifier to implement a discrete instrumentation amplifier (INA). The ratiometric matching between the two resistor dividers improves CMRR performance for the circuit when compared to a similar implementation using unmatched discrete resistors, RES11A SLPS785 – DECEMBER 2023 www.ti.com

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8.1.2.1 Instrumentation Amplifier Common-Mode Rejection Analysis

The differential-input, differential-output instrumentation amplifier shown in Figure 8-3 has a common-mode gain of ACM = 1 V/V. The differential gain is described by the following (assuming an ideal amplifier): AD = RG1 + R G2 RIN1 + R IN2 + 1 = G nom × 1±tRG1 + 1±tRG2 1±tRIN1 + 1±tRIN2 + 1 (24) Because the worst-case-stage CMRR occurs when the differential gain is lowest, and the common-mode gain is unity, the minimum CMRR is evaluated as: AD ACM = G nom × 1–tRG1 + 1–tRG2 1+tRIN1 + 1+tRIN2 + 1 = G nom × 1.9995 2.0005 + 1 (25) For example, for an instrumentation amplifier with RES11A90, the worst-case CMRR is: AD ACM = G nom × 1–tRG1 + 1–tRG2 1+tRIN1 + 1+tRIN2 + 1 = 9 V/V × 1.9995 2.0005 + 1 = 9.9955 V/V (26)

8.1.3 Fully Differential Amplifier

The RES11A can be used to set the gain of a fully differential amplifier, such as the THP210. The ratiometric matching between the two resistor dividers leads to improved gain matching and CMRR performance for the circuit, when compared to a similar implementation using unmatched discrete resistors. Figure 8-5 shows a generic schematic representation of a fully differential amplifier driving a differential ADC, with a RES11A used to set the amplifier gain. VOUT+ − VOUT− = VIN+ − VIN− × RG RIN (27) VIN+ ADC RES11A VIN– RG2 RIN1 RG1RIN2 VOUT+ THP210 VOUT– – + Figure 8-5. Fully-differential Amplifier Gain Setting Using RES11A RES11A SLPS785 – DECEMBER 2023 www.ti.com

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8.2 Typical Application

8.2.1 Common-Mode Shifting Input Stage

The RES11A can be used to implement a common-mode attenuator at the high-impedance inputs of an instrumentation amplifier (INA). This configuration extends the usable signal range, so long as the maximum differential voltage limitation of each resistor divider is respected. Figure 8-6 shows an example of a high-side current-sense circuit where a differential voltage, V SHUNT, develops across a sense resistor with an undesirably high common-mode voltage V CM. V REF is used to shift input common-mode voltages V MID1 and V MID2 to levels within the specified input common-mode range of the INA. The amplifier output, VOUT, is a scaled function of VSHUNT, such that nominally: VOUT = V SHUNT × RIN RG + R IN + R EQUIV (28) VOUT can be gained up further by the INA stage, to make maximal use of the effective resolution of a downstream ADC. In practice R EQUIV is optional; however, if R EQUIV = R SHUNT, this resistance equalizes the nominal impedance between V CM and each of the INA high-impedance inputs, thus improving CMRR performance. Select an INA with input bias currents I B1 and IB2 << ISTATIC1 and ISTATIC2, such as the INA333 or INA823. Select a RES11A device with a sufficiently high divider series resistance so that I STATIC1 and ISTATIC2 << ILOAD. RSHUNT VBUS GND RG1 REQUIV RIN1 VREF GND RG2 RIN2 GND ISTATIC1 ISTATIC2 ILOADILOAD + ISTATIC2ILOAD + ISTATIC1 + ISTATIC2 INA VMID1 VMID2 VOUT ILOAD VSHUNT Figure 8-6. RES11A Common-Mode Shifting Circuit To achieve a desired nominal input common-mode voltage, VMID1TARGET, set VREF as follows: VREF = V MID1TARGET × RG + R IN + R EQUIV RG + R EQUIV − VCM × RG + R IN + R EQUIV RG + R EQUIV − 1 (29) www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: RES11A

8.2.1.1 Design Requirements

Consider a level-shifting application where a high-side current shunt measurement from an 18-V supply rail must be measured by a 3.3-V amplifier and ADC. PARAMETER DESIGN GOAL Input VBUS 18 V ILOAD 300 mA (maximum) RSHUNT 1 Ω ADC full-scale range (target VOUT) 3.3 V Possible VREF voltages 3.3 V, 0 V

8.2.1.2 Detailed Design Procedure

The design parameters are used with the aforementioned equations to select a nominal target G. When the possible VREF voltages available in the system are considered, VREF = 0 V with G = 9 is found to result in a VMID1 value of 1.8 V, well within the input common-mode range of a 3.3 ‑V rail-to-rail amplifier such as the OPA392. When the corresponding RES11A90 is employed, the loss terms I STATIC1 and I STATIC2 are nominally 1.80 mA and 1.77 mA for I LOAD = 300 mA, resulting in an effective floor of 1.77 mA for I LOAD. For simplicity, the error contributions of the INA stage VOS and IB are ignored. For the INA stage, an integrated TI instrumentation amplifier (IA) can be used. Alternatively, a discrete approach can be implemented using another RES11A device or devices, and one or more op amps. For this example, an IA stage is constructed with two channels of a OPA4392 and a second RES11A90 (RIN3, RG3, RIN4, and R G4). This stage is in turn cascaded with a difference amplifier stage, constructed with the third amplifier channel and a RES11A00 (RIN5, RG5, RIN6, and R G6). The level-shifting stage gain of 10 –1, multiplied by the instrumentation amplifier stage gain of 10, results in an effective unity-gain transfer function for VSHUNT. Therefore, the differential output voltage for this stage is approximately 0.3 V, with amplifier outputs of 1.936 V and 1.634 V. After the final difference amplifier stage gain of G = 10, the common-mode voltage drops out and the maximum value of the resulting VOUT is nominally 3.0 V, compatible with a single-ended 3.3 ‑V ADC such as the ADS7046. If desired, the fourth channel of the OPA4392 can be used to buffer this output signal and serve as a dedicated ADC driver. RSHUNT VBUS GND RG1 REQUIV RIN1 GND RG2 RIN2 GND ISTATIC1 ISTATIC2 ILOADILOAD + ISTATIC2ILOAD + ISTATIC1 + ISTATIC2 VMID1 VMID2 ILOAD VSHUNT OPA392 RIN4 RIN3 OPA392 RG4 RG3 RIN6 RG5 GND RIN5 OPA392 RG6 OPA392 VOUT Figure 8-7. High-Side Current Shunt Common-Mode Shifting Circuit RES11A SLPS785 – DECEMBER 2023 www.ti.com

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8.2.1.3 Application Curves

VS1 3.3 RI N3 1k RI N4 1k RG3 9k ISTATIC1 ISTATIC2 RG1 9k RG2 9k RIN1 1k RIN2 1k + + U2 OPAx392 + + U1 OPAx392 RG4 9k RI N6 1k + + U3 OPAx392 RG6 10k + + U4 OPAx392 REQUIV 1 Figure 8-8. Circuit Model in TINA-TI Shunt Current (mA) Divider Current (mA) 0 30 60 90 120 150 180 210 240 270 300 1.76 1.765 1.77 1.775 1.78 1.785 1.79 1.795 1.8 1.805 1.81 ISTATIC2 ISTATIC1 Figure 8-9. Simulation Result for ISTATIC Shunt Current (mA) Divider Midpoint Voltage (V) 0 30 60 90 120 150 180 210 240 270 300 1.76 1.765 1.77 1.775 1.78 1.785 1.79 1.795 1.8 1.805 1.81 VMID2 VMID1 Figure 8-10. Simulation Result for VMID Shunt Current (mA) Output Voltage (V) 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOUT Figure 8-11. Simulation Result for VOUT www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: RES11A

8.3 Power Supply Recommendations

The ratio of a given RES11A device dictates the maximum differential voltage rating for the resistor dividers of the device. See the Absolute Maximum Ratings and Recommended Operating Conditions for device-specific values under transient and sustained bias conditions, respectively. See Figure 8-12 for approximate values, assuming RθJA = 156.2°C/W and that both dividers are biased to the same dc voltage at the same time. Keep T J less than the absolute maximum rating of 150°C. Ambient Temperature (C) Maximum Recommended Divider Voltage (V) 70 80 90 100 110 120 130 140 150 RES11A10 RES11A15 RES11A16 RES11A20 RES11A25 RES11A30 RES11A40 RES11A50 RES11A90 RES11A00 Figure 8-12. Maximum Recommended Divider Voltage vs Ambient Temperature

8.4 Layout

8.4.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

Reduce parasitic coupling by running input traces as far away from supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible.
Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. For differential circuits, match the length of the input traces as best possible.
Keep high impedance input signals away from noisy traces.
Make sure system supply voltages are adequately filtered.
Clean the PCB following board assembly for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
Only connect one of the two GND/SUB pins to the ground plane, to prevent the formation of current return paths through the device substrate. Float the other GND/SUB pin. RES11A SLPS785 – DECEMBER 2023 www.ti.com

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8.4.2 Layout Examples

In the following examples, the RES11A is shown with a VSSOP amplifier and 0402-size decoupling capacitors. Figure 8-13. Single-Layer Difference Amplifier Implementation Figure 8-14. Single-Layer Instrumentation Amplifier Implementation Figure 8-15. Front-and-Back Instrumentation Amplifier Implementation Figure 8-16. Front-and-Back, Differential-Output Instrumentation Amplifier Implementation www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: RES11A

For Figure 8-17, two RES11A devices (bottom side) and one dual-channel op-amp (top side) are used. Figure 8-17. Front-and-Back Dual Difference Amplifiers Implementation RES11A SLPS785 – DECEMBER 2023 www.ti.com

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

9.1.1.1 PSpice® for TI

PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create subsystem designs and prototype solutions before committing to layout and fabrication, reducing development cost and time to market.

9.1.1.2 TINA-TI™ Simulation Software (Free Download)

TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software or TINA-TI software be installed. Download the free TINA-TI simulation software from the TINA-TI™ software folder.

9.1.1.3 TI Reference Designs

TI reference designs are analog solutions created by TI’s precision analog applications experts. TI reference designs offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI reference designs are available online at https://www.ti.com/reference-designs.

9.1.1.4 Filter Design Tool

The filter design tool is a simple, powerful, and easy-to-use active filter design program. The filter design tool allows the user to create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web-based tool from the Design tools and simulation web page, the filter design tool allows the user to design, optimize, and simulate complete multistage active filter solutions within minutes. www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: RES11A

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note
Texas Instruments, THP210 Ultra-Low Offset, High-Voltage, Low-Noise, Precision, Fully-Differential Amplifier data sheet
Texas Instruments, OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current, Rail-to-Rail I/O, e-trim™ Operational Amplifiers data sheet

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. TINA™ is a trademark of DesignSoft, Inc. PSpice® is a registered trademark of Cadence Design Systems, Inc. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2023 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. RES11A SLPS785 – DECEMBER 2023 www.ti.com

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11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PRES11A00QDDFRQ1 SOT-23- PRES11A10QDDFRQ1 SOT-23- PRES11A150QDDFRQ1 SOT-23- PRES11A16QDDFRQ1 SOT-23- PRES11A20QDDFRQ1 SOT-23- PRES11A25QDDFRQ1 SOT-23- PRES11A30QDDFRQ1 SOT-23- PRES11A40QDDFRQ1 SOT-23- PRES11A50QDDFRQ1 SOT-23- PRES11A90QDDFRQ1 SOT-23- www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: RES11A

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PRES11A00QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A10QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A15QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A16QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A20QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A25QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A30QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A40QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A50QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 PRES11A90QDDFRQ1 SOT-23-THIN DFF 8 3000 201.0 185.0 35.0 RES11A SLPS785 – DECEMBER 2023 www.ti.com

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11.2 Mechanical Data

www.ti.com PACKAGE OUTLINE C TYP2.95 2.65

1.1 MAX

6X 0.65 8X 0.4 0.2 1.95 TYP0.20 0.08 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A NOTE 3 2.95 2.85 B 1.65 1.55 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4222047/B 11/2015 SYMM SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED RES11A SLPS785 – DECEMBER 2023 www.ti.com

Product Folder Links: RES11A

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R ) TYP0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have diﬀerent recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X www.ti.com RES11A SLPS785 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: RES11A

www.ti.com 24-Dec-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples RES11A40DDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 R1140 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Dec-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant RES11A40DDFR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Dec-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) RES11A40DDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

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Product Information

RES11A15 specifications and overview.

Summary

RES11A Matched, Thin-Film Resistor Dividers With 1-kΩ Inputs DECEMBER 2023

Description

RES11A Matched, Thin-Film Resistor Dividers With 1-kΩ Inputs DECEMBER 2023

Source title RES11A15 Datasheet(PDF) - Texas Instruments

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