REG101 TI | Alldatasheet

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Technical content

100mA Low-Dropout Regulator

FEATURES

G NEW DMOS TOPOLOGY: Ultra Low Dropout Voltage: 60mV typ at 100mA Output capacitor NOT required for stability G FAST TRANSIENT RESPONSE G VERY LOW NOISE: 23µVrms G HIGH ACCURACY: ±1.5% max G HIGH EFFICIENCY: IGND = 500µA at IOUT = 100mA Not Enabled: IGND = 10nA ADJUSTABLE OUTPUT VERSIONS G OTHER OUTPUT VOLTAGES AVAILABLE UPON REQUEST G FOLDBACK CURRENT LIMIT G THERMAL PROTECTION G SMALL SURFACE-MOUNT PACKAGES: SOT23-5 and SO-8

APPLICATIONS

G PORTABLE COMMUNICATION DEVICES G BATTERY-POWERED EQUIPMENT G PERSONAL DIGITAL ASSISTANTS G MODEMS G BAR-CODE SCANNERS G BACKUP POWER SUPPLIES

DESCRIPTION

The REG101 is a family of low-noise, low-dropout linear regulators with low ground pin current. Its new DMOS topology provides significant improvement over previous designs, including low dropout voltage (only 60mV typ at full load), and better transient performance. In addition, no output capacitor is required for stability, unlike conventional low-dropout regulators that are difficult to compensate and require expensive low ESR capacitors greater than 1µF. Typical ground pin current is only 500µA (at I OUT = 100mA) and drops to 10nA when not in enabled mode. Unlike regula- tors with PNP pass devices, quiescent current remains rela- tively constant over load variation and under dropout condi- tions. The REG101 has very low output noise (typically 23µVrms for V OUT = 3.3V with CNR = 0.01µF), making it ideal for use in portable communications equipment. Accuracy is main- tained over temperature, line, and load variations. Key parameters are tested over the specified temperature range (–40°C to +85°C). The REG101 is well protected—internal circuitry provides a current limit that protects the load from damage. Thermal protection circuitry keeps the chip from being damaged by excessive temperature. The REG101 is available in the SOT23-5 and the SO-8 packages. REG101 (Fixed Voltage Versions) Enable Gnd 0.1µF C OUT (1)++ VOUTVIN NR NR = Noise Reduction NOTE: (1) Optional. REG101-A Gnd Enable 0.1µF + C OUT (1)+ VOUTVIN R 2 R 1 Adj REG101 REG101 SBVS026D – JULY 2001 – REVISED SEPTEMBER 2005 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000-2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

ABSOLUTE MAXIMUM RATINGS (1) Operating Temperature Range (T NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN CONFIGURATIONS Top View VOUT (2) VOUT (2) NR/Adjust(1) GND VIN (3) VIN (3) NC Enable SO-8 (U Package) VIN GND Enable VOUT NR/Adjust(1) SOT23-5 (N Package) NOTE: (1) For REG101A-A: voltage setting resistor pin. All other models: noise reduction capacitor pin. (2) Both pin 1 and pin 2 must be connected. (3) Both pin 7 and pin 8 must be connected. PACKAGE/ORDERING INFORMATION (1) PRODUCT VOUT (2) REG101 xx-yyyy/zzz XX is package designator. YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable). ZZZ is package quantity. (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability.

ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range, TJ = –40°C to +85°C. REG101NA REG101UA PARAMETER CONDITION MIN TYP MAX UNITS OUTPUT VOLTAGE Output Voltage V OUT REG101-2.5 2.5 V REG101-2.8 2.8 V REG101-2.85 2.85 V REG101-3.0 3.0 V REG101-3.3 3.3 V REG101-5 5V REG101-A 2.5 5.5 V Reference Voltage V REF 1.267 V Adjust Pin Current I ADJ 0.2 1 µA Accuracy ±0.5 ±1.5 % Over Temperature ±2.2 % vs Temperature dV OUT /dT 50 ppm/°C Includes Line and Load IOUT = 2mA to 100mA, VIN = (VOUT + 0.4V) to 10V ±0.8 ±2.0 % Over Temperature V IN = (VOUT + 0.6V) to 10V ±2.7 % DC DROPOUT VOLTAGE (2) VDROP IOUT = 2mA 4 10 mV For all models I OUT = 100mA 60 100 mV Over Temperature I OUT = 100mA 130 mV VOLTAGE NOISE Vn f = 10Hz to 100kHz Without CNR C NR = 0, COUT = 0 23 µVrms/V • VOUT µVrms With CNR (all fixed voltage models) C NR = 0.01µF, COUT = 10µF7 µVrms/V • VOUT µVrms OUTPUT CURRENT Current Limit(3) ICL 130 170 220 mA Over Temperature 110 240 mA Short-Circuit Current I SC 60 mA RIPPLE REJECTION f = 120Hz I OUT = 100mA 65 dB ENABLE CONTROL VENABLE High (output enabled) V ENABLE 1.8 V IN V VENABLE Low (output disabled) –0.2 0.5 V IENABLE High (output enabled) I ENABLE VENABLE = 1.8V to VIN, VIN = 1.8V to 6.5(4) 1 100 nA IENABLE Low (output disabled) V ENABLE = 0V to 0.5V 2 100 nA Output Disable Time C OUT = 1.0µF, RLOAD = 33Ω 200 µs Output Enable Time C OUT = 1.0µF, RLOAD = 33Ω 1.5 ms THERMAL SHUTDOWN Junction Temperature Shutdown 160 °C Reset from Shutdown 140 °C GROUND PIN CURRENT Ground Pin Current I GND IOUT = 2mA 400 500 µA IOUT = 100mA 500 650 µA Enable Pin Low V ENABLE ≤ 0.5V 0.01 0.2 µA INPUT VOLTAGE VIN Operating Input Voltage Range(5) 1.8 10 V Specified Input Voltage Range V IN > 1.8V V OUT + 0.4 10 V Over Temperature V IN > 1.8V V OUT + 0.6 10 V TEMPERATURE RANGE Specified Range T J –40 +85 °C Operating Range T J –55 +125 °C Storage Range T A –65 +150 °C Thermal Resistance SOT23-5 Surface Mount θJA Junction-to-Ambient 200 °C/W SO-8 Surface Mount θJA Junction-to-Ambient 150 °C/W NOTES: (1) The REG101 does not require a minimum output capacitor for stability. However, transient response can be improved with proper capacitor selection. (2) Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN = VOUT + 1V at fixed load. (3) Current limit is the output current that produces a 10% change in output voltage from VIN = VOUT + 1V and IOUT = 2mA. (4) For VENABLE > 6.5V, see typical characteristic “IENABLE vs VENABLE ”. (5) The REG101 no longer regulates when VIN < VOUT + VDROP (MAX) . In drop-out, the impedance from VIN to VOUT is typically less than 1Ω at TJ = +25°C.

For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. 2004 010 30 60 50 70 80 90 100 0.80 0.60 0.40 0.20 0.00 –0.20 –0.40 –0.60 –0.80 Output Voltage Change (%) IOUT (mA) OUTPUT VOLTAGE CHANGE vs I OUT (VIN = VOUT + 1V, Output Voltage % Change Referred to IOUT = 50mA at +25°C) –55°C +125°C +25°C –25–50 0 75 25 50 100 125 0.0% –0.1% –0.2% –0.3% –0.4% Output Voltage Change (%) Temperature (°C) LOAD REGULATION vs TEMPERATURE (VIN = VOUT + 1V) 10mA < IOUT < 100mA 2mA < IOUT < 1000mA –50 –25 0 25 50 75 100 125 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 Output Voltage Change (%) Temperature (°C) LINE REGULATION vs TEMPERATURE IOUT = 100mA (VOUT + 1V) < VIN < 10V (VOUT + 0.4V) < VIN < 10V 0 10 100 100 DC Dropout Voltage (mV) IOUT (mA) DC DROPOUT VOLTAGE vs I OUT 20 30 40 50 60 70 80 90 –55°C +125°C +25°C 01 2 345 8 67 –10 –15 –20 Output Voltage Change (mV) VIN – VOUT (V) LINE REGULATION (Referred to VIN = VOUT + 1V at IOUT = 50mA) IOUT = 2mA IOUT = 50mA IOUT = 100mA –50 125 1007550250–25 100 DC Dropout Voltage (mV) Temperature (°C) DC DROPOUT VOLTAGE vs TEMPERATURE IOUT = 100mA

TYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. –50 25 –25 0 50 75 100 125 0.50 0.40 0.30 0.20 0.10 0.00 –0.10 –0.20 –0.30 –0.40 –0.50 Output Voltage Change (%) Temperature (°C) OUTPUT VOLTAGE vs TEMPERATURE (Output Voltage % Change Referred to IOUT = 50mA at +25°C) IOUT = 2mA IOUT = 100mA IOUT = 50mA –50 25 –25 0 50 75 100 125 100n 10n 100p IGND (A) Temperature (°C) GROUND PIN CURRENT, NOT ENABLED vs TEMPERATURE VENABLE = 0.5V VIN = VOUT + 1V –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 Percentage of Units (%) Error (%) OUTPUT VOLTAGE ACCURACY HISTOGRAM 100 Percentage of Units (%) VOUT Drift (ppm/°C) OUTPUT VOLTAGE DRIFT HISTOGRAM 02 0 3 010 50 40 70 60 90 80 100 600 500 400 300 200 100 IGND (µA) IOUT (mA) GROUND PIN CURRENT vs I OUT VOUT = 2.5V VIN = VOUT + 1V VOUT = 3.3V VOUT = 5.0V –50 –25 0 25 50 75 125 100 600 575 550 525 500 475 450 425 400 IGND (µA) Temperature (°C) GROUND PIN CURRENT vs TEMPERATURE IOUT = 100mAVOUT = 5V VOUT = 3.3V VOUT = 2.5V VIN = VOUT + 1V

TTYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. 10 100 1k 10k 100k 0.1 0.01 eN (µV/√Hz) Frequency (Hz) NOISE SPECTRAL DENSITY IOUT = 100mA C NR = 0µF C OUT = 1µF C OUT = 0µF C OUT = 10µF 10 100 1k 10k 100k 0.1 0.01 eN (µV/√Hz) Frequency (Hz) NOISE SPECTRAL DENSITY IOUT = 100mA C NR = 0.01µF C OUT = 1µF C OUT = 0µF C OUT = 10µF Ripple Rejection (dB) VIN - VOUT (V) RIPPLE REJECTION vs (VIN – VOUT ) REG101-3.3 Frequency = 100kHz C OUT = 10µF IOUT = 100mA 0.1 11 0 Noise Voltage (µVrms) C OUT (µF) RMS NOISE VOLTAGE vs C OUT REG101-5.0 REG101-3.3 REG101-2.5 C NR = 0.01µF 10Hz < BW < 100kHz 11 0 1 k 100 10k 110 100 Noise Voltage (µVrms) C NR (pF) RMS NOISE VOLTAGE vs C NR C NR = 0µF 10Hz < BW < 100kHz REG101-5.0 REG101-2.5 REG101-3.3 10 100 1k 10k 100k 10M 1M Ripple Rejection (dB) Frequency (Hz) RIPPLE REJECTION vs FREQUENCY IOUT = 2mA IOUT = 100mA IOUT = 2mA C OUT = 10µF IOUT = 100mA C OUT = 10µF C OUT = 0µF

TYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. –50 –25 ISC 125 180 160 140 120 100 IOUT (mA) Temperature (°C) CURRENT LIMIT vs TEMPERATURE ICL 0 25 50 75 100 VIN = VOUT + 1V LINE TRANSIENT RESPONSE 50µs/div 5.3V 50mV/div50mV/div VIN VOUT VOUT 4.3V REG101-3.3 IOUT = 100mA C OUT = 0 C OUT = 10µF LOAD TRANSIENT RESPONSE 10µs/div REG101-3.3 VIN = 4.3V 100mA 200mV/div200mV/div IOUT VOUT VOUT 10mA C OUT = 0µF C OUT = 10µF TURN-OFF 200µs/div 1V/div1V/div VENABLE VOUT REG101-3.3 C NR = 0.01µF C OUT = 0µF R LOAD = 1600Ω C OUT = 10µF R LOAD = 33Ω C OUT = 1.0µF R LOAD = 33Ω TURN-ON 250µs/div 1V/div1V/div VENABLE VOUT REG101-3.3 VIN = VOUT + 1V C NR = 0.01µF C OUT = 0µF R LOAD = 33Ω C OUT = 10µF R LOAD = 33Ω C OUT = 0µF R LOAD = 1600Ω 04 0 20 140 160 80 100 12060 180 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Output Voltage (V) Output Current (mA) FOLDBACK CURRENT LIMIT ICL ISC REG101-3.3

TYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. 6789 1 0 10µ 100n 10n IENABLE (A) VENABLE (V) IENABLE vs VENABLE T = +25°C T = –55°C T = +125°C POWER UP/POWER DOWN 1s/div 500mV/div VOUT = 3.0V R LOAD = 30Ω VOUTVIN 10 100 1k 10k 100k Vn (µVrms) C ADJ (pF) RMS NOISE VOLTAGE vs C ADJ REG101 –A VOUT = 3.3V C OUT = 0.1µF 10Hz < frequency < 100kHz –50 –25 0 25 50 75 100 125 0.350 0.300 0.250 0.200 0.150 0.100 0.050 0.000 IADJ (µA) Temperature (°C) ADJUST PIN CURRENT vs TEMPERATURE 200mV/div 200mV/div 10mA VOUT C OUT = 0 REG101 –A VIN = 4.3V VOUT = 3.3V C OUT = 10µF VOUT IOUT 100mA LOAD TRANSIENT-ADJUSTABLE VERSION 50mV/div 50mV/div 4.3V VOUT C OUT = 0 REG101 –A IOUT = 100mA C FB = 0.01µF VOUT = 3.3V C OUT = 10µF VOUT VIN 5.3V LINE TRANSIENT-ADJUSTABLE VERSION

FIGURE 6. Transient and DC Dropout. drop-out under DC load conditions. an undesirable effect on the load.

FIGURE 7. Maximum Power Dissipation versus Ambient Temperature for the Various Packages. configurations are shown in Figure 7.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REG101NA-2.5/250 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1G REG101NA-2.5/250.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1G REG101NA-2.5/3K Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1G REG101NA-2.5/3K.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1G REG101NA-2.8/250 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1E REG101NA-2.8/250.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1E REG101NA-2.85/250 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1N REG101NA-2.85/250.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1N REG101NA-2.85/3K Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1N REG101NA-2.85/3K.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1N REG101NA-3.3/250 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C REG101NA-3.3/250.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C REG101NA-3.3/250G4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C REG101NA-3.3/3K Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C REG101NA-3.3/3K.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C REG101NA-3.3/3KG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C REG101NA-3/250 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 R01D REG101NA-3/250.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 R01D REG101NA-3/3K Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 R01D REG101NA-3/3K.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 R01D REG101NA-5/250 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1B REG101NA-5/250.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1B REG101NA-5/3K Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1B REG101NA-5/3K.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1B REG101NA-A/250 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A REG101NA-A/250.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A REG101NA-A/250.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A REG101NA-A/3K Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A REG101NA-A/3K.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A Addendum-Page 1

www.ti.com 23-May-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REG101NA-A/3K.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A REG101NA-A/3KG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A REG101UA-2.5 Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U25 REG101UA-2.5.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U25 REG101UA-3 Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U30 REG101UA-3.3 Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U33 REG101UA-3.3.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U33 REG101UA-3.3/2K5 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U33 REG101UA-3.3/2K5.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U33 REG101UA-3.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U30 REG101UA-5 Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U50 REG101UA-5.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U50 REG101UA-5/2K5 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U50 REG101UA-5/2K5.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101U50 REG101UA-A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101UA REG101UA-A.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101UA REG101UA-A.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 REG 101UA (1) Status: For more details on status, see our product life cycle. Addendum-Page 2

www.ti.com 23-May-2025 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REG101NA-2.5/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-2.5/3K SOT-23 DBV 5 3000 200.0 183.0 25.0 REG101NA-2.8/250 SOT-23 DBV 5 250 200.0 183.0 25.0 REG101NA-2.85/250 SOT-23 DBV 5 250 200.0 183.0 25.0 REG101NA-2.85/3K SOT-23 DBV 5 3000 200.0 183.0 25.0 REG101NA-3.3/250 SOT-23 DBV 5 250 200.0 183.0 25.0 REG101NA-3.3/3K SOT-23 DBV 5 3000 200.0 183.0 25.0 REG101NA-3/250 SOT-23 DBV 5 250 200.0 183.0 25.0 REG101NA-3/3K SOT-23 DBV 5 3000 200.0 183.0 25.0 REG101NA-5/250 SOT-23 DBV 5 250 200.0 183.0 25.0 REG101NA-5/3K SOT-23 DBV 5 3000 200.0 183.0 25.0 REG101NA-A/250 SOT-23 DBV 5 250 200.0 183.0 25.0 REG101NA-A/3K SOT-23 DBV 5 3000 200.0 183.0 25.0 REG101UA-3.3/2K5 SOIC D 8 2500 356.0 356.0 35.0 REG101UA-5/2K5 SOIC D 8 2500 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) REG101UA-2.5 D SOIC 8 75 506.6 8 3940 4.32 REG101UA-2.5.B D SOIC 8 75 506.6 8 3940 4.32 REG101UA-3 D SOIC 8 75 506.6 8 3940 4.32 REG101UA-3.3 D SOIC 8 75 506.6 8 3940 4.32 REG101UA-3.3.B D SOIC 8 75 506.6 8 3940 4.32 REG101UA-3.B D SOIC 8 75 506.6 8 3940 4.32 REG101UA-5 D SOIC 8 75 506.6 8 3940 4.32 REG101UA-5.B D SOIC 8 75 506.6 8 3940 4.32 REG101UA-A D SOIC 8 75 506.6 8 3940 4.32 REG101UA-A.A D SOIC 8 75 506.6 8 3940 4.32 REG101UA-A.B D SOIC 8 75 506.6 8 3940 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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