REF70_V04 TI | Alldatasheet
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Technical content
REF70 2 ppm/°C Maximum Drift, 0.23 ppmp-p 1/f Noise, Precision Voltage Reference
1 Features
- Low noise enables precision measurements: – 1/f Noise (0.1 Hz to 10 Hz): 0.23 ppmp-p – 10 Hz to 1 kHz: 0.35 ppmrms
- Low temperature drift coefficient: – 2 ppm/°C maximum (-40°C to 125°C)
- High accuracy: ±0.025% maximum
- Humidity resistant hermetic ceramic package (LCCC)
- Low long-term stability (1k hr): 28 ppm
- Low dropout: 400 mV
- Designed for a wide range of applications: – Wide input voltage up to 18 V – Output current: ±10 mA – Voltage options: 1.25 V, 2.5 V, 3 V, 3.3 V, 4.096 V, 5 V
- Ultra-flexible solution: – Stable with 1-μF to 100-μF output low-ESR capacitor – High PSRR: 107 dB at 1 kHz – Operating temperature range: −40°C to +125°C
2 Applications
- Semiconductor test equipment
- Precision data acquisition systems
- Precision weight scales
- Ultrasound scanner
- X-ray systems
- Industrial instrumentation
- PLC analog I/O modules
- Field transmitters
- Power monitoring
3 Description
The REF70 is a family of high precision series voltage references that offers the industry’s lowest noise (0.23 ppm p-p), very low temperature drift coefficient (2 ppm/°C), and high accuracy (±0.025%). The REF70 offers a high PSRR, low drop-out voltage and excellent load and line regulation to help meet strict transient requirements. This combination of precision and features is designed for applications such as test and measurement that demand a precise reference to be paired with precision, high-resolution data converters such as ADS8900B, ADS127L01 and DAC11001A, to achieve optimal performance in the signal chain. The REF70 is also designed for noise- sensitive medical applications such as ultrasound and X-ray to help enable low-noise measurements from the analog front end. The REF70 family is available in VSSOP and LCCC package options. The LCCC (FKH) package is a hermetically sealed ceramic package that allows for low, long-term drift for applications that require a stable reference over a long time period without calibration. The REF70 is specified for the wide temperature range of −40°C to +125°C. The wide temperature range enables operation across various industrial applications. Device Information PART NAME PACKAGE (1) BODY SIZE (NOM) REF70 LCCC (8) 5.00 mm × 5.00 mm VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Noise (ppmp-p) Population (%) 0.1 0.2 0.3 0.4 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.1-Hz to 10-Hz Voltage Noise Distribution Temperature (°C) Output Voltage (V) -50 -25 0 25 50 75 100 125 2.499 2.49925 2.4995 2.49975 2.5 2.50025 2.5005 2.50075
2.501 Output Voltage Vs Free-Air-Temperature
SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
13.2 Receiving Notification of Documentation Updates..32
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2021) to Revision D (November 2021) Page Changes from Revision B (April 2021) to Revision C (September 2021) Page
- In the Device Comparison Table, added the 1.25V variant and added foot notes to indicate which devices are
- Under Temperature Drift section of the Parameter Measurement Information, corrected the figure from Long Changes from Revision A (December 2020) to Revision B (April 2021) Page
- Changed REF7025 to more general REF70 series in heading and device information. Added ADC companion REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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Changes from Revision * (October 2020) to Revision A (December 2020) Page www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: REF70
5 Device Comparison Table
PRODUCT (2) VOUT REF7012 (1) 1.25 V REF7025 (1) 2.5 V REF7030 3.0 V REF7033 3.3 V REF7040 4.096 V REF7050 5.0 V (1) Released device - REF7012, REF7025. (2) Preproduction device - REF7030, REF7033, REF7040, REF7050. REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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6 Pin Configuration and Functions
Figure 6-1. FKH Package 8-Pin LCCC Top View VIN EN GND OUTF OUTSGND GNDGND Figure 6-2. DGK Package 8-Pin VSSOP Top View Table 6-1. Pin Functions PIN TYPE DESCRIPTION NAME FKH DGK EN 1 1 Input Device enable control. Low level input disables the reference output and device enters shutdown mode. Device can be enabled by driving voltage > 1.6V. If the pin is left floating, the internal pull up will enable the device. VIN 2 2 Power Input supply voltage connection. Connect a minimum 0.1-μF decoupling capacitor to ground for the best performance. GND 3 3 Ground Ground connection. GND 4 4 Ground Ground connection. GND 5 5 Ground Ground connection OUTS 6 6 Input Reference voltage output sense connection. OUTF 7 7 Output Reference voltage output force connection. Connect a output capacitor between 1-μF to 100-μF for the best performance. GND 8 8 Ground Ground connection. www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: REF70
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN -0.3 20 V Enable voltage EN -0.3 VIN + 0.3 V Output voltage VOUT -0.3 6 V Output short circuit current ISC 25 mA Operating temperature range TA -55 150 °C Storage temperature range Tstg -65 170 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified in the Electrical Characteristics Table is not implied.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ± 1000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ± 500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage VOUT + VDO (1) 18 V EN Enable voltage 0 VIN V IL Output current –10 10 mA TA Operating temperature –40 25 125 °C (1) VDO = Dropout voltage. For VOUT < 2.5 V minimum VIN = 2.75 V
7.4 Thermal Information
THERMAL METRIC(1) REF70xx UNITFKH (CERAMIC) DGK (MSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 95.8 201.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 59.0 85.7 °C/W RθJB Junction-to-board thermal resistance 58.3 122.9 °C/W ΨJT Junction-to-top characterization parameter 48.2 21.2 °C/W ΨJB Junction-to-board characterization parameter 58.1 121.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 28.5 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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7.5 REF7012 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = 3 V, OUTS connected to OUTF, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25°C –0.025 0.025 % Output voltage temperature coefficient –40°C ≤ TA ≤ 125°C 2 ppm/℃ LINE AND LOAD REGULATION ΔVO / ΔVIN Line regulation
2.7 V ≤ VIN ≤ 18 V 4
2.7 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C 30
ΔVO / ΔIL Load regulation IL = 0 mA to 10mA, VIN = 3 V 5 ppm/mA IL = 0 mA to 10mA, VIN = 3 V, –40°C ≤ TA ≤ 125°C 15 IL = 0 mA to –10mA, VIN = 3 V 15 IL = 0 mA to –10mA, VIN = 3 V, –40°C ≤ TA ≤ 125°C 30 NOISE enp-p Low frequency noise ƒ = 0.1 Hz to 10 Hz 0.25 ppmp-p en Output voltage noise ƒ = 10 Hz to 1 kHz 0.35 ppmrms HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 250h at 35°C –FKH package 15 ppm 0 to 1000h at 35°C – FKH package 35 Output voltage hysteresis 25°C, –40°C, 125°C, 25°C – FKH package 18 ppm25°C, –40°C, 85°C, 25°C – FKH package 11 25°C, 0°C, 70°C, 25°C – FKH package 11 TURN ON TIME tON Turn-on time 0.1% settling, COUT = 1µF 0.5 ms CAPACITIVE LOAD CIN Stable input capacitor range –40℃ ≤ TA ≤ 125℃ 0.1 µF COUT Stable output capacitor range (1) –40℃ ≤ TA ≤ 125℃ 1 100 µF POWER SUPPLY VIN Input voltage 2.75 18 V IQ Quiescent current TA = 25°C Active mode 4 6.5 mA –40°C ≤ TA ≤ 125°C 7.5 mA TA = 25°C Shutdown mode 5 10 uA –40°C ≤ TA ≤ 125°C 12 uA VEN Enable pin voltage Active mode (EN=1) 1.6 V Shutdown mode (EN=0) 0.5 V IEN Enable pin current VIN = VEN = 18V 3.2 4 uA VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C 5 uA ISC Short circuit current VOUT = 0V 30 mA (1) ESR for the capacitor can range from 10mΩ to 400mΩ www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: REF70
7.6 REF7025 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25°C –0.025 0.025 % Output voltage temperature coefficient –40°C ≤ TA ≤ 125°C 2 ppm/℃ LINE AND LOAD REGULATION ΔVO / ΔVIN Line regulation VOUT + VDO ≤ VIN ≤ 18 V 4 ppm/V VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C 30 ΔVO / ΔIL Load regulation IL = 0 mA to 10mA, VIN = VOUT + VDO 5 ppm/mA IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤ TA ≤ 125°C 10 IL = 0 mA to –10mA, VIN = VOUT + VDO 5 IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤ TA ≤ 125°C 15 NOISE enp-p Low frequency noise ƒ = 0.1 Hz to 10 Hz 0.23 ppmp-p en Output voltage noise ƒ = 10 Hz to 1 kHz 0.35 ppmrms HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 250h at 35°C - FKH package 10 ppm 0 to 1000h at 35°C - FKH package 28 Output voltage hysteresis 25°C, –40°C, 125°C, 25°C – FKH package 180 ppm25°C, –40°C, 85°C, 25°C – FKH package 100 25°C, 0°C, 70°C, 25°C – FKH package 40 TURN ON TIME tON Turn-on time 0.1% settling, COUT = 1µF 0.5 ms CAPACITIVE LOAD CIN Stable input capacitor range –40℃ ≤ TA ≤ 125℃ 0.1 µF COUT Stable output capacitor range (1) –40℃ ≤ TA ≤ 125℃ 1 100 µF POWER SUPPLY VIN Input voltage VOUT + VDO 18 V IQ Quiescent current TA = 25°C Active mode 4 6 mA –40°C ≤ TA ≤ 125°C 6.5 mA TA = 25°C Shutdown mode 5 10 uA –40°C ≤ TA ≤ 125°C 12 uA VEN Enable pin voltage Active mode (EN=1) 1.6 V Shutdown mode (EN=0) 0.5 V IEN Enable pin current VIN = VEN = 18V 3.2 4 uA VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C 5 uA VDO Dropout voltage IL = 5mA, –40°C ≤ TA ≤ 125°C 250 mV IL = 10mA, –40°C ≤ TA ≤ 125°C 400 mV ISC Short circuit current VOUT = 0V 25 mA (1) ESR for the capacitor can range from 10mΩ to 400mΩ REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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7.7 REF7030 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25°C –0.025 0.025 % Output voltage temperature coefficient –40°C ≤ TA ≤ 125°C 2 ppm/℃ LINE AND LOAD REGULATION ΔVO / ΔVIN Line regulation
3.2 V ≤ VIN ≤ 18 V 4
3.2 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C 30
ΔVO / ΔIL Load regulation IL = 0 mA to 10mA, VIN = 3.5 V 5 ppm/mA IL = 0 mA to 10mA, VIN = 3.5 V, –40°C ≤ TA ≤ 125°C 10 IL = 0 mA to –10mA, VIN = 3.5 V 5 IL = 0 mA to –10mA, VIN = 3.5 V, –40°C ≤ TA ≤ 125°C 15 NOISE enp-p Low frequency noise ƒ = 0.1 Hz to 10 Hz 0.23 ppmp-p en Output voltage noise ƒ = 10 Hz to 1 kHz 0.35 ppmrms HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 250h at 35°C - FKH package 10 ppm 0 to 1000h at 35°C - FKH package 28 Output voltage hysteresis 25°C, –40°C, 125°C, 25°C – FKH package 180 ppm25°C, –40°C, 85°C, 25°C – FKH package 100 25°C, 0°C, 70°C, 25°C – FKH package 40 TURN ON TIME tON Turn-on time 0.1% settling, COUT = 1µF 0.5 ms CAPACITIVE LOAD CIN Stable input capacitor range –40℃ ≤ TA ≤ 125℃ 0.1 µF COUT Stable output capacitor range (1) –40℃ ≤ TA ≤ 125℃ 1 100 µF POWER SUPPLY VIN Input voltage VOUT + VDO 18 V IQ Quiescent current TA = 25°C Active mode 4 6 mA –40°C ≤ TA ≤ 125°C 6.5 mA TA = 25°C Shutdown mode 5 10 uA –40°C ≤ TA ≤ 125°C 12 uA VEN Enable pin voltage Active mode (EN=1) 1.6 V Shutdown mode (EN=0) 0.5 V IEN Enable pin current VIN = VEN = 18V 3.2 4 uA VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C 5 uA VDO Dropout voltage IL = 5mA, –40°C ≤ TA ≤ 125°C 250 mV IL = 10mA, –40°C ≤ TA ≤ 125°C 400 mV ISC Short circuit current VOUT = 0V 25 mA (1) ESR for the capacitor can range from 10mΩ to 400mΩ www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: REF70
7.8 REF7033 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25°C –0.025 0.025 % Output voltage temperature coefficient –40°C ≤ TA ≤ 125°C 2 ppm/℃ LINE AND LOAD REGULATION ΔVO / ΔVIN Line regulation
3.5 V ≤ VIN ≤ 18 V 4
3.5 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C 30
ΔVO / ΔIL Load regulation IL = 0 mA to 10mA, VIN = 3.8 V 5 ppm/mA IL = 0 mA to 10mA, VIN = 3.8 V, –40°C ≤ TA ≤ 125°C 10 IL = 0 mA to –10mA, VIN = 3.8 V 5 IL = 0 mA to –10mA, VIN = 3.8 V, –40°C ≤ TA ≤ 125°C 15 NOISE enp-p Low frequency noise ƒ = 0.1 Hz to 10 Hz 0.23 ppmp-p en Output voltage noise ƒ = 10 Hz to 1 kHz 0.35 ppmrms HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 250h at 35°C - FKH package 10 ppm 0 to 1000h at 35°C - FKH package 28 Output voltage hysteresis 25°C, –40°C, 125°C, 25°C – FKH package 180 ppm25°C, –40°C, 85°C, 25°C – FKH package 100 25°C, 0°C, 70°C, 25°C – FKH package 40 TURN ON TIME tON Turn-on time 0.1% settling, COUT = 1µF 0.5 ms CAPACITIVE LOAD CIN Stable input capacitor range –40℃ ≤ TA ≤ 125℃ 0.1 µF COUT Stable output capacitor range (1) –40℃ ≤ TA ≤ 125℃ 1 100 µF POWER SUPPLY VIN Input voltage VOUT + VDO 18 V IQ Quiescent current TA = 25°C Active mode 4 6 mA –40°C ≤ TA ≤ 125°C 6.5 mA TA = 25°C Shutdown mode 5 10 uA –40°C ≤ TA ≤ 125°C 12 uA VEN Enable pin voltage Active mode (EN=1) 1.6 V Shutdown mode (EN=0) 0.5 V IEN Enable pin current VIN = VEN = 18V 3.2 4 uA VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C 5 uA VDO Dropout voltage IL = 5mA, –40°C ≤ TA ≤ 125°C 250 mV IL = 10mA, –40°C ≤ TA ≤ 125°C 400 mV ISC Short circuit current VOUT = 0V 25 mA (1) ESR for the capacitor can range from 10mΩ to 400mΩ REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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7.9 REF7040 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25°C –0.025 0.025 % Output voltage temperature coefficient –40°C ≤ TA ≤ 125°C 2 ppm/℃ LINE AND LOAD REGULATION ΔVO / ΔVIN Line regulation VOUT + VDO ≤ VIN ≤ 18 V 4 ppm/V VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C 30 ΔVO / ΔIL Load regulation IL = 0 mA to 10mA, VIN = VOUT + VDO 5 ppm/mA IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤ TA ≤ 125°C 10 IL = 0 mA to –10mA, VIN = VOUT + VDO 5 IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤ TA ≤ 125°C 15 NOISE enp-p Low frequency noise ƒ = 0.1 Hz to 10 Hz 0.23 ppmp-p en Output voltage noise ƒ = 10 Hz to 1 kHz 0.35 ppmrms HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 250h at 35°C - FKH package 10 ppm 0 to 1000h at 35°C - FKH package 28 Output voltage hysteresis 25°C, –40°C, 125°C, 25°C – FKH package 180 ppm25°C, –40°C, 85°C, 25°C – FKH package 100 25°C, 0°C, 70°C, 25°C – FKH package 40 TURN ON TIME tON Turn-on time 0.1% settling, COUT = 1µF 0.5 ms CAPACITIVE LOAD CIN Stable input capacitor range –40℃ ≤ TA ≤ 125℃ 0.1 µF COUT Stable output capacitor range (1) –40℃ ≤ TA ≤ 125℃ 1 100 µF POWER SUPPLY VIN Input voltage VOUT + VDO 18 V IQ Quiescent current TA = 25°C Active mode 4 6 mA –40°C ≤ TA ≤ 125°C 6.5 mA TA = 25°C Shutdown mode 5 10 uA –40°C ≤ TA ≤ 125°C 12 uA VEN Enable pin voltage Active mode (EN=1) 1.6 V Shutdown mode (EN=0) 0.5 V IEN Enable pin current VIN = VEN = 18V 3.2 4 uA VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C 5 uA VDO Dropout voltage IL = 5mA, –40°C ≤ TA ≤ 125°C 250 mV IL = 10mA, –40°C ≤ TA ≤ 125°C 400 mV ISC Short circuit current VOUT = 0V 25 mA (1) ESR for the capacitor can range from 10mΩ to 400mΩ www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: REF70
7.10 REF7050 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy TA = 25°C –0.025 0.025 % Output voltage temperature coefficient –40°C ≤ TA ≤ 125°C 2 ppm/℃ LINE AND LOAD REGULATION ΔVO / ΔVIN Line regulation VOUT + VDO ≤ VIN ≤ 18 V 4 ppm/V VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C 30 ΔVO / ΔIL Load regulation IL = 0 mA to 10mA, VIN = VOUT + VDO 5 ppm/mA IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤ TA ≤ 125°C 10 IL = 0 mA to –10mA, VIN = VOUT + VDO 5 IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤ TA ≤ 125°C 15 NOISE enp-p Low frequency noise ƒ = 0.1 Hz to 10 Hz 0.23 ppmp-p en Output voltage noise ƒ = 10 Hz to 1 kHz 0.35 ppmrms HYSTERESIS AND LONG-TERM STABILITY Long-term stability 0 to 250h at 35°C - FKH package 10 ppm 0 to 1000h at 35°C - FKH package 28 Output voltage hysteresis 25°C, –40°C, 125°C, 25°C – FKH package 180 ppm25°C, –40°C, 85°C, 25°C – FKH package 100 25°C, 0°C, 70°C, 25°C – FKH package 40 TURN ON TIME tON Turn-on time 0.1% settling, COUT = 1µF 0.5 ms CAPACITIVE LOAD CIN Stable input capacitor range –40℃ ≤ TA ≤ 125℃ 0.1 µF COUT Stable output capacitor range (1) –40℃ ≤ TA ≤ 125℃ 1 100 µF POWER SUPPLY VIN Input voltage VOUT + VDO 18 V IQ Quiescent current TA = 25°C Active mode 4 6 mA –40°C ≤ TA ≤ 125°C 6.5 mA TA = 25°C Shutdown mode 5 10 uA –40°C ≤ TA ≤ 125°C 12 uA VEN Enable pin voltage Active mode (EN=1) 1.6 V Shutdown mode (EN=0) 0.5 V IEN Enable pin current VIN = VEN = 18V 3.2 4 uA VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C 5 uA VDO Dropout voltage IL = 5mA, –40°C ≤ TA ≤ 125°C 250 mV IL = 10mA, –40°C ≤ TA ≤ 125°C 400 mV ISC Short circuit current VOUT = 0V 25 mA (1) ESR for the capacitor can range from 10mΩ to 400mΩ REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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7.11 Typical Characteristics
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted) Temperature (°C) Output Voltage (V) -50 -25 0 25 50 75 100 125 2.499 2.49925 2.4995 2.49975 2.5 2.50025 2.5005 2.50075 2.501 Figure 7-1. Output Voltage Vs Free-Air Temperature Temperature Drift -40°C to 125°C (ppm/°C) Population (%) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 10% 20% 30% 40% 50% Figure 7-2. Temperature Drift Distribution Output Initial Accuracy (%) Population (%) -0.02 -0.016 -0.012 -0.008 -0.004 0.004 0.008 0.012 0.016 0.02 10% 20% 30% 40% 50% Figure 7-3. Accuracy Distribution Temperature (qC) Line Regulation (ppm/V) -50 -25 0 25 50 75 100 125 Figure 7-4. Line Regulation vs Temperature Temperature (°C) Load Regulation Sourcing (ppm/mA) -50 -25 0 25 50 75 100 125 Figure 7-5. Load Regulation (Sourcing) vs Temperature Temperature (°C) Load Regulation Sinking (ppm/mA) -50 -25 0 25 50 75 100 125 16 Figure 7-6. Load Regulation (Sinking) vs Temperature www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: REF70
7.11 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted) 100µs/div
5 V/div
Figure 7-7. Line Regulation Response 200µs/div 10 mA/div 10 mV/div 10mA -10mA -10mA Figure 7-8. Load Transient Response (CL = 1 μF) 200µs/div 10 mA/div 10 mV/div 10mA -10mA -10mA Figure 7-9. Load Transient Response (CL = 10 μF) Frequency (Hz) Output Impedance :) 10 20 50 100 1000 10000 100000 1000000 0.25 0.5 0.75 1.25 1.5 1.75 1PF 10PF 100PF Figure 7-10. Output Impedance Temperature (°C) Quiescent Current (mA) -50 -25 0 25 50 75 100 125 Figure 7-11. Quiescent Current vs Temperature Temperature (°C) Shutdown Current (µA) -50 -25 0 25 50 75 100 125 0.4 0.8 1.2 1.6 2.4 Figure 7-12. Shutdown Current vs Temperature REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted) Input Voltage (V) Voltage (V) 0 4 8 12 16 20 0.3 0.6 0.9 1.2 1.5 VEN_HIGH VEN_LOW Figure 7-13. Enable Threshold vs VIN Temperature (°C) Dropout Voltage (mV) -50 -25 0 25 50 75 100 125 100 150 200 250 300 0mA 5mA 10mA Figure 7-14. Dropout Voltage vs Temperature Noise (ppmp-p) Population (%) 0.1 0.2 0.3 0.4 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 Figure 7-15. 0.1-Hz to 10-Hz Voltage Noise Distribution (300 units) Frequency (Hz) Noise (nV/vHz) 100 10 100 1k 10k 100k Figure 7-16. Noise Performance 10 Hz to 100 kHz Frequency (Hz) Power Supply Rejection Ratio (dB) 100 120 10 100 1k 10k 100k 1uF 10uF 100uF Figure 7-17. Power-Supply Rejection Ratio vs Frequency Thermal Hysteresis (ppm) Population (%) 0 10 20 30 40 50 60 70 80 90 100 10% 15% 20% 25% 30% 35% Figure 7-18. REF7025 FKH Thermal Hysteresis Distribution (0°C to 70°C) www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: REF70
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted) Thermal Hysteresis (ppm) Population (%) 0 5 10 20 25 30 Figure 7-19. REF7012 FKH Thermal Hysteresis Distribution (0°C to 70°C) Time (hr) Output Voltage Stability (ppm) 0 400 800 1200 1600 2000 -150 -100 -50 100 150 Figure 7-20. Long-Term Stability (First 2000 Hours) REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF70 have differing coefficients of thermal expansion, resulting in stress on the device die when the part is heated during soldering process. Mechanical and thermal stress on the device die can cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a common cause of this error. In order to illustrate this effect, a total of 32 devices were soldered on two printed circuit boards [16 devices on each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow profile. The reflow profile is as shown in Figure 8-1. The printed circuit board is comprised of FR4 material. The board thickness is 1.65 mm and the area is 114 mm × 152 mm. For recommended reflow profiles using 'Sn-Pb Eutectic Assembly' or 'Pb-Free Assembly' please refer JEDEC J-STD-020 standard. 100 150 200 250 300 0 50 100 150 200 250 300 350 400 Temperature (C) Time (seconds) C01 Figure 8-1. Reflow Profile The reference output voltage is measured before and after the reflow process. Although all tested units exhibit very low shifts, higher shifts are also possible depending on the size, thickness, and material of the printed circuit board. An important note is that the Figure 8-2 display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, the device must be soldered in the last pass to minimize its exposure to thermal stress. Solder Shift (%) Population (%) 20% 40% 60% 80% Figure 8-2. Solder Shift www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: REF70
8.2 Long-Term Stability
One of the key parameters of the REF70 references is long-term stability also known as long-term drift. The long-term stability value was tested in a typical setup that reflects standard PCB board manufacturing practices. The boards are made of standard FR4 material and the board does not have special cuts or grooves around the devices to relieve the mechanical stress of the PCB. The devices and boards in this test do not undergo high temperature burn in post-soldering prior to testing. These conditions reflect a real world use case scenario and common manufacturing techniques. During the long-term stability testing, precautions are taken to ensure that only the long-term stability drift is being measured. The boards are maintained at 35°C in an oil bath. The oil bath ensures that the temperature is constant across the device over time compared to an air oven. The measurements are captured every 30 minutes with a calibrated 8.5 digit multimeter. Typical long-term stability characteristic is expressed as a deviation over time. Figure 8-3 shows the typical drift value for the REF70 FKH V OUT is 28 ppm from 0 to 1000 hours. It is important to understand that long-term stability is not ensured by design and that the value is typical. The REF70 will experience the highest drift in the initial 1000 hr. Subsequent deviation is typically lower than 13 ppm for the next 1000 hr. Time (hr) Output Voltage Stability (ppm) 0 400 800 1200 1600 2000 -150 -100 -50 100 150 Figure 8-3. Long Term Stability LCCC -2000 hours (VOUT)
8.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF70 FKH soldered to a PCB, similar to a real-world application. Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling the device through the specified temperature range, and returning to 25°C. This can be seen in Figure 8-4 to Figure 8-5. Hysteresis can be expressed by Equation 1: 6PRE POST HYST NOM | V V |V 10 ppm V § · u ¨ ¸ © ¹ (1) where
- VHYST = thermal hysteresis (in units of ppm)
- VNOM = the specified output voltage
- VPRE = output voltage measured at 25°C pre-temperature cycling
- VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature range of –40°C to +125°C and returns to 25°C. REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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Thermal Hysteresis (ppm) Population (%) 120 130 140 150 160 170 180 190 200 210 220 230 240 10% 20% 30% 40% 50% Figure 8-4. REF7025 Thermal Hysteresis Distribution (-40°C to 125°C) Thermal Hysteresis (ppm) Population (%) 10% 20% 30% 40% 50% 0 10 20 30 40 Figure 8-5. REF7012 Thermal Hysteresis Distribution (-40°C to 125°C)
8.4 Noise Performance
8.4.1 1/f Noise 1/f noise, also known as flicker noise, is a low frequency noise that affects the device output voltage which can affect precision measurements in ADCs. This noise increases proportionally with output voltage and operating temperature. It is measured by filtering the output from 0.1-Hz to 10-Hz. Since the 1/f noise is an extremely low value, the frequency of interest needs to be amplified and band-pass filtered. This is done by using a high-pass filter to block the DC voltage. The resulting noise is then amplified by a gain of 1000. The bandpass filter is created by a series of high-pass and low-pass filter that adds additional gain to make it more visible on a oscilloscope as shown in Figure 8-6 . 1/f noise must be tested in a Faraday cage enclosure to block environmental noise. REF70xx GND OUTS OUTF VIN EN VIN CL CIN VREFP High-pass Filter FC = 0.07 Hz Low Noise Preamplifier G = 1000 2nd Order Low-pass Filter FC = 10 Hz G = 1 2nd Order Low-pass Filter FC = 10 Hz G = 10 2nd Order High-pass Filter FC = 0.1 Hz G = 10 Scope Copyright © 2017, Texas Instruments Incorporated Figure 8-6. 1/f Noise Test Setup Typical 1/f noise (0.1-Hz to 10-Hz) distribution can be seen in Figure 8-7. www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: REF70
Noise (ppmp-p) Population (%) 0.1 0.2 0.3 0.4 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 Figure 8-7. 0.1-Hz to 10-Hz Voltage Noise Distribution The 1/f noise is in such a low frequency range that it is not practical to filter out which makes it a key parameter for ultra-low noise measurements. Noise sensitive designs must use the lowest 1/f noise for the highest precision measurements. Figure 8-8 shows the effect of 1/f noise over 10s. 200 nV/div Time 1s/div Figure 8-8. 0.1-Hz to 10-Hz Voltage Noise
8.4.2 Broadband Noise
Broadband noise is a noise that appears at higher frequency compared to 1/f noise. The broadband noise is usually flat and uniform over frequency as shown in Figure 8-10. The broadband noise is measured by high-pass filtering the output of the REF70 and measuring the result on a spectrum analyzer as shown in Figure 8-9. The DC component of the REF70 is removed by using a high-pass filter and then amplified. When measuring broadband noise, it is not necessary to have high gain in order to achieve maximum bandwidth. REF70xx GND OUTS OUTF VIN EN VIN CL CIN VREFP Spectrum Analyzer Post Amplifier G = 11 High-pass Filter G = 11 Figure 8-9. Broadband Noise Test Setup For noise sensitive designs, a low-pass filter can be used to reduce broadband noise output noise levels by removing the high frequency components. When designing a low-pass filter special care must be taken to REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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ensure the output impedance of the filter does not degrade ac performance. This can occur in RC low-pass filters where a large series resistance can impact the load transients due to output current fluctuations. Frequency (Hz) Noise (nV/vHz) 100 10 100 1k 10k 100k Figure 8-10. Noise Performance 10 Hz to 100 kHz
8.5 Temperature Drift
The REF70 is designed and tested for a minimal output voltage temperature drift, which is defined as the change in output voltage over temperature. Every unit shipped is tested at multiple temperatures to ensure that the product meets data sheet specifications. The temperature coefficient is calculated using the box method in which a box is formed by the min/max limits for the nominal output voltage over the operating temperature range. REF70 has a low maximum temperature coefficient of 2 ppm/°C from –40°C to +125°C. This method corresponds more accurately to the method of test and provides a closer estimate of actual error than the other methods. The box method specifies limits for the temperature error but does not specify the exact shape and slope of the device under test. Due to temperature curvature correction to achieve low-temperature drift, the temperature drift is expected to be non-linear. See SLYT183 for more information on the box method. The box method equation is shown in Equation 2: REF(MAX) REF(MIN) 6 REF(25 C) V V Drift 10V Temperature Rangeq § · u ¨ ¸ ¨ ¸ u© ¹ (2) Temperature (°C) Output Voltage (V) -50 -25 0 25 50 75 100 125 2.499 2.49925 2.4995 2.49975 2.5 2.50025 2.5005 2.50075 2.501 Figure 8-11. Output Voltage Vs Free-Air Temperature
8.6 Power Dissipation
The REF70 voltage references are capable of source and sink up to 10 mA of load current across the rated input voltage range. However, when used in applications subject to high ambient temperatures, the input voltage and load current must be carefully monitored to ensure that the device does not exceeded its maximum power dissipation rating. The maximum power dissipation of the device can be calculated with Equation 3: www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: REF70
(3) where
- PD is the device power dissipation
- TJ is the device junction temperature
- TA is the ambient temperature
- RθJA is the package (junction-to-air) thermal resistance Because of this relationship, acceptable load current in high temperature conditions may be less than the maximum current-sourcing capability of the device. In no case should the device be operated outside of its maximum power rating because doing so can result in premature failure or permanent damage to the device. REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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9 Detailed Description
9.1 Overview
The REF70 is family of ultra low-noise, precision bandgap voltage references that are specifically designed for excellent initial voltage accuracy and drift. The Section 9.2 is a simplified block diagram of the REF70 showing basic band-gap topology.
9.2 Functional Block Diagram
Å OUTS VIN GND VIN REN
9.3 Feature Description
9.3.1 EN Pin
The EN pin of the REF70 has an internal 16 M Ω pull-up resistor (R EN) to VIN. This allows the EN pin of the REF70 to be left floating. When the EN pin of the REF70 is pulled high, the device is in active mode. The device must be in active mode for normal operation. The REF70 can be placed in shutdown mode by pulling the EN pin low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of the device reduces to 12 µA in shutdown mode. The EN pin must not be pulled higher than VIN supply voltage. See the Section 7.6 for logic high and logic low voltage levels.
9.4 Device Functional Modes
9.4.1 Basic Connections
Figure 9-1 shows the typical connections for the REF70. TI recommends a supply bypass capacitor (CIN) ranging from 0.1-μF to 10-μF. A 1-μF to 100-μF output capacitor (CL) must be connected from OUTF to GND. The equivalent series resistance (ESR) value of CL must be 10mΩ to 400mΩ to ensure output stability. REF7025 Copyright © 2020, Texas Instruments Incorporated GND OUTS OUTFVIN EN AVDD VOUT CLCIN Figure 9-1. Basic Connections
9.4.2 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF70 and OPA211 can be used to provide a dual-supply reference from a 5-V supply. Figure 9-2 shows the REF70 used to provide a 2.5-V supply reference voltage and -2.5V negative reference voltage. The low noise performance of the REF70 complements www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: REF70
the low noise of the OPA211 to provide an accurate solution for split-supply applications. Take care to match the temperature coefficients of R1 and R2. REF7025 Copyright © 2020, Texas Instruments Incorporated GND OUTS OUTF VIN EN +5V +5V -5V 10 k 10 k +2.5V -2.5V OPA211 Figure 9-2. The REF70 and OPA211 Create Positive and Negative Reference Voltages REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
10.1 Application Information
This device is a natural fit for many precision applications and it can be connected to system components in various ways and thus there are many situations that this data sheet can not characterize in detail. Basic applications include positive/negative voltage reference and data acquisition systems. The table below shows the typical applications of REF70 and its companion data converters. APPLICATION DATA CONVERTER Precision Data Acquisition ADS124S08, ADS8900B, ADS1278, ADS1262, DAC80501, DAC8562 Industrial Instrumentation ADS127L01, ADS8699, ADS1256, ADS1251, DAC9881, DAC8811, DAC1220, DAC80508 Semiconductor Test ADS8598H, ADS131M08, ADS8686S, ADS8881, DAC11001A, DAC91001A, DAC7744 Power Monitoring, PLC Analog I/O ADS131E04, ADS131A02, Field Transmitters ADS1247, ADS1220
10.2 Typical Applications
10.2.1 Typical Application: Basic Voltage Reference Connection
The circuit shown in Figure 10-1 shows the basic configuration for the REF70 references. Connect bypass REF7025 ADS124S08 OPA2320 AIN0 AIN1 REFN0 Copyright © 2020, Texas Instruments Incorporated REFP0 AVDD AVSS AVDD GND OUTS OUTF VIN EN AVDD OPA2320 AVDD AVDD AIN Figure 10-1. Basic Reference Connection www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: REF70
10.2.1.1 Design Requirements
A detailed design procedure is based on a design example. For this design example, use the parameters listed in Table 10-1 as the input parameters. Table 10-1. Design Example Parameters DESIGN PARAMETER VALUE Input voltage VIN 5.5 V Output voltage VOUT 2.5 V REF7025 input capacitor 10-µF REF7025 output capacitor 10-µF
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Input and Output Capacitors
A 1 μF to 10 μF bypass capacitor should be connected to the input to improve transient response in applications where the supply voltage may fluctuate. Connect an additional 0.1 μF capacitor in parallel to reduce high frequency supply noise. A low ESR capacitor of 1 μF to 100 μF must be connected to the output to improve stability and help filter out high frequency noise. Best performance and stability is attained with low-ESR output capacitors with an ESR from 10 m Ω to 400 m Ω. For very low noise applications, special care must be taken with X7R and other MLCC capacitors due to their piezoelectric effect. Mechanical vibration can transduce to voltage via the piezoelectric effect which appears as noise in the μV range, potentially dominating the noise of the REF70. More information on how the piezoelectric effect can be explored in systems can be found in Stress-induced outbursts: Microphonics in ceramic capacitors (Part 1) and Stress-induced outbursts: Microphonics in ceramic capacitors (Part 2). It is recommended that to use film capacitors for noise sensitive applications. The transient startup response of the REF70 is shown in Figure 10-2. The startup response of the REF70 family is dependent on the output capacitor. While larger capacitors will decrease the output noise, they will increase the startup response. REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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Figure 10-2. REF7025 Startup (C = 10 μF)
10.2.1.2.2 Force and Sense Connection
Current flowing through a PCB trace produces an IR voltage drop, and with longer traces, this drop can reach several millivolts or more, introducing a considerable error into the output voltage of the reference. A 3000-mil long, 15-mil wide trace of 1-ounce copper has a resistance of approximately 100 m Ω at room temperature; at a load current of 10 mA, this can introduce a full millivolt of error. In an ideal board layout, the reference must be mounted as close as possible to the load to minimize the length of the output traces, and, therefore, the error introduced by voltage drop. However, in applications where this is not possible or convenient, force and sense connections (sometimes referred to as Kelvin sensing connections) are provided as a means of minimizing the IR drop and improving accuracy. Kelvin connections work by providing a set of high impedance voltage-sensing lines to the output and ground nodes. Because very little current flows through these connections, the IR drop across their traces is negligible, and the output and ground. The REF70 has kelvin connection capabilities due to its output force (OUTF) and input sense (OUTS) connection as shown in Basic Reference Connection . The output force voltage will vary upwards from the internal V REF voltage to ensure that at V OUT, which is where the OUTF and OUTS connect at the point-of-load, the voltage will be precisely V REF. The sense connection on the REF70 requires 4 mA due to its architecture, therefore if the load current is expected to be less than 4mA, then OUTF should be shorted to OUTS. It is always advantageous to use Kelvin connections whenever possible. However, in applications where the IR drop is negligible or an extra set of traces cannot be routed to the load, the force and sense pins for V OUT can simply be tied together close to the pins, and the device can be used in the same fashion as a normal 3-terminal reference. www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: REF70
10.2.2 Typical Application: DAC Force and Sense Reference Drive Circuit
Certain DACs require external voltage references to operate properly. There are DACs that only require a positive voltage for operating in which the basic connection will work. For other DACs there can be a need a positive and negative reference voltage due to their bipolar output. The circuit shown in Figure 10-3 shows a DAC force and sense reference drive circuit for the DACx1001 using the REF70. This circuit takes advantage of the DACx1001 RCM circuit to remove the need of additional external resistors to make a negative reference due to the integrated precision resistors. This circuit requires additional buffers due to undesired series resistance on the reference input of the DAC. REF7050 Copyright © 2020, Texas Instruments Incorporated GND OUTS OUTF VIN EN VIN CL CIN REFPF REFPS ROFS RCM RFB REFNS REFNF DACx1001 VREFN VREFP Figure 10-3. Basic Force and Sense Reference Drive Circuit Connections with DACx1001
10.2.2.1 Design Requirements
For this design example, use the reference op amp recommendation listed in Table 10-2 for the buffer circuit. Table 10-2. Reference Op Amp Options SELECTION PARAMETERS OP AMPS Low voltage and current noise OPA211, OPA827, OPA828 Low offset and drift OPA189 The REF70 turn-on time is dependent on the output capacitor. In certain applications that require a fast turn-on can require a smaller output capacitor as shown in Figure 10-4 REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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11 Power Supply Recommendation
The REF70 family of references features a low-dropout voltage. These references can be operated with a supply of only 50 mV above the output voltage for 0-mA output current conditions. The dropout voltage will vary with the output current so refer to the dropout voltage to see typical dropout voltage requirements. TI recommends a supply bypass capacitor ranging between 0.1 µF to 10 µF. During start-up the REF70 can experience moments of high input current due to the output capacitors. The input current can momentarily rise to ISC. Temperature (°C) Dropout Voltage (mV) -50 -25 0 25 50 75 100 125 100 150 200 250 300 0mA 5mA 10mA Figure 11-1. Dropout Voltage vs Temperature REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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12 Layout
12.1 Layout Guidelines
Figure 12-1 illustrates an example of a PCB layout for a data acquisition system using the REF70. Some key considerations are:
- Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN of the REF70.
- Connect low-ESR, 1-uF to 100-uF capacitor at OUTF of the REF70.
- Decouple other active devices in the system per the device specifications.
- Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Copyright © 2020, Texas Instruments Incorporated GND VIN EN GND GND OUTF OUTS GND CLCIN Analog GND Input Voltage VREF Enable Control Figure 12-1. Layout Example www.ti.com REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: REF70
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
- Texas Instruments, Voltage Reference Design Tips For Data Converters
- Texas Instruments, Voltage Reference Selection Basics
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. REF70 SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021 www.ti.com
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www.ti.com 7-Apr-2022 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PREF7030QFKHT ACTIVE LCCC FKH 8 250 TBD Call TI Call TI -40 to 125 PREF7033QFKHT ACTIVE LCCC FKH 8 250 TBD Call TI Call TI -40 to 125 PREF7040QFKHT ACTIVE LCCC FKH 8 250 TBD Call TI Call TI -40 to 125 REF7012QFKHT ACTIVE LCCC FKH 8 250 RoHS-Exempt & Green Call TI N / A for Pkg Type -40 to 125 REF12FKH REF7025QFKHT ACTIVE LCCC FKH 8 250 RoHS-Exempt & Green Call TI N / A for Pkg Type -40 to 125 REF25FKH REF7050QFKHT ACTIVE LCCC FKH 8 250 RoHS-Exempt & Green Call TI N / A for Pkg Type -40 to 125 REF50FKH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 7-Apr-2022 Addendum-Page 2 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2022 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF7012QFKHT LCCC FKH 8 250 210.0 185.0 35.0 REF7025QFKHT LCCC FKH 8 250 210.0 185.0 35.0 REF7050QFKHT LCCC FKH 8 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2022 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE 5.15 4.85
4.58 MAX
1.6 MAX
(2) 7X 1.2 0.8 8X 0.84 0.44 2.54 0.2 4X 1.27 0.2 (0.1) TYP (R0.2) TYP (0.65) TYP LCCC - 1.6 mm max heightFKH0008A LEADLESS CERAMIC CHIP CARRIER 4222330/C 12/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M 2. This drawing is subject to change without notice. 3. Terminals are gold plated. NOTE 3 PKG PKG 8TYP NOTE 3 TYP NOTE 3 SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
(4.4) 4X (1.27) (1.75) (2.2) 7X (1.6) 8X (0.7) (2.5) (R0.05) LCCC - 1.6 mm max heightFKH0008A LEADLESS CERAMIC CHIP CARRIER 4222330/C 12/2020 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:10X SYMM PKG PKG SOLDER MASK OPENING METAL SOLDER MASK DETAILS NON SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN 7X (1.6) 9X (0.7) 4X (1.27) (1.75) (4.4) (2.2) (2.5) LCCC - 1.6 mm max heightFKH0008A LEADLESS CERAMIC CHIP CARRIER 4222330/C 12/2020 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:12X PKG SYMM
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