REF6025 TI | Alldatasheet
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Reference Droop (LSB) Time (µs) C042 Regular Voltage Reference Droop REF60xx Droop Bandgap Voltage Reference C FILT C L R ESR R FILT Buffer VIN OUT_S OUT_F FILT VIN GND_S GND_F Power Supply SSREF60xx R LIM EN GND REF+ VIN R R R Power Supply R F R F R C FTHS4521 AINP AINN ADS8881 Copyright © 2016, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 SBOS708B –MAY 2016–REVISED AUGUST 2016 REF60xxHigh-PrecisionVoltageReferenceWithIntegratedADCDriveBuffer
1 Features
1• Excellent Temperature Drift Performance – 5 ppm/°C (max) from –40°C to +125°C
- Extremely Low Noise – Total Noise: 5 µVRMS With 47-µF Capacitor – 1/f Noise (0.1 Hz to 10 Hz): 3 µVPP/V
- Integrated ADC Drive Buffer – Low Output Impedance: < 50 mΩ (0-200 kHz) – First Sample Precise to 18 Bits With ADS8881 – Enables Burst-Mode DAQ Systems
- Low Supply Current: 820 μA
- Low Shutdown Current: 1 µA
- High Initial Accuracy: ±0.05%
- Very-Low Noise and Distortion – SNR: 100.5 dB, THD: –125 dB (ADS8881) – SNR: 106 dB, THD: –120 dB (ADS127L01)
- Output Current Drive: ±4 mA
- Programmable Short-Circuit Current
- Verified to Drive REF Pin of ADS88xx family of SAR ADCs and ADS127xx family of Wideband ΔΣ ADCs
2 Applications
- ATE Testers and Oscilloscopes
- Test and Measurement Equipment
- Analog Input Modules for PLCs
- Medical Equipment
- Precision Data Acquisition Systems
3 Description
The REF6000 family of voltage references have an integrated low output impedance buffer that enable the user to directly drive the REF pin of precision data converters, while preserving linearity, distortion, and noise performance. Most precision SAR and Delta-Sigma ADCs, switch binary-weighted capacitors onto the REF pin during the conversion process. In order to support this dynamic load the output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The REF6000 family devices are well suited, but not limited, to drive the REF pin of the ADS88xx family of SAR ADCs, and ADS127xx family of delta-sigma ADCs, as well as other digital-to-analog converters (DACs). The REF6000 family of voltage references are able to maintain an output voltage within 1LSB (18-bit) with minimal droop, even during the first conversion while driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time sampling, and variable-sampling-rate data-acquisition systems. The REF60xx variants of REF6000 family specify a maximum temperature drift of just 5 ppm/°C and initial accuracy of 0.05% for both the voltage reference and the low output impedance buffer combined. For various temperature drift options in REF6000 family, see the Device Comparison Table. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) REF60xx VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Application Reference Droop comparison (1 LSB = 19.07 µV, With ADS8881 at 1 MSPS)
REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 SBOS708B –MAY 2016–REVISED AUGUST 2016 www.ti.com Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Table of Contents
13.3 Receiving Notification of Documentation Updates 29
14 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision A (June 2016) to Revision B Page Changes from Original (May 2016) to Revision A Page
1VIN 8 GND_S 2EN 7 GND_F 3SS 6 OUT_F 4FILT 5 OUT_S REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 www.ti.com SBOS708B –MAY 2016–REVISED AUGUST 2016 Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
5 Device Comparison Table
DEVICE FAMILY TEMPERATURE DRIFT REF60xx 5 ppm/°C from –40 to 125°C REF61xx 8 ppm/°C from –40 to 125°C REF62xx 3 ppm/°C from 0 to 70°C
6 Pin Configuration and Functions
NAME NO. EN 2 Input Enable pin FILT 4 — Filter capacitor pin. A capacitor (CFILT) ≥ 1 µF must be connected between the FILT pin and ground for stability. GND_F 7 Ground Ground force pin GND_S 8 Ground Ground sense pin OUT_F 6 Output Output voltage force pin OUT_S 5 Input Output voltage sense pin SS 3 — Short circuit current limit pin. Connect a resistor to this pin to set the output short-circuit current limit. Connect to VIN pin for highest current limit VIN 1 Power Input supply voltage pin
REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 SBOS708B –MAY 2016–REVISED AUGUST 2016 www.ti.com Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Input voltage VIN –0.3 6 V VEN –0.3 VIN + 0.3 V Operating temperature, TA –55 150 °C Junction temperature, Tj 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
7.3 Recommended Operating Conditions
(IOUT = 0 mA) REF6025 3 5.5 VREF6030, REF6033, REF6041, REF6045 VOUT + 0.25 5.5 REF6050 5.3 5.5 VEN Enable voltage 0 VIN V IL Output current REF6025, REF6030, REF6033, REF6041 –4 4 mAREF6045 –3.5 3.5 REF6050 –3 3 TA Operating temperature –40 25 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) REF60xx UNITDGK (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 158.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.2 °C/W RθJB Junction-to-board thermal resistance 79.5 °C/W ψJT Junction-to-top characterization parameter 5.2 °C/W ψJB Junction-to-board characterization parameter 78.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 www.ti.com SBOS708B –MAY 2016–REVISED AUGUST 2016 Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) Temperature drift is specified according to the box method. See the Feature Description section for more details. (2) See the Thermal Hysteresis section.
7.5 Electrical Characteristics
at TA = 25°C, VIN = 5 V for all devices except REF6050, VIN = 5.4 V for REF6050, IL = 0 mA, CL = 22 µF, CFILT = 1 µF, and VEN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy -0.05% 0.05% Output voltage temperature coefficient(1) 5 ppm/°C LINE AND LOAD REGULATION ΔVO(ΔVI) Line regulation REF6025 VOUT + 0.5 V ≤ VIN ≤ 5.5 V TA = 25°C 4 20 ppm/V TA = –40°C to +125°C 30 REF6030, REF6033, REF6041, REF6045 VOUT + 0.25 V ≤ VIN ≤ 5.5 V TA = 25°C 4 20 TA = –40°C to +125°C 30 REF6050 VOUT + 0.3 V ≤ VIN ≤ 5.5 V TA = 25°C 7 60 TA = –40°C to +125°C 120 ΔVO(ΔIL) Load regulation, sourcing and sinking REF6025, REF6030, REF6033, REF6041 IL = 0 mA to 4 mA, VIN = VOUT + 600 mV TA = 25°C 2 20 ppm/mA TA = –40°C to +125°C 30 REF6045 IL = 0 mA to 3.5 mA, VIN = VOUT + 600 mV TA = 25°C 2 20 TA = –40°C to +125°C 30 REF6050 IL = 0 mA to 3 mA, VIN = VOUT + 400 mV TA = 25°C 2 20 TA = –40°C to +125°C 50 ISC Short-circuit current SS = open 10.5 mA NOISE Total integrated noise CL = 22 µF 5 µVRMS CL = 47 µF 5 Low frequency noise 0.1 Hz ≤ f ≤ 10 Hz 3 µVPP/V OUTPUT IMPEDANCE Output impedance f = DC to 200 kHz, CL= 47 μF 50 mΩ TURN-ON TIME ton Turn-on time 0.1% settling, CL = 47 µF, SS = open, REF6025 100 ms HYSTERESIS AND LONG TERM DRIFT Long term stability 0 to 1000h at 25°C 80 ppm 1000h to 2000h at 25°C 20 Output voltage hysteresis(2) 25°C, –40°C,125°C, 25°C (cycle 1) 33 ppm 25°C, –40°C,125°C, 25°C (cycle 2) 8 CAPACITIVE LOAD CL Stable output capacitor value 10 47 µF
REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 SBOS708B –MAY 2016–REVISED AUGUST 2016 www.ti.com Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) at TA = 25°C, VIN = 5 V for all devices except REF6050, VIN = 5.4 V for REF6050, IL = 0 mA, CL = 22 µF, CFILT = 1 µF, and VEN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VOLTAGE VOUT Output voltage REF6025 2.5 V REF6030 3 REF6033 3.3 REF6041 4.096 REF6045 4.5 REF6050 5 POWER SUPPLY ICC Supply current REF6025, REF6030, REF6033, REF6041 Active mode, VEN = 5 V TA = 25°C 0.82 0.90 mA TA = –40°C to +125°C 1.1 REF6045, REF6050 Active mode, VEN = 5 V TA = 25°C 0.83 0.95 TA = –40°C to +125°C 1.15 Shutdown mode, VEN = 0 V TA = 25°C 1 3 µA TA = –40°C to +125°C 15 Enable pin voltage Voltage reference in active mode (EN = 1) 1.6 V Voltage reference in shutdown mode (EN = 0) 0.6 Enable pin current VEN = 5 V 100 150 nA Dropout voltage REF6025 IL = 0 mA 500 500 mV IL = 4 mA 600 REF6030, REF6033, REF6041 IL = 0 mA 50 250 IL = 4 mA 600 REF6045 IL = 0 mA 50 250 IL = 3.5 mA 600 REF6050 IL = 0 mA 100 300 IL = 3 mA 400
7.6 Typical Characteristics
Figure 1. Drift Distribution Figure 2. Drift Distribution Figure 3. Initial Accuracy Distribution Figure 4. Solder-Heat Shift Distribution Figure 5. Output Voltage Accuracy vs Temperature Figure 6. Dropout Voltage vs Load Current
2 V/div
Figure 7. Load Regulation Sourcing vs Temperature Figure 8. Load Regulation Sinking vs Temperature Figure 9. Line Regulation vs Temperature Figure 10. Supply Current vs Temperature Figure 11. Supply Current vs Input Voltage Figure 12. Turn-On Settling Time
8 Parameter Measurement Information
8.1 Solder Heat Shift
soldering is a common cause of this error. Figure 41. Although all tested units exhibit very low shifts (< 0.03%), higher shifts are also possible depending on the size, thickness, and material of the PCB. Figure 40. Reflow Profile Figure 41. Solder Heat Shift Distribution
8.2 Thermal Hysteresis
- VHYST = thermal hysteresis (in units of ppm).
- VNOM = the specified output voltage.
- VPRE = output voltage measured at 25°C pretemperature cycling.
- VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature range of –40°C to 125°C and returns to 25°C. (1) Typical thermal hysteresis distribution is shown in Figure 42 and Figure 43.
Figure 42. Thermal Hysteresis Distribution (Cycle 1) Figure 43. Thermal Hysteresis Distribution (Cycle 2)
8.3 Reference Droop Measurements
negative full-scale inputs, respectively. Figure 44. Output Voltage Droop Figure 45. Output Voltage Droop multiple times, as described in the next paragraph.
OUT_S OUT_F FILT VIN GND_S GND_F SS EN REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 www.ti.com SBOS708B –MAY 2016–REVISED AUGUST 2016 Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
Most SAR ADCs, and a few delta-sigma ADCs, switch binary-weighted capacitors onto the REF pin during the conversion process. The magnitude of the capacitance switched onto the REF pin during each conversion depends on the input signal to the ADC. If a voltage reference is directly connected to the REF pin of these ADCs, the reference voltage droops because of the dynamic input signal dependent load of the binary-weighted capacitors. Because the reference voltage droop now has input signal dependance, significant degradation in THD and linearity for the system occurs. In order to support this dynamic load and preserve the ADC linearity, distortion and noise performance, the output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The REF60xx family of voltage references have an integrated low output impedance buffer that enables the user to directly drive the REF pin of a SAR ADC, while preserving ADC linearity and distortion. In addition, the total noise in the full bandwidth of the REF60xx is extremely low, thus preserving the noise performance of the ADC. Voltage-Reference Impact on Total Harmonic Distortion (SLYY097) correlates the effect of reference settling to ADC distortion, and how the REF60xx achieves lowest distortion with minimal components and lowest power consumption. The output voltage of the REF60xx does not droop below 1 LSB (18-bit), even during the first conversion while driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time sampling, and variable-sampling-rate data-acquisition systems. Functional Block Diagram shows a simplified schematic of the REF60xx.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Integrated ADC Drive Buffer
(usually high bandwidth) amplifier to achieve excellent linearity and distortion performance. are high-frequency specifications. Therefore, achieving all the performance in one amplifier requires power. Figure 49. Composite Amplifier Reference Buffer
J A D -$T T P R 9 3 9 3 9 3 9 3 SC SSI (115 *10 ) * R (4.6 *10 ) 9 3 SC SSI (80 *10 ) * R (3 *10 ) REF(MAX) REF(MIN) 6 REF V V Drift 10 (ppm)V Temperature Range REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 SBOS708B –MAY 2016–REVISED AUGUST 2016 www.ti.com Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Feature Description (continued)
9.3.2 Temperature Drift
The REF60xx family is designed for minimal drift error, defined as the change in output voltage over temperature. The drift is calculated using the box method, as described by the following equation: (3)
9.3.3 Load Current
The REF6025, REF6030, REF6033 and REF6041 are specified to deliver current load of ±4 mA. The REF6045 is specified to deliver ±3.5 mA, and the REF6050 is specified to deliver ±3 mA. The REF60xx are protected from short circuits at the output by limiting the output short-circuit current. The short-circuit current limit (ISC) of the REF60xx family of devices is adjusted by connecting a resistor (RSS) on the SS pin. The short-circuit current limit when the REF60xx device is sourcing current can be calculated as shown in Equation 4: (4) The short circuit current limit when the REF60xx device is sinking is calculated as shown in Equation 5: (5) The recommended output current of the REF60xx also depends on the resistor connected to the SS pin. The recommended output current (sourcing and sinking) for the REF6025, REF6030, REF6033 and REF6041 is given by Equation 6: (6) The recommended output current (sourcing and sinking) for the REF6045 is given by Equation 7: (7) The recommended output current (sourcing and sinking) for the REF6050 is given by Equation 8: (8) The temperature of the device increases according to Equation 9: where:
- TJ = junction temperature (°C).
- TA = ambient temperature (°C).
- PD = power dissipated (W).
- RθJA = junction-to-ambient thermal resistance (°C/W). (9) The REF60xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.3.4 Stability
The REF60xx family of voltage references are stable with output capacitor values ranging from 10 µF to 47 µF. Figure 53 shows the stable region of operation for the REF60xx devices. Figure 53. Stable Output Capacitor Range mΩ) is easily achieved by increasing the PCB trace length, thus eliminating the need for a discrete resistor. worsens noise performance because of increased bandwidth.
9.4 Device Functional Modes
enable pin voltage parameter in the Electrical Characteristics table for logic high and logic low voltage levels.
10 Applications and Implementation
validate and test their design implementation to confirm system functionality.
10.1 Application Information
operating at a throughput of 1 MSPS, for a 1-kHz, full-scale, pure sine-wave input.
10.2 Typical Application
Figure 54. 18-bit, 1-MSPS, Burst-Mode Data Acquisition system
10.2.1 Design Requirements
- Burst-mode support (see Reference Droop Measurements section for more details)
- Power consumption < 50 mW
10.2.2 Detailed Design Procedure
accuracy within the acquisition time of the ADC. connected to the FILT pin to reduce broadband noise of the REF60xx.
10.2.2.1 Results
Table 1 summarizes the measured results. Table 1. Measured Results
10.2.3 Application Curves
Figure 55. Typical FFT Plot Figure 56. Typical FFT Plot Figure 57. Typical FFT Plot Figure 58. Reference Droop Figure 59. Reference Droop Figure 60. Reference Droop
11 Power Supply Recommendations
VIN and GND_F pins of the REF60xx. A typical dropout voltage versus load is shown in Figure 61. Figure 61. Dropout Voltage vs Load Current
12 Layout
12.1 Layout Guidelines
- Connect low-ESR, 0.1-μF ceramic bypass capacitors between the VIN pin and ground.
- Place the REF60xx output capacitor (CL) and the ADC as close to each other as possible.
- Run two separate traces between VOUT_F, VOUT_S and the output capacitor, as shown in Figure 62.
- Short the GND_F and GND_S pins with a solid plane, and extend this plane to connect to the output capacitor CL, as shown in Figure 62.
- Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Figure 62. Layout Example
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
- ADS8881x 18-Bit, 1-MSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-to- Digital Converter Data Sheet (SBAS547)
- ADS127L01 24-Bit, High-Speed, Wide-Bandwidth Analog-to-Digital Converter Data Sheet (SBAS607)
- REF6025EVM-PDK User's Guide (SBAU258)
- Voltage-Reference Impact on Total Harmonic Distortion (SLYY097)
13.2 Related Links
resources, tools and software, and quick access to sample or buy. Table 2. Related Links
13.3 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
solve problems with fellow engineers. contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
REF6025,REF6030,REF6033,REF6041,REF6045,REF6050 SBOS708B –MAY 2016–REVISED AUGUST 2016 www.ti.com Product Folder Links: REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
13.7 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF6025IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11KV REF6025IDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11KV REF6025IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11KV REF6025IDGKT.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11KV REF6025IDGKTG4 Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11KV REF6025IDGKTG4.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11KV REF6030IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11LV REF6030IDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11LV REF6030IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11LV REF6030IDGKT.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11LV REF6033IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11MV REF6033IDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11MV REF6033IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11MV REF6033IDGKT.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11MV REF6041IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11NV REF6041IDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11NV REF6041IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11NV REF6041IDGKT.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11NV REF6041IDGKTG4 Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11NV REF6041IDGKTG4.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 11NV REF6045IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13SG REF6045IDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13SG REF6045IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13SG REF6045IDGKT.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13SG REF6050IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13QV REF6050IDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13QV REF6050IDGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13QV REF6050IDGKRG4.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13QV REF6050IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13QV Addendum-Page 1
www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF6050IDGKT.B Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 13QV (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF6025IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 REF6025IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 REF6025IDGKTG4 VSSOP DGK 8 250 223.0 270.0 35.0 REF6030IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 REF6030IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 REF6033IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 REF6033IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 REF6041IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 REF6041IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 REF6041IDGKTG4 VSSOP DGK 8 250 223.0 270.0 35.0 REF6045IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 REF6045IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 REF6050IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 REF6050IDGKRG4 VSSOP DGK 8 2500 346.0 346.0 29.0 REF6050IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
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