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+5V R 1 50Ÿ C 1 1.2nF IN IN VDD GNDREF VIN VOUT GND +5V C BYPASS 1µF C 2 µF Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 SBOS410G –JUNE 2007–REVISED NOVEMBER 2015 REF50xxLow-Noise,VeryLowDrift,Precision VoltageReference

1 Features 3 Description

The REF50xx is a family of low-noise, low-drift, very 1• Low Temperature Drift: high precision voltage references. These references– High-Grade: 3 ppm/°C (Maximum) are capable of both sinking and sourcing current, and – Standard-Grade: 8 ppm/°C (Maximum) have excellent line and load regulation.

  • High Accuracy: Excellent temperature drift (3 ppm/°C) and high – High-Grade: 0.05% (Maximum) accuracy (0.05%) are achieved using proprietary design techniques. These features, combined with– Standard-Grade: 0.1% (Maximum) very low noise, make the REF50xx family ideal for• Low Noise: 3 μVPP/V use in high-precision data acquisition systems.
  • Excellent Long-term Stability: Each reference voltage is available in both standard-– 45 ppm/1000 hr (typ) after 1000 Hours and high-grade versions. They are offered in MSOP-8
  • High-Output Current: ±10 mA and SO-8 packages, and are specified from –40°C to 125°C.• Temperature Range: –40°C to 125°C Device Information(1)

2 Applications

PART NUMBER PACKAGE BODY SIZE (NOM)

  • 16-Bit Data Acquisition Systems SOIC (8) 4.90 mm × 3.91 mm REF50xx• ATE Equipment VSSOP (8) 3.00 mm × 3.00 mm
  • Industrial Process Controls space• Medical Instrumentation space• Pressure and Temperature Transmitters (1) For all available packages, see the orderable addendum at• Seismic monitoring systems the end of the data sheet. Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 SBOS410G –JUNE 2007–REVISED NOVEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (December 2013) to Revision G Page

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision E (June 2010) to Revision F Page Changes from Revision D (April 2009) to Revision E Page

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Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 www.ti.com SBOS410G –JUNE 2007–REVISED NOVEMBER 2015 Changes from Revision C (December 2008) to Revision D Page Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

NC(2) VOUT TRIM/NR VIN DNC(1)DNC(1) NOTES: (1) DNC = Do not connect. (2) NC = No internal connection. REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 SBOS410G –JUNE 2007–REVISED NOVEMBER 2015 www.ti.com

5 Device Comparison Table

REF5020 2.048 V REF5025 2.5 V REF5030 3 V REF5040 4.096 V REF5045 4.5 V REF5050 5 V REF5010 10 V

6 Pin Configuration and Functions

DESCRIPTION

NAME NO. DNC 1 Do not connect VIN 2 Input supply voltage TEMP 3 Temperature monitoring pin. Provides a temperature-dependent output voltage GND 4 Ground TRIM/NR 5 Output adjustment and noise reduction pin VOUT 6 Reference voltage output NC 7 No internal connection DNC 8 Do not connect

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Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 www.ti.com SBOS410G –JUNE 2007–REVISED NOVEMBER 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage –0.2 18 V Output short circuit –30 30 mA Operating temperature –55 125 °C Junction temperature (TJ max) 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

7.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3000 V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification JESD22-C101, all ±1000pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN VOUT + 0.2 V(1) 18 V IOUT –10 10 mA (1) Except for REF5025, where VIN (min) = 2.7V

7.4 Thermal Information

THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 115 160.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 63.4 53.9 °C/W RθJB Junction-to-board thermal resistance 57.1 82.3 °C/W ψJT Junction-to-top characterization parameter 15.4 5.1 °C/W ψJB Junction-to-board characterization parameter 56.2 80.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 SBOS410G –JUNE 2007–REVISED NOVEMBER 2015 www.ti.com

7.5 Electrical Characteristics

At TA = 25°C, ILOAD = 0, CL = 1 μF, and VIN = (VOUT + 0.2 V) to 18 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VOLTAGE TEMPERATURE DRIFT dVOUT/dT Output Voltage Temperature Drift High-Grade 2.5 3 ppm/°C Standard-Grade 3 8 ppm/°C LINE REGULATION VIN = (VOUT + 0.2) TO 18 V(1) 0.1 1 ppm/V ΔVO(ΔVI) Line Regulation VIN = VOUT + 0.2 V, 0.2 1 ppm/VTA = –40°C to 125°C(1) LOAD REGULATION –10 mA < ILOAD < 10 mA, 20 30 ppm/mAVIN = VOUT + 0.75 V(2) ΔVO(ΔIL) Load Regulation –10 mA < ILOAD < 10 mA, VIN = VOUT + 0.75 V 50 ppm/mA TA = –40°C to 125°C(2) SHORT- CIRCUIT CURRENT ISC Short circuit current VOUT = 0 25 mA THERMAL HYSTERESIS(3) (4) High-Grade MSOP-8 Cycle 1 50 ppm Standard-Grade MSOP-8 Cycle 1 70 ppm High-Grade SO-8 Cycle 1 70 ppm Standard-Grade SO-8 Cycle 1 90 ppm High-Grade MSOP-8 Cycle 2 40 ppm Standard-Grade MSOP-8 Cycle 2 40 ppm High-Grade SO-8 Cycle 2 50 ppm Standard-Grade SO-8 Cycle 2 50 ppm LONG-TERM STABILITY(4) MSOP-8 0 to 1000 hours 125 ppm/1000 hr MSOP-8 1000 to 2000 hours 45 ppm/1000 hr SO-8 0 to 1000 hours 100 ppm/1000 hr SO-8 1000 to 2000 hours 50 ppm/1000 hr TEMP PIN Voltage Output At TA = 25°C 575 mV Temperature Sensitivity TA = -40°C to 125°C 2.64 mV/°C TURNON SETTLING TIME Turnon Settling Time To 0.1% with CL = 1 μF 200 μs POWER SUPPLY VOUT +VS Supply Voltage See Note (5) 18 V0.2(5) 0.8 1 mA Quiescent Current TA = -40°C to 125°C 1.2 mA TEMPERATURE RANGE Specified Range –40 125 °C Operating Range –55 125 °C (1) Except for REF5020, where VIN = 2.7 V to 18 V. (2) Except for REF5020, where VIN = 3 V. (3) The thermal hysteresis procedure is explained in more detail in the Thermal Hysteresis section. (4) Data collected using devices soldered onto the test board. (5) For VOUT ≤ 2.5 V, the minimal supply voltage is 2.7 V.

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Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

7.6 Typical Characteristics

Figure 1. Temperature Drift Figure 2. Temperature Drift Figure 3. Output Voltage Initial Accuracy Figure 4. Output Voltage Accuracy vs Temperature Figure 5. Power-Supply Rejection Ratio vs Frequency Figure 6. Dropout Voltage vs Load Current

Figure 7. REF5025 Output Voltage vs Load Current Figure 8. Temp Pin Output Voltage vs Temperature Figure 9. Quiescent Current vs Temperature Figure 10. Quiescent Current vs Input Voltage Figure 11. Line Regulation vs Temperature Figure 12. Short Circuit Current vs Temperature

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1 V/div/c109

Figure 14. Start-UpFigure 13. NOISE Figure 15. Start-Up Figure 16. Load Transient Figure 17. Load Transient Figure 18. Load Transient

Figure 19. Load Transient Figure 20. Line Transient Figure 21. Line Transient Figure 22. REF50xx Long-Term Stability (First 1000 Hours) Figure 23. REF50xx Long-Term Stability (Second 1000 Figure 24. REF50xx Long-Term Stability (2000 Hours)

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8 Parameter Measurement Information

8.1 Solder Heat Shift

circuit-board is comprised of FR4 material. The board thickness is 0.8 mm and the area is 13 mm × 13 mm. pass to minimize its exposure to thermal stress. Figure 28. Reflow Profile

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Figure 35. Drift Shift Distribution, SOIC Package Figure 36. Drift Shift Distribution, MSOP Package

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/c97T /c97T (10 A/c109 at□+25 C)/c176 R2 R1 10k/c87 1k/c871.2V REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 www.ti.com SBOS410G –JUNE 2007–REVISED NOVEMBER 2015

9 Detailed Description

9.1 Overview

The REF50xx is family of low-noise, precision bandgap voltage references that are specifically designed for excellent initial voltage accuracy and drift. See Functional Block Diagram for a simplified block diagram of the REF50xx.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Temperature Monitoring

The temperature output terminal (TEMP, pin 3) provides a temperature-dependent voltage output with approximately 60-kΩ source impedance. As seen in Figure 8, the output voltage follows the nominal relationship: VTEMP PIN = 509 mV + 2.64 × T(°C) (1) This pin indicates general chip temperature, accurate to approximately ±15°C. Although it is not generally suitable for accurate temperature measurements, it can be used to indicate temperature changes or for temperature compensation of analog circuitry. A temperature change of 30°C corresponds to an approximate 79- mV change in voltage at the TEMP pin. The TEMP pin has high-output impedance (see Functional Block Diagram). Loading this pin with a low- impedance circuit induces a measurement error; however, it does not have any effect on VOUT accuracy. To avoid errors caused by low-impedance loading, buffer the TEMP pin output with a suitable low-temperature drift op amp, such as the OPA333, OPA335, or OPA376, as shown in Figure 37. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

NOTE:□(1)□Low□drift□op□amp,□such□as□the□OPA333,□OPA335,□or□OPA376. Figure 37. Buffering the TEMP Pin Output

9.3.2 Temperature Drift

temperature. The drift is calculated using the box method, as described show in Equation 2.

9.3.3 Thermal Hysteresis

  • VHYST = thermal hysteresis (in units of ppm).
  • VNOM = the specified output voltage.
  • VPRE = output voltage measured at 25°C pretemperature cycling.
  • VPOST = output voltage measured after the device has been cycled from 25°C through the specified temperature range of –40°C to 125°C and returned to 25°C. (3)

9.3.4 Noise Performance

output noise levels, although take care to ensure the output impedance does not degrade performance. three literature numbers: SLYT331, SLYT339, and SLYT355 for Part I, Part II, and Part III, respectively.

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1 F/c109

Figure 38. Noise Reduction Using the TRIM/NR Pin

9.3.5 Output Adjustment Using the TRIM/NR Pin

Figure 39. VOUT Adjustment Using the TRIM/NR Pin frequency, further reducing output noise. Using this capacitor increases start-up time.

9.4 Device Functional Modes

9.4.1 Basic Connections

NOTE:□Bypass□capacitors□not□shown.

1 F□to□10 F/c109 /c109

1 F□to□50 F/c109 /c109

Figure 40. Basic Connections

9.4.2 Supply Voltage

versus load plot is shown in Figure 6 in the Typical Characteristics.

9.4.3 Negative Reference Voltage

Figure 41. The REF5025 and OPA735 Create Positive and Negative Reference Voltages

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10 Applications and Implementation

validate and test their design implementation to confirm system functionality.

10.1 Application Information

shows the REF5040 in a basic data acquisition system.

10.2 Typical Applications

Figure 42. Complete Data Acquisition System Using REF50xx

10.2.1.1 Design Requirements

10.2.1.2 Detailed Design Procedure

the bandwidth of the RC filter.

REF50xx and different values of capacitors at the TRIM/NR pin are shown in Table 1. Table 1. Data Acquisition Measurement Results for Different Conditions

10.2.1.3 Application Curve

Figure 43. FFT plot- Noise floor of Data Acquisition system

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11 Power Supply Recommendations

12 Layout

12.1 Layout Guidelines

  • Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The recommended value of this bypass capacitor is from 1 μF to 10 μF. If necessary, additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies.
  • Place a 1-μF noise filtering capacitor between the NR pin and ground.
  • The output must be decoupled with a 1-μF to 50-μF capacitor. In series with load capacitor, add an ESR of 1 Ω for the best noise performance.
  • A high-frequency, 1-μF capacitor can be added in parallel between the output and ground to filter noise and help with switching loads as data converters.

12.2 Layout Example

Figure 44. Layout Example

12.3 Power Dissipation

  • TJ = Junction temperature (°C)
  • TA = Ambient temperature (°C)
  • PD = Power dissipated (W)
  • θJA = Junction-to-ambient thermal resistance (°C/W) (4) The REF50xx junction temperature must not exceed the absolute maximum rating of 150°C. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

  • 0.05uV/degC (max), Single-Supply CMOS Zero-Drift Series Operational Amplifier, SBOS282.
  • REF5020 PSpice Model, SLIM160.
  • REF5020 TINA-TI Reference Design, SLIM159.
  • REF5020 TINA-TI Spice Model, SLIM158.
  • INA270 PSpice Model, SBOM485.
  • INA270 TINA-TI Reference Design, SBOC246.
  • INA270 TINA-TI Spice Model, SBOM306.

13.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

13.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

13.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

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REF5010,REF5020,REF5025,REF5030 REF5040,REF5045,REF5050 www.ti.com SBOS410G –JUNE 2007–REVISED NOVEMBER 2015

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050

www.ti.com 24-Sep-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF5010AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50G REF5010AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50G REF5010AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5010 REF5010IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50G REF5010IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50G REF5020AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 A REF5020AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 A REF5020AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50A REF5020AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50A REF5020AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 A REF5020AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 A REF5020ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020

www.ti.com 24-Sep-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF5020IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 REF5020IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50A REF5020IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50A REF5020IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 REF5020IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 REF5025AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50B REF5025AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50B REF5025AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 REF5025IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 REF5025IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50B REF5025IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50B REF5025IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025

www.ti.com 24-Sep-2015 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF5025IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 REF5030AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 REF5030IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 REF5030IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50C REF5030IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50C REF5030IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 REF5040AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50D

www.ti.com 24-Sep-2015 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF5040AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50D REF5040AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 REF5040IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 REF5040IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50D REF5040IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50D REF5040IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 REF5040IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 REF5045AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50E REF5045AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50E REF5045AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 REF5045IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50E

www.ti.com 24-Sep-2015 Addendum-Page 5 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF5045IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50E REF5045IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 REF5050AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 A REF5050AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 A REF5050AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 A REF5050ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 REF5050IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 REF5050IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50F REF5050IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 R50F REF5050IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 REF5050IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 24-Sep-2015 Addendum-Page 6 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF REF5020, REF5025, REF5040, REF5050 :

  • Enhanced Product: REF5020-EP , REF5025-EP , REF5040-EP , REF5050-EP NOTE: Qualified Version Definitions:
  • Enhanced Product - Supports Defense, Aerospace and Medical Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 1

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF5010AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5010AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5010AIDR SOIC D 8 2500 367.0 367.0 35.0 REF5010IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5010IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5020AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5020AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5020AIDR SOIC D 8 2500 367.0 367.0 35.0 REF5020IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5020IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5020IDR SOIC D 8 2500 367.0 367.0 35.0 REF5025AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5025AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5025AIDR SOIC D 8 2500 367.0 367.0 35.0 REF5025IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5025IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5025IDR SOIC D 8 2500 367.0 367.0 35.0 REF5030AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5030AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5030AIDR SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 3

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF5030IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5030IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5030IDR SOIC D 8 2500 367.0 367.0 35.0 REF5040AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5040AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5040AIDR SOIC D 8 2500 367.0 367.0 35.0 REF5040IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5040IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5040IDR SOIC D 8 2500 367.0 367.0 35.0 REF5045AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5045AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5045AIDR SOIC D 8 2500 367.0 367.0 35.0 REF5045IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5045IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5045IDR SOIC D 8 2500 367.0 367.0 35.0 REF5050AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5050AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5050AIDR SOIC D 8 2500 367.0 367.0 35.0 REF5050IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 REF5050IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 REF5050IDR SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 4

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