REF2025_18 TI1 | Alldatasheet
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3.0 V VBIAS 1.5 V EN ADC GND LOAD ISENSER SHUNT VIN- VIN+ REF VOUT Power Supply -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 ±75 ±50 ±25 0 25 50 75 100 125 150 Output Voltage Accuracy (%) Temperature (C) C001 VREF VBIAS Product Folder Order Now T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. REF2025,REF2030,REF2033,REF2041 SBOS600C –MAY 2014–REVISED JANUARY 2017 REF20xxLow-Drift,Low-Power,Dual-Output,VREFandVREF/2VoltageReferences
1 Features
1• Two Outputs, VREF and VREF / 2, for Convenient Use in Single-Supply Systems
- Excellent Temperature Drift Performance: – 8 ppm/°C (max) from –40°C to 125°C
- High Initial Accuracy: ±0.05% (max)
- VREF and VBIAS Tracking over Temperature: – 6 ppm/°C (max) from –40°C to 85°C – 7 ppm/°C (max) from –40°C to 125°C
- Microsize Package: SOT23-5
- Low Dropout Voltage: 10 mV
- High Output Current: ±20 mA
- Low Quiescent Current: 360 μA
- Line Regulation: 3 ppm/V
- Load Regulation: 8 ppm/mA
2 Applications
- Digital Signal Processing: – Power Inverters – Motor Controls
- Current Sensing
- Industrial Process Controls
- Medical Equipment
- Data Acquisition Systems
- Single-Supply Systems
3 Description
Applications with only a positive supply voltage often require additional stable voltage in the middle of the analog-to-digital converter (ADC) input range to bias input bipolar signals. The REF20xx provides a reference voltage (VREF) for the ADC and a second highly-accurate voltage (VBIAS) that can be used to bias the input bipolar signals. The REF20xx offers excellent temperature drift (8 ppm/°C, max) and initial accuracy (0.05%) on both the VREF and VBIAS outputs while operating at a quiescent current less than 430 µA. In addition, the VREF and VBIAS outputs track each other with a precision of 6 ppm/°C (max) across the temperature range of –40°C to 85°C. All these features increase the precision of the signal chain and decrease board space, while reducing the cost of the system as compared to a discrete solution. Extremely low dropout voltage of only 10 mV allows operation from very low input voltages, which can be very useful in battery-operated systems. Both the VREF and VBIAS voltages have the same excellent specifications and can sink and source current equally well. Very good long-term stability and low noise levels make these devices ideally-suited for high-precision industrial applications. Device Information(1) PART NAME PACKAGE BODY SIZE (NOM) REF20xx SOT (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space Application Example VREF and VBIAS vs Temperature
REF2025,REF2030,REF2033,REF2041 SBOS600C –MAY 2014–REVISED JANUARY 2017 www.ti.com Product Folder Links: REF2025 REF2030 REF2033 REF2041 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Table of Contents
13.3 Receiving Notification of Documentation Updates 25
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (July 2014) to Revision C Page Changes from Revision A (June 2014) to Revision B Page Changes from Original (May 2014) to Revision A Page
REF2025,REF2030,REF2033,REF2041 www.ti.com SBOS600C –MAY 2014–REVISED JANUARY 2017 Product Folder Links: REF2025 REF2030 REF2033 REF2041 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
5 Device Comparison Table
REF2025 2.5 V 1.25 V REF2030 3.0 V 1.5 V REF2033 3.3 V 1.65 V REF2041 4.096 V 2.048 V
6 Pin Configuration and Functions
(Top View) Pin Functions PIN I/O DESCRIPTION NO. NAME
1 VBIAS Output Bias voltage output (VREF / 2)
2 GND — Ground
3 EN Input Enable (EN ≥ VIN – 0.7 V, device enabled)
4 VIN Input Input supply voltage
5 VREF Output Reference voltage output (VREF)
REF2025,REF2030,REF2033,REF2041 SBOS600C –MAY 2014–REVISED JANUARY 2017 www.ti.com Product Folder Links: REF2025 REF2030 REF2033 REF2041 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN –0.3 6 V EN –0.3 VIN + 0.3 Temperature Operating –55 150 °CJunction, Tj 150 Storage, Tstg –65 170 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 (1) See Figure 28 in Typical Characteristics for minimum input voltage at different load currents and temperature
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Supply input voltage range (IL = 0 mA, TA = 25°C) VREF + 0.02(1) 5.5 V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) REF20xx UNITDDC (SOT23)
5 PINS
RθJA Junction-to-ambient thermal resistance 193.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 40.2 °C/W RθJB Junction-to-board thermal resistance 34.5 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 34.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
REF2025,REF2030,REF2033,REF2041 www.ti.com SBOS600C –MAY 2014–REVISED JANUARY 2017 Product Folder Links: REF2025 REF2030 REF2033 REF2041 Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated (1) Temperature drift is specified according to the box method. See the Feature Description section for more details. (2) The VREF and VBIAS tracking over temperature specification is explained in more detail in the Feature Description section. (3) The peak-to-peak noise measurement procedure is explained in more detail in the Noise Performance section. (4) The thermal hysteresis measurement procedure is explained in more detail in the Thermal Hysteresis section.
7.5 Electrical Characteristics
At TA = 25°C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy –0.05% 0.05% Output voltage temperature coefficient(1) –40°C ≤ TA ≤ 125°C ±3 ±8 ppm/°C VREF and VBIAS tracking over temperature(2) –40°C ≤ TA ≤ 85°C ±1.5 ±6 ppm/°C LINE AND LOAD REGULATION ΔVO(ΔVI) Line regulation VREF + 0.02 V ≤ VIN ≤ 5.5 V 3 35 ppm/V ΔVO(ΔIL) Load regulation Sourcing 0 mA ≤ IL ≤ 20 mA , VREF + 0.6 V ≤ VIN ≤ 5.5 V 8 20 ppm/mA Sinking 0 mA ≤ IL ≤ –20 mA, VREF + 0.02 V ≤ VIN ≤ 5.5 V 8 20 POWER SUPPLY ICC Supply current Active mode 360 430 µA –40°C ≤ TA ≤ 125°C 460 Shutdown mode 3.3 5 –40°C ≤ TA ≤ 125°C 9 Enable voltage Device in shutdown mode (EN = 0) 0 0.7 V Device in active mode (EN = 1) VIN – 0.7 VIN Dropout voltage 10 20 mV IL = 20 mA 600 ISC Short-circuit current 50 mA ton Turn-on time 0.1% settling, CL = 1 µF 500 µs NOISE Low-frequency noise(3) 0.1 Hz ≤ f ≤ 10 Hz 12 ppmPP Output voltage noise density f = 100 Hz 0.25 ppm/√Hz CAPACITIVE LOAD Stable output capacitor range 0 10 µF HYSTERESIS AND LONG TERM STABILITY Long-term stability 0 to 1000 hours 60 ppm Output voltage hysteresis(4) 25°C, –40°C, 125°C, 25°C Cycle 1 60 ppm Cycle 2 35
7.6 Typical Characteristics
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted. Figure 1. Initial Accuracy Distribution (VREF) Figure 2. Drift Distribution (VREF) Figure 3. Initial Accuracy Distribution (VBIAS) Figure 4. Drift Distribution (VBIAS) Figure 5. VREF – 2 × VBIAS Distribution Figure 6. Distribution of VREF – 2 × VBIAS Drift Tracking
2 V/div
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted. Figure 25. Load Transient Response Figure 26. Load Transient Response Figure 27. Load Transient Response Figure 28. Minimum Dropout Voltage vs Load Current Figure 29. Turn-On Settling Time Figure 30. Turn-On Settling Time
8 Parameter Measurement Information
8.1 Solder Heat Shift
board thickness is 1.57 mm and the area is 171.54 mm × 165.1 mm. its exposure to thermal stress. Figure 40. Reflow Profile Figure 41. Solder Heat Shift Distribution, VREF (%) Figure 42. Solder Heat Shift Distribution, VBIAS (%)
8.2 Thermal Hysteresis
- VHYST = thermal hysteresis (in units of ppm),
- VNOM = the specified output voltage,
- VPRE = output voltage measured at 25°C pre-temperature cycling, and
- VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature range of –40°C to 125°C and returns to 25°C. (1) Typical thermal hysteresis distribution is as shown in Figure 43 and Figure 44.
Figure 43. Thermal Hysteresis Distribution (VREF) Figure 44. Thermal Hysteresis Distribution (VBIAS)
0.1 Hz to 10 Hz Filter
8.3 Noise Performance
noise measurement setup is shown in Figure 47. Figure 45. 0.1-Hz to 10-Hz Noise (VREF) Figure 46. 0.1-Hz to 10-Hz Noise (VBIAS) Figure 47. 0.1-Hz to 10-Hz Noise Measurement Setup
DIFF REF BIASV V 2 V DIFF(MAX) DIFF (MIN) 6 REF V V Tracking Error 10 (ppm)V Temperature Range e-Trim e-Trim VREF VBIAS R 3 R 4 R 1 R 2 Q 1 Q 2 VBE1 VBE2 - - + + R 5 R 7R 6 REF2025,REF2030,REF2033,REF2041 SBOS600C –MAY 2014–REVISED JANUARY 2017 www.ti.com Product Folder Links: REF2025 REF2030 REF2033 REF2041 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
The REF20xx are a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The Functional Block Diagram section provides a block diagram of the basic band-gap topology and the two buffers used to derive the VREF and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of Q2. The difference of the two base emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2, which has a negative temperature coefficient. The resulting band-gap output voltage is almost independent of temperature. Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The resistors R1, R2 and R3, R4 are sized such that VBIAS = VREF / 2. e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and VBIAS, implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is implemented in the REF20xx to minimize the temperature drift and maximize the initial accuracy of both the VREF and VBIAS outputs.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 VREF and VBIAS Tracking
Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter (ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF20xx are generated from the same band-gap voltage as shown in the Functional Block Diagram section. Hence, both outputs track each other over the full temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (max). The tracking accuracy increases to 6 ppm/°C (max) when the temperature range is limited to –40°C to 85°C. The tracking error is calculated using the box method, as described by Equation 2: where
- (2)
The tracking accuracy is as shown in Figure 48. Figure 48. VREF and VBIAS Tracking vs Temperature
9.3.2 Low Temperature Drift
9.3.3 Load Current
- TJ = junction temperature (°C),
- TA = ambient temperature (°C),
- PD = power dissipated (W), and
- RθJA = junction-to-ambient thermal resistance (°C/W) (4) The REF20xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.4 Device Functional Modes
mode for normal operation. The REF20xx can be placed in a low-power mode by pulling the ENABLE pin low.
10 Applications and Implementation
validate and test their design implementation to confirm system functionality.
10.1 Application Information
supply and reference voltages are supplied by the low-drift REF2030.
10.2 Typical Application
10.2.1 Low-Side, Current-Sensing Application
Figure 49. Low-Side, Current-Sensing Application
10.2.1.1 Design Requirements
- Maximum shunt voltage: ±25 mV
10.2.1.2 Detailed Design Procedure
design procedure, refer to TIDU357. Figure 50. Low-Drift, Low-side, Bidirectional, Current-Sensing Circuit Topology
10.2.1.2.1 Shunt Resistor
can be used to calculate the maximum value of RSHUNT. resistance is calculated as shown in Equation 7. resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used.
10.2.1.2.2 Differential Amplifier
- Low initial input offset voltage (VOS),
- Low-side sensing (input common-mode range below ground).
INA213B specifications can be found in the INA213 product data sheet. Figure 51. INA21x Current-Shunt Monitor Topology amplifiers use external resistors that are not conducive to low-drift applications.
10.2.1.2.3 Voltage Reference
- Dual output (3.0 V and 1.5 V),
- Low tracking errors between the two outputs.
across temperature, as shown in Figure 52 and Figure 53. Figure 52. VREF – 2 × VBIAS Distribution (At TA = 25°C) Figure 53. Distribution of VREF – 2 × VBIAS Drift Tracking
10.2.1.2.4 Results
Table 1 summarizes the measured results. Table 1. Measured Results
10.2.1.3 Application Curves
measurement procedure, calibration, and calculations, please refer to TIDU357. Figure 54. Measured Transfer Function Figure 55. Uncalibrated Error vs Load Current Figure 56. Calibrated Error vs Load Current
11 Power-Supply Recommendations
versus load is shown in Figure 57. A supply bypass capacitor ranging between 0.1 µF to 10 µF is recommended. Figure 57. Dropout Voltage vs Load Current
12 Layout
12.1 Layout Guidelines
- Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030.
- Decouple other active devices in the system per the device specifications.
- Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
- Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Figure 58. Layout Example
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
- INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt Monitors (SBOS437)
- Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design (TIDU357)
13.2 Related Links
resources, tools and software, and quick access to sample or buy. Table 2. Related Links
13.3 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
solve problems with fellow engineers. contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments. e-Trim is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
This glossary lists and explains terms, acronyms, and definitions.
REF2025,REF2030,REF2033,REF2041 SBOS600C –MAY 2014–REVISED JANUARY 2017 www.ti.com Product Folder Links: REF2025 REF2030 REF2033 REF2041 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 16-May-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF2025AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GACM REF2025AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GACM REF2025AISDDCR PREVIEW SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 1M98 REF2030AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GADM REF2030AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GADM REF2033AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEM REF2033AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEM REF2041AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFM REF2041AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 16-May-2018 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant REF2025AIDDCR SOT- 23-THIN REF2025AIDDCT SOT- 23-THIN REF2025AISDDCR SOT- 23-THIN REF2030AIDDCR SOT- 23-THIN REF2030AIDDCT SOT- 23-THIN REF2033AIDDCR SOT- 23-THIN REF2033AIDDCT SOT- 23-THIN REF2041AIDDCR SOT- 23-THIN REF2041AIDDCT SOT- 23-THIN PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2018 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF2025AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2025AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 REF2025AISDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2030AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2030AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 REF2033AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2033AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 REF2041AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2041AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2018 Pack Materials-Page 2
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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non- compliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated