REF2025 TI1 | Alldatasheet
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3.0 V VBIAS 1.5 V EN ADC GND LOAD ISENSER SHUNT VIN- VIN+ REF VOUT Power Supply -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 /cb175 /cb150 /cb125 0 25 50 75 100 125 150 Output Voltage Accuracy (%) Temperature (/c83C) C001 VREF VBIAS Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design REF2025,REF2030,REF2033,REF2041 SBOS600B –MAY 2014–REVISED JULY 2014 REF20xxLow-Drift,Low-Power,Dual-Output,VREFandVREF/2VoltageReferences
1 Features 3 Description
Applications with only a positive supply voltage often 1• Two Outputs, VREF and VREF / 2, for Convenient require additional stable voltage in the middle of theUse in Single-Supply Systems analog-to-digital converter (ADC) input range to bias• Excellent Temperature Drift Performance: input bipolar signals. The REF20xx provides a – 8 ppm/°C (max) from –40°C to 125°C reference voltage (VREF) for the ADC and a second highly-accurate voltage (VBIAS) that can be used to• High Initial Accuracy: ±0.05% (max) bias the input bipolar signals.• VREF and VBIAS Tracking over Temperature: The REF20xx offers excellent temperature drift– 6 ppm/°C (max) from –40°C to 85°C (8 ppm/°C, max) and initial accuracy (0.05%) on both– 7 ppm/°C (max) from –40°C to 125°C the VREF and VBIAS outputs while operating at a
- Microsize Package: SOT23-5 quiescent current less than 430 µA. In addition, the VREF and VBIAS outputs track each other with a• Low Dropout Voltage: 10 mV precision of 6 ppm/°C (max) across the temperature• High Output Current: ±20 mA range of –40°C to 85°C. All these features increase
- Low Quiescent Current: 360 μA the precision of the signal chain and decrease board space, while reducing the cost of the system as• Line Regulation: 3 ppm/V compared to a discrete solution. Extremely low• Load Regulation: 8 ppm/mA dropout voltage of only 10 mV allows operation from very low input voltages, which can be very useful in2 Applications battery-operated systems.
- Digital Signal Processing: Both the VREF and VBIAS voltages have the same – Power Inverters excellent specifications and can sink and source current equally well. Very good long-term stability and– Motor Controls low noise levels make these devices ideally-suited for• Current Sensing high-precision industrial applications.• Industrial Process Controls
- Medical Equipment Device Information(1) PART NAME PACKAGE BODY SIZE (NOM)• Data Acquisition Systems REF20xx SOT (5) 2.90 mm × 1.60 mm• Single-Supply Systems (1) For all available packages, see the orderable addendum at the end of the datasheet. space space Application Example VREF and VBIAS vs Temperature An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF2025,REF2030,REF2033,REF2041 SBOS600B –MAY 2014–REVISED JULY 2014 www.ti.com Table of Contents
4 Revision History
Changes from Revision A (June 2014) to Revision B Page Changes from Original (May 2014) to Revision A Page
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Product Folder Links: REF2025 REF2030 REF2033 REF2041
REF2025,REF2030,REF2033,REF2041 www.ti.com SBOS600B –MAY 2014–REVISED JULY 2014
5 Device Comparison Table
REF2025 2.5 V 1.25 V REF2030 3.0 V 1.5 V REF2033 3.3 V 1.65 V REF2041 4.096 V 2.048 V
6 Pin Configuration and Functions
(Top View) Pin Functions PIN
DESCRIPTION
NO. NAME
1 VBIAS Bias voltage output (VREF / 2)
2 GND Ground
3 EN Enable (EN ≥ VIN – 0.7 V, device enabled)
4 VIN Input supply voltage
5 VREF Reference voltage output (VREF)
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: REF2025 REF2030 REF2033 REF2041
REF2025,REF2030,REF2033,REF2041 SBOS600B –MAY 2014–REVISED JULY 2014 www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN –0.3 6 V Input voltage EN –0.3 VIN + 0.3 V Operating temperature range –55 150 °C Temperature Junction Temperature, Tj 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg Storage temperature range –65 170 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –4000 4000pins(1) V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification –1500 1500JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Supply input voltage range (IL = 0 mA, TA = 25°C) VREF + 0.02(1) 5.5 V (1) Please refer to Figure 28 in Typical Characteristics for minimum input voltage at different load currents and temperature
7.4 Thermal Information
THERMAL METRIC(1) DDC (SOT23) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 193.6 RθJC(top) Junction-to-case (top) thermal resistance 40.2 RθJB Junction-to-board thermal resistance 34.5 °C/W ψJT Junction-to-top characterization parameter 0.9 ψJB Junction-to-board characterization parameter 34.3 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: REF2025 REF2030 REF2033 REF2041
REF2025,REF2030,REF2033,REF2041 www.ti.com SBOS600B –MAY 2014–REVISED JULY 2014
7.5 Electrical Characteristics
At TA = 25°C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy –0.05% 0.05% Output voltage temperature coefficient(1) –40°C ≤ TA ≤ 125°C ±3 ±8 ppm/°C –40°C ≤ TA ≤ 85°C ±1.5 ±6 ppm/°C VREF and VBIAS tracking over temperature(2) –40°C ≤ TA ≤ 125°C ±2 ±7 ppm/°C LINE AND LOAD REGULATION ΔVO(ΔVI) Line regulation VREF + 0.02 V ≤ VIN ≤ 5.5 V 3 35 ppm/V 0 mA ≤ IL ≤ 20 mA ,Sourcing 8 20 ppm/mAVREF + 0.6 V ≤ VIN ≤ 5.5 V ΔVO(ΔIL) Load regulation 0 mA ≤ IL ≤ –20 mA,Sinking 8 20 ppm/mAVREF + 0.02 V ≤ VIN ≤ 5.5 V POWER SUPPLY 360 430 µA Active mode –40°C ≤ TA ≤ 125°C 460 µA ICC Supply current 3.3 5 µA Shutdown mode –40°C ≤ TA ≤ 125°C 9 µA Device in shutdown mode (EN = 0) 0 0.7 V Enable voltage Device in active mode (EN = 1) VIN – 0.7 VIN V 10 20 mV Dropout voltage IL = 20 mA 600 mV ISC Short-circuit current 50 mA ton Turn-on time 0.1% settling, CL = 1 µF 500 µs NOISE Low-frequency noise(3) 0.1 Hz ≤ f ≤ 10 Hz 12 ppmPP Output voltage noise density f = 100 Hz 0.25 ppm/√Hz CAPACITIVE LOAD Stable output capacitor range 0 10 µF HYSTERESIS AND LONG TERM STABILITY Long-term stability 0 to 1000 hours 60 ppm Cycle 1 60 ppm Output voltage hysteresis(4) 25°C, –40°C, 125°C, 25°C Cycle 2 35 ppm (1) Temperature drift is specified according to the box method. See the Feature Description section for more details. (2) The VREF and VBIAS tracking over temperature specification is explained in more detail in the Feature Description section. (3) The peak-to-peak noise measurement procedure is explained in more detail in the Noise Performance section. (4) The thermal hysteresis measurement procedure is explained in more detail in the Thermal Hysteresis section. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: REF2025 REF2030 REF2033 REF2041
7.6 Typical Characteristics
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted. Figure 1. Initial Accuracy Distribution (VREF) Figure 2. Drift Distribution (VREF) Figure 3. Initial Accuracy Distribution (VBIAS) Figure 4. Drift Distribution (VBIAS) Figure 6. Distribution of VREF – 2 × VBIAS Drift TrackingFigure 5. VREF – 2 × VBIAS Distribution
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At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted. Figure 14. Load Regulation Sourcing vs Temperature (VREF)Figure 13. Output Voltage Change vs Load Current (VBIAS) Figure 15. Load Regulation Sourcing vs Temperature (VBIAS) Figure 16. Load Regulation Sinking vs Temperature (VREF) Figure 17. Load Regulation Sinking vs Temperature (VBIAS) Figure 18. Line Regulation vs Temperature (VREF)
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2 V/div
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted. Figure 25. Load Transient Response Figure 26. Load Transient Response Figure 27. Load Transient Response Figure 28. Minimum Dropout Voltage vs Load Current Figure 29. Turn-On Settling Time Figure 30. Turn-On Settling Time
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At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted. Figure 37. Output Impedance vs Frequency (VBIAS) Figure 38. Thermal Hysteresis Distribution (VREF) Figure 39. Thermal Hysteresis Distribution (VBIAS)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
board thickness is 1.57 mm and the area is 171.54 mm × 165.1 mm. its exposure to thermal stress. Figure 40. Reflow Profile Figure 42. Solder Heat Shift Distribution, VBIAS (%)Figure 41. Solder Heat Shift Distribution, VREF (%)
8.2 Thermal Hysteresis
- VHYST = thermal hysteresis (in units of ppm),
- VNOM = the specified output voltage,
- VPRE = output voltage measured at 25°C pre-temperature cycling, and
- VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature range of –40°C to 125°C and returns to 25°C. (1) Typical thermal hysteresis distribution is as shown in Figure 43 and Figure 44.
Figure 43. Thermal Hysteresis Distribution (VREF) Figure 44. Thermal Hysteresis Distribution (VBIAS)
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0.1 Hz to 10 Hz Filter
8.3 Noise Performance
noise measurement setup is shown in Figure 47. Figure 45. 0.1-Hz to 10-Hz Noise (VREF) Figure 46. 0.1-Hz to 10-Hz Noise (VBIAS) Figure 47. 0.1-Hz to 10-Hz Noise Measurement Setup
/c87DIFF REF BIASV V 2 V/c20 /c10 DIFF(MAX) DIFF (MIN) 6 REF V V Tracking Error 10 (ppm)V Temperature Range /c10/ca7 /cb7 /c20 /c78 /ca8 /cb8 /c78/ca9 /cb9 e-Trim e-Trim VREF VBIAS R 3 R 4 R 1 R 2 Q 1 Q 2 VBE1 VBE2 - - + + R 5 R 7R 6 REF2025,REF2030,REF2033,REF2041 SBOS600B –MAY 2014–REVISED JULY 2014 www.ti.com
9 Detailed Description
9.1 Overview
The REF20xx are a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The Functional Block Diagram section provides a block diagram of the basic band-gap topology and the two buffers used to derive the VREF and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of Q2. The difference of the two base emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2, which has a negative temperature coefficient. The resulting band-gap output voltage is almost independent of temperature. Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The resistors R1, R2 and R3, R4 are sized such that VBIAS = VREF / 2. e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and VBIAS, implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is implemented in the REF20xx to minimize the temperature drift and maximize the initial accuracy of both the VREF and VBIAS outputs.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 VREF and VBIAS Tracking
Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter (ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF20xx are generated from the same band-gap voltage as shown in the Functional Block Diagram section. Hence, both outputs track each other over the full temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (max). The tracking accuracy increases to 6 ppm/°C (max) when the temperature range is limited to –40°C to 85°C. The tracking error is calculated using the box method, as described by Equation 2: where
- (2)
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Product Folder Links: REF2025 REF2030 REF2033 REF2041
The tracking accuracy is as shown in Figure 48. Figure 48. VREF and VBIAS Tracking vs Temperature
9.3.2 Low Temperature Drift
9.3.3 Load Current
- TJ = junction temperature (°C),
- TA = ambient temperature (°C),
- PD = power dissipated (W), and
- RθJA = junction-to-ambient thermal resistance (°C/W) (4) The REF20xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.4 Device Functional Modes
mode for normal operation. The REF20xx can be placed in a low-power mode by pulling the ENABLE pin low.
10 Applications and Implementation
10.1 Application Information
supply and reference voltages are supplied by the low-drift REF2030.
10.2 Typical Application
10.2.1 Low-Side, Current-Sensing Application
Figure 49. Low-Side, Current-Sensing Application
10.2.1.1 Design Requirements
- Maximum shunt voltage: ±25 mV
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10.2.1.2 Detailed Design Procedure
design procedure, refer to TIDU357. Figure 50. Low-Drift, Low-side, Bidirectional, Current-Sensing Circuit Topology
10.2.1.2.1 Shunt Resistor
can be used to calculate the maximum value of RSHUNT. resistance is calculated as shown in Equation 7. resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used.
10.2.1.2.2 Differential Amplifier
- Low initial input offset voltage (VOS),
- Low-side sensing (input common-mode range below ground).
INA213B specifications can be found in the INA213 product data sheet. Figure 51. INA21x Current-Shunt Monitor Topology amplifiers use external resistors that are not conducive to low-drift applications.
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10.2.1.2.3 Voltage Reference
- Dual output (3.0 V and 1.5 V),
- Low tracking errors between the two outputs.
across temperature, as shown in Figure 52 and Figure 53. Figure 53. Distribution of VREF – 2 × VBIAS Drift TrackingFigure 52. VREF – 2 × VBIAS Distribution (At TA = 25°C)
10.2.1.2.4 Results
Table 1 summarizes the measured results. Table 1. Measured Results
10.2.1.3 Application Curves
measurement procedure, calibration, and calculations, please refer to TIDU357. Figure 54. Measured Transfer Function Figure 55. Uncalibrated Error vs Load Current Figure 56. Calibrated Error vs Load Current
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11 Power-Supply Recommendations
Figure 57. Dropout Voltage vs Load Current
12 Layout
12.1 Layout Guidelines
- Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030.
- Decouple other active devices in the system per the device specifications.
- Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
- Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Figure 58. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
- INA213 Data Sheet, SBOS437
- Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design, TIDU357
13.2 Related Links
resources, tools and software, and quick access to sample or buy. Table 2. Related Links
13.3 Trademarks
e-Trim is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 1-Aug-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF2025AIDDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GACM REF2025AIDDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GACM REF2030AIDDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GADM REF2030AIDDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GADM REF2033AIDDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEM REF2033AIDDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEM REF2041AIDDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFM REF2041AIDDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 1-Aug-2014 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF2025AIDDCR SOT DDC 5 3000 195.0 200.0 45.0 REF2025AIDDCT SOT DDC 5 250 195.0 200.0 45.0 REF2030AIDDCR SOT DDC 5 3000 195.0 200.0 45.0 REF2030AIDDCT SOT DDC 5 250 195.0 200.0 45.0 REF2033AIDDCR SOT DDC 5 3000 195.0 200.0 45.0 REF2033AIDDCT SOT DDC 5 250 195.0 200.0 45.0 REF2041AIDDCR SOT DDC 5 3000 195.0 200.0 45.0 REF2041AIDDCT SOT DDC 5 250 195.0 200.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2015 Pack Materials-Page 2
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