REF200 TI1 | Alldatasheet
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I High I High Substrate Mirror In I Low I Low Mirror Out Mirror Common 1 2 1 2 8 7 6 5 1 2 3 4 100µA 100µA Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design REF200 SBVS020B –SEPTEMBER 2000–REVISED JULY 2015 REF200DualCurrentSourceandCurrentSink
1 Features 3 Description
The REF200 combines three circuit building-blocks 1• Completely Floating: No Power Supply or Ground on a single monolithic chip: two 100-µA currentConnections sources and a current mirror. The sections are• High Accuracy: 100 µA ±0.5% dielectrically isolated, making them completely
- Low Temperature Coefficient: ±25 ppm/°C independent. Also, because the current sources are two-terminal devices, they can be used equally well• Wide Voltage Compliance: 2.5 V to 40 V as current sinks. The performance of each section is• Includes Current Mirror individually measured and laser-trimmed to achieve high accuracy at low cost.2 Applications The sections can be pin-strapped for currents of 50• Sensor Excitation µA, 100 µA, 200 µA, 300 µA, or 400 µA. External
- Biasing Circuitry circuitry can obtain virtually any current. These and many other circuit techniques are shown in the• Offsetting Current Loops Application Information section of this data sheet.• Low Voltage References The REF200 is available in an SOIC package.• Charge-pump Circuitry
- Hybrid Microcircuits Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) REF200 SOIC (8) 3.91 mm × 4.90 mm (1) For all available packages, see the package addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SBVS020B –SEPTEMBER 2000–REVISED JULY 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2015) to Revision B Page Changes from Original (September 2000) to Revision A Page
- Added ESD Ratings and Recommended Operating Conditions tables, and Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation
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Product Folder Links: REF200
I I Substrate Mirror Input Low Low Mirror Common Mirror Output High High I I REF200 www.ti.com SBVS020B –SEPTEMBER 2000–REVISED JULY 2015
5 Pin Configuration and Functions
DESCRIPTION
NAME NO. I1 Low 1 Current source 1 low terminal I2 Low 2 Current source 2 low terminal Mirror Common 3 Current mirror common terminal Mirror Output 4 Current mirror output terminal Mirror Input 5 Current mirror input terminal Substrate 6 Substrate (Usually connected to most negative potential in the system) I2 High 7 Current source 2 high terminal I1 High 8 Current source 1 high terminal Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: REF200
SBVS020B –SEPTEMBER 2000–REVISED JULY 2015 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Applied voltage –6 40 V Reverse current –350 µA Voltage between any two sections ±80 V Operating temperature –40 85 °C Tstg Storage temperature –40 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(1) ±750 V (1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCOMP Compliance voltage 2.5 40 V TA Specified temperature range –25 85 °C
6.4 Electrical Characteristics
at TA = 25°C, VS = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT SOURCES Current accuracy ±0.25% ±1% Current match ±0.25% ±1% Temperature drift Specified temperature range 25 ppm/°C
2.5 V to 40 V 20 100
Output impedance MΩ
3.5 V to 30 V 200 500
BW = 0.1 Hz to 10 Hz 1 nAp-p Noise f = 10 kHz 20 pA/√Hz Voltage compliance (1%) TMIN to TMAX See Typical Characteristics Capacitance 10 pF CURRENT MIRROR – I = 100 µA unless otherwise noted Gain 0.995 1 1.005 Temperature drift 25 ppm/°C Impedance (output) 2 V to 40 V 40 100 MΩ Nonlinearity I = 0 µA to 250 µA 0.05% Input voltage 1.4 V Output compliance voltage See Typical Characteristics Frequency response (–3 dB) Transfer 5 MHz
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Product Folder Links: REF200
6.5 Typical Characteristics
Figure 1. Current Source Typical Drift vs Temperature Figure 2. Current Source Temperature Drift Distribution Figure 4. Current Source Output Current vs VoltageFigure 3. Current Source Output Current vs Voltage Figure 6. Current Source Reverse Current vs ReverseFigure 5. Current Source Current Noise (0.1 Hz to 10 Hz)
Figure 8. Mirror Transfer NonlinearityFigure 7. Mirror Gain Error vs Current Figure 9. Mirror Input Voltage and Output Compliance Voltage vs Current
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I High I High Substrate Mirror In I Low I Low Mirror Out Mirror Common 1 2 1 2 8 7 6 5 1 2 3 4 100µA 100µA REF200 www.ti.com SBVS020B –SEPTEMBER 2000–REVISED JULY 2015
7 Detailed Description
7.1 Overview
The REF200 device combines three circuit building-blocks on a single monolithic chip— two 100-µA current sources and a current mirror. The sections are dielectrically isolated, making them completely independent. Also, because the current sources are two terminal devices, they can be used equally well as current sinks. The performance of each section is individually measured and laser-trimmed to achieve high accuracy at low cost.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Temperature Drift
Drift performance is specified by the box method, as illustrated in Figure 1. The upper and lower current extremes measured over temperature define the top and bottom of the box. The sides are determined by the specified temperature range of the device. The drift of the unit is the slope of the diagonal, typically 25 ppm/°C from –25°C to +85°C. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: REF200
7.4 Device Functional Modes
Figure 10. Simplified Circuit Diagram
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3 Wire
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
configuration, however, reduces the compliance voltage range by one diode drop.
8.2 Typical Application
the signal. The design also uses a 3-wire RTD configuration to minimize errors due to wiring resistance. Figure 11. RTD Resistance to Voltage Converter Schematic
8.2.1 Design Requirements
- Supply Voltage: 5 V
- RTD temperature range: –50°C to +125°C
- RTD resistance range 80.3 Ω to 147.9 Ω
- Output: 0.1 V to 4.9 V The design goals and performance are summarized in Table 1. Figure 15 depicts the measured transfer function of the design.
Table 1. Comparison of Design Goals, Calculations, Simulation, and Measured Performance
8.2.2 Detailed Design Procedure
Figure 12 and Figure 13 shows the schematic of the RTD amplifier for minimum and maximum output conditions. Reference Design Using Instrumentation Amplifier and Current Reference (TIDU969). Figure 12. RTD Amplifier with Minimum Output Condition
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Figure 13. RTD Amplifier with Maximum Output Condition
8.2.2.1 Lead Resistance Cancelation (3-Wire RTD)
input is only from the RTD voltage. In this example, the RTD drop is 14.8 mV and the leads each have 1 mV. Figure 14. 3-Wire RTD Configuration Cancels Lead Resistance
8.2.3 Application Curves
Figure 16. Measured Error vs RTD ResistanceFigure 15. RTD to Vout Transfer Function
8.3 System Examples
Figure 17. Reverse Voltage Protection Figure 18. 50-µA Current Source
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also provides improved PSRR. (2) For current sinks (Circuits (a) and (b) only), invert circuits and use “N” channel JFETS. Figure 23. FET Cascode Circuits
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Figure 24. Operational Amplifier Offset Adjustment Circuits
(1) Zero volts shunt compliance. allow swing to zero volts from rail. Figure 25. Adjustable Current Sources
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2 Vp-p
Figure 26. RTD Excitation With Three-Wire Lead Resistance Compensation Figure 27. Precision Triangle Waveform Generator
12 Vp-p
Figure 28. Precision Duty-Cycle Modulator Figure 29. Low Noise Current Sink
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4 V to 30 V
100 A μ
current is included in the 25 mA. Figure 32. Rate Limiter Figure 33. 25-mA Floating Current Source
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Figure 34. Dead-Band Circuit
Figure 35. Double Dead-Band Circuit Figure 36. Low-Voltage Reference
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NOTES: (1) Capacitors optional to reduce noise and switching time. (2) Programs center of threshold voltage. (3) Programs window voltage. Figure 40. Window Comparator Figure 41. Instrumentation Amplifier With Compliance to –VS
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9 Power Supply Recommendations
compliance voltage range from 2.5 V to 40 V.
10 Layout
10.1 Layout Guidelines
- Minimize trace lengths in the current source and current mirror paths to reduce impedance.
- Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.
10.2 Layout Example
Figure 42. Example Layout of REF200 in a RTD Measurement System
SBVS020B –SEPTEMBER 2000–REVISED JULY 2015 www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
- RTD to Voltage Reference Design Using Instrumentation Amplifier and Current Reference, TIDU969
- Implementation and Applications of Current Sources and Current Receivers, SBOA046
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: REF200
www.ti.com 23-Jul-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples REF200AP OBSOLETE PDIP P 8 TBD Call TI Call TI REF200AU ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 REF 200U REF200AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 REF 200U REF200AU/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 REF 200U REF200AUE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 REF 200U REF200AUG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 REF 200U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 23-Jul-2015 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF200AU/2K5 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2015 Pack Materials-Page 2
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