REF-03 AD | Alldatasheet

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FEATURES GENERAL DESCRIPTION © Low Cost dips and surface-mountable small outline plastic packages. For © Available in Die Form improved performance or -55°C/125°C operation, see the REF-43 data sheet. ORDERING INFORMATION+ OPERATING PIN CONNECTIONS TEMPERATURE PLASTIC PACKAGE RANGE RErOsGP XIN ne. Of Le}nc. 8-PIN PLASTIC DIP REFO3GStt XIND. Vw 2] [7] ne. (P-Suffix) Vrewe (3 ay 8-PIN SO +t Burn-inis available on commercial and industrial temperature range parts in = ‘our plastic DIP. rouno [4] [erm (S-Suttix) tt For availability and burn-in information on SO and PLCC packages, contact your local sales office SIMPLIFIED SCHEMATIC - o INPUT L = . ore ; ROUND REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its Use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 otherwise under any patent or patent rights of Analog Devices Telex: 924491 Cable: ANALOG NORWOODMASS

ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE TYPE ©), (NOTE 2) %\\ UNITS Supply Voltage ss enenrnnennonnnnnis $40V GenpacoP Res uutput Short-Circuit Duration ....seorsnsecnsnnnnnene ‘epnso®) 8a Operating Temperature Range SS iéi<iaS REF-03G (P,S) o.sccssccsssssssessssseessssssessssseesee “40°C to 485°C. NOTES ‘| 1y to both DICE and packaged parts. un Junction Temperature Range sessssssnsnseerecsseses O5°C tO +175°C 2. @,, 8 specified for worst case mounting conditions, i.e., 6, is specified for printed circuit board for SO package. ELECTRICAL CHARACTERISTICS at Vin = +15V, ~40°C < Ta = +85°C, unless otherwise noted. aS REF-03G PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Voltage vo ___No Load 2.485 2.500 2515 v Output Voltage Tolerance No Load - 02 06 % Output Voltage e Temperature Coefficient TCVo (Note 1) ~ iad so Pem/*C Line Regulation * Vin = +4.5V to +33V a: 2A _ 0.002 0.005 %/V Load Regulation 1, =0mA to 10mA 100mm - 0.008 0.010 9/mA Load Current (Sourcing) in 10 a - mA Load Current (Sinking) Is -03 -05 - ma Short-Gircuit Output Current_lec Output ShortedtoGround 2 = ma Quiescent Supply Current Isy No Load - 10 14 mA Turn-On Settling Time ton To +0.1% of Final Value - 5 = as Output Voltage Noise enpp O.1Hz to 10Hz - 6 - Mop Output Adjustment Range Vir Rpor = 10ki +6 2 — % Input Voltage Range 45 6 33 v Temperature Voltage Output Vy (Note 2) = 620 = mv NOTES: 1. TCVo is measured by the endpoint method, 2. Limit current in or out of pin 3 to SOnA and capacitance on pin 3 to 30pF- (85°C) - v(-40°C) and is equal to ean em | in ppm/°C. BURN-IN CIRCUIT OUTPUT VOLTAGE TRIM METHOD “ev v- S sour vin

1011 Vour [© OVour

2 TAM

[=> | ono voxs, G + cca “wo -2- REV. C

Poa lc 3. Vrew lp en 4. GROUND maga Or 5. TRIM [a le ES . co DIE SIZE 0.048 x 0.074 inch, 3552 sq. mils (1.22 X 1.88 mm, 2.29 sq. mm) WAFER TEST LIMITS at Vin = +15V, Ta = 25°C. REF-03G PARAMETER SYMBOL CONDITIONS _ ‘LIMIT _ UNITS: Output Voltage Tolerance Vo L=0 2.600 +0 oe mM ae Line Regulation Viy= +4.8V to +33V cone Pemiv Waa Output Adjust Range Veni Rp= 10k. +6 % MIN Quiescent Supply Current ley No Load 14 mA MAX NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. TYPICAL PERFORMANCE CHARACTERISTICS LOAD REGULATION MAXIMUM LOAD CURRENT (Al, = 10mA) LINE REGULATION vs INPUT VOLTAGE vs INPUT VOLTAGE vs INPUT VOLTAGE 30 6s 20 TT Fs 8 3 H : 2 é 3 A ee i. 3 3 3 w « ° >a ssa we a Baa rr a a oe ee Ree pur voLTAGE (voLTs) INPUT VOLTAGE (voLTs) INPUT VOLTAGE (VOLTS) REV. C -3-

TYPICAL PERFORMANCE CHARACTERISTICS NORMALIZED | LINE REGULATION MAXIMUM LOAD CURRENT (4.5V TO 33V) QUIESCENT CURRENT vs TEMPERATURE vs TEMPERATURE vs TEMPERATURE . eee eg titi tty 7 a s WIDEBAND OUTPUT NOISE NORMALIZED LOAD vs BANDWIDTH LINE REGULATION REGULATION (Al, = 10mA) (0.1Hz TO FREQUENCY vs FREQUENCY vs TEMPERATURE INDICATED) an ngs Pe tt} Sir SE Se at ill | iN || lil s bu | | | Cone Pha Ntras CTC Cr) 3 ba Nel 38 ra 2 Eee 5 ll | i INGA B gw 8 Fd y s 8 5 ihe able . Mam 8, AttHH ag . a a a JCOUCE T TYPICAL DISTRIBUTION TYPICAL DISTRIBUTION OF OUTPUT OF OUTPUT VOLTAGE NOISE VOLTAGE TEMPCO ee) = erp LTT TAT TT LTT TAL TT Lt Tv LT INE TT [| | PIN TT PT Ty | [| TAT ATT PAT A [| Vi TIN | PALIN Tf LY TIN | [7 T TN | -4- REV. C

APPLICATIONS INFORMATION FIGURE 2: Adjustable Bipolar Reference The REF-03 provides a stable + 2.5V output voltage with min- imal dependence on load current, line voltage or tempera- S ture. This voltage is typically used to set an absolute refer- ence point in data conversion circuits, or in analog circuits such as log amps, 4-20mA transmitters and power supplies. 5, The REF-03 is of particular value in systems requiring a m re precision reference using a single + 5V supply rail. REF-03 Vout 7 Because an onboard operational amplifier is used to amplify ono Sto Ne oo cay the basic bandgap cell voltage to 2.5V, supply decoupling is a soKnt x g critical to the transient performance of a voltage reference. The supply line should be bypassed with a 10uF tantalum = = 0 capacitor in parallel with a 0.01uF to 0.1uF ceramic capacitor . for best results as shown in Figure 1. For less critical condi- tions, a single 0.14F capacitor is adequate. The bypass capacitors should be located as close to the reference as FIGURE 3: +2.5V Reference possible. Inadequate bypassing can lead to instabilities. Output bypass capacitors are not generally recommended. If ° necessary for high-frequency output impedance reduction, the capacitance value used should be at least 1uF | Vin FIGURE 1: Basic Connections O-25v GN wor 9 = 00k | So ay J = 2 ‘4 Vin — - GN a = FIGURE 4: -2.5V Reference oy GENERATING AN ADJUSTABLE BIPOLAR ake VOLTAGE REFERENCE Many times, there is a requirement for an adjustable bipolar . reference. A simple method of generating such a reference is ro to connect the output of the REF-03 to an op amp in an . adjustable gain configuration as shown in Figure 2. The trim- REF-03 Your able resistor is then used to generate the desired output GNo = voltage from -2.5V to +2.5V. oy aS GENERATING A -2.5V REFERENCE 2N2905. O-28v Often, there is a requirement for a negative reference voltage. The simplest method of generating a—2.5V reference with the REF-03 is to connect an op amp in a gain of —1 to the output, as shown in Figure 3. This provides both positive and nega- tive 2.5V references. Figure 4 shows another method of obtaining a negative reference, in which the current-output 6 element is a PNP transistor, with the REF-03 in aservo loop to ia ensure that the output remains 2.5V below ground. REV. C -5-

BOOST TRANSISTOR PROVIDES HIGH FIGURE 5: Output Current Boost OUTPUT CURRENT When applications require more than 10mA current delivery, an external boost transistor may be added to the REF-03 to S So pass the required current without dissipating excessive power within the IC. The maximum current output to the system is bounded only by the capabilities of the boost tran- ws Re sistor. This technique is shown in Figure 5 with and without a son current limiting. Current limiting may be used to prevent damage to the boost transistor. In Figure 5b, the limit occurs 2N2905 -2N2305 when the voltage dropped across R2 exceeds one Vege (0.6V). Te vw The current limit is sensitive to the variations of the diodes’ forward drop and the PNP’s Vge_ with temperature, and will REF-03 Your O +25v REF-03 Your} OFF coma decrease with increasing temperature. GND GND CMOS DAC REFERENCE = sana m | sana The REF-03 makes an excellent reference for use with CMOS and bipolar DACs. Figure 6 shows the REF-03 connected to the DAC-8012, a 12-bit parallel loading CMOS DAC with i + memory. With an OP-43 output amplifier for fast settling, the ~ ~ circuit requires less than 3mA when driven from TTL gates, a. No Current Limit b. Current Limiting and less than 2mA when driven from CMOS gates. In situa- tions not requiring the higher speed of the OP-43, enhanced linearity and some savings in power dissipation can be real- ized using an OP-97 for the output amplifier. Figure 7 shows a typical multiplying DAC application using a REF-03 reference. FIGURE 6: CMOS DAC Reference “sv Vw 1011 F Kial | a = Veer Yoo Are - our z acno £2 2 d en Bo sel | a] 16 b oiciTaL = INPUT *OP AMP IS OP-43 IF HIGHER SPEED AND FASTER SETTLING IS REQUIRED. P-97 IF LOWER SPEED ANO HIGHER LINEARITY IS REQUIRED. -6- REV. C

FIGURE 7: Multiplying CMOS DAC Reference ow ‘oo V +25V, OVour< Viv < 425Vp Your our ° Veer V2. 0AC-8228" av 6.8K0 ° Ve, ono "© V Yin Vv +25 REF-03 Your 6.Kn uF | ano Vv i Vv Vour = ~B/256 x Vy WITH RESPECT TO VIRTUAL ZERO. “DIGITAL INTERFACING OMITTED FOR CLARITY. REV. C -7-

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