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© Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Semiconductor Data Sheet MC3PHAC Rev. 2, 7/2005 MC3PHAC Monolithic Intelligent Motor Controller Overview The MC3PHAC is a high-performance monolithic intelligent motor controller designed specifically to meet the requirements for low-cost, variable-speed, 3-phase ac motor control systems. The device is adaptable and configurable, based on its environment. It contains all of the active functions required to implement the control portion of an open loop, 3-phase ac motor drive. One of the unique aspects of this device is that although it is adaptable and configurable based on its environment, it does not require any software development. This makes the MC3PHAC a perfect fit for customer applications requiring ac motor control but with limited or no software resources available. The device features are:

• Volts-per-Hertz speed control  Digital signal processing (DSP) filtering to enhance speed stability  32-bit calculations for high-precision operation  Internet enabled  No user software development required for operation  6-output pulse-width modulator (PWM)  3-phase waveform generation  4-channel analog-to-digital converter (ADC)  User configurable for standalone or hosted operation  Dynamic bus ripple cancellation  Selectable PWM polarity and frequency  Selectable 50/60 Hz base frequency  Phase-lock loop (PLL) based system oscillator  Serial communications interface (SCI)  Low-power supply voltage detection circuit Included in the MC3PHAC are protective features consisting of dc bus voltage monitoring and a system fault input that will immediately disable the PWM module upon detection of a system fault.

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Figure 1. MC3PHAC-Based Motor Control System Table 1. Ordering Information

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

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Electrical Characteristics

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIn and VOut be constrained to the range VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD). Functional Operating Range Control Timing Characteristic(1) 1. Voltages referenced to VSS Symbol Value Unit Supply voltage V DD –0.3 to +6.0 V Input voltage V In –0.3 to VDD +0.3 V Input high voltage V Hi VDD + 0.3 V Maximum current per pin excluding VDD and VSS I± 2 5 m A Storage temperature T stg –55 to +150 °C Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA Characteristic Symbol Value Unit Operating temperature range (see Table 1) TA –40°C to +105°C °C Operating voltage range VDD 5.0 ± 10% V Characteristic Symbol Value Unit Oscillator frequency(1) 1. Follow the crystal/resonator manufacturer’s recommendations, as the crystal/resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. Fosc 4.00 ± 1% MHz

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 5 Characteristic(1) 1. VDD = 5.0 Vdc ± 10% Symbol Min Max Unit Output high voltage (ILoad = –2.0 mA) All I/O pins except RBRAKE VOH VDD –0.8 — V Output high voltage RBRAKE (IRBRAKE = –15.0 mA) VOHRB VDD –1.0 — V Output low voltage (ILoad = 1.6 mA) All I/O pins except FAULTOUT and RETRY/TxD VOL — 0.4 V Output low voltage (ILoad = 15 mA) FAULTOUT and RETRY/TxD VOL1 — 1.0 V Input high voltage All ports VHi 0.7 x VDD VDD V Input low voltage All ports VIL VSS 0.3 x VDD V VDD supply current IDD — 60 mA I/O ports high-impedance leakage current IIL — ± 5 µA Input current IIn — ± 1 µA Capacitance Ports (as input or output) COut CIn 8 pF VDD low-voltage inhibit reset VLVR1 3.80 4.3 V VDD low-voltage reset/recovery hysteresis VLVH1 50 150 mV VDD power-on reset re-arm voltage VPOR 3.85 4.45 V VDD power-on reset rise time ramp rate RPOR 0.035 — V/ms Serial communications interface baud rate SCIBD 9504 9696 Bits/sec Voltage Boost(2) 2. Limited in standalone mode to 0 to 35% VBoost 0 100 % Dead time range(3) 3. Limited in standalone mode to 0.5 to 6.0 µs DTRange 0 31.875 µs Retry time(4) 4. Limited in standalone mode to 0 to ~53 seconds RTTime 0 4.55 Hours Acceleration rate ACRate 0.5 128 Hz/sec Speed control SPEED 1 128 Hz PWM Frequency PWMFREQ 5.291 21.164 kHz High side power transistor drive pump-up time TPump 99 101 ms

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28-pin packages (see Figure 2). Table 2. MC3PHAC Pin Descriptions (Sheet 1 of 2) performance, this pin should be tied to VDDA (analog).

2 RESET

8 PWMPOL_BASEFREQ Input which is sampled at specific moments during initialization to

9 PWM_U_TOP PWM output signal for the top transistor driving motor phase U

10 PWM_U_BOT PWM output signal for the bottom transistor driving motor phase U

11 PWM_V_TOP PWM output signal for the top transistor driving motor phase V

12 PWM_V_BOT PWM output signal for the bottom transistor driving motor phase V

13 PWM_W_TOP PWM output signal for the top transistor driving motor phase W

14 PWM_W_BOT PWM output signal for the bottom transistor driving motor phase W

15 FAULTIN

16 PWMFREQ_RxD

input which receives UART serial data.

17 RETRY_TxD

software mode, this pin is an output that transmits UART serial data.

18 RBRAKE

prevent excess capacitor voltage.

19 DT_FAULTOUT

which goes low whenever a fault condition occurs.

20 VBOOST_MODE

specify the amount of voltage boost to apply to the motor.

22 V SS Digital power supply ground return for the MC3PHAC

23 FWD Input which is sampled to determine whether the motor should rotate in

24 START Input which is sampled to determine whether the motor should be

25 MUX_IN

26 SPEED

steady-state speed of the motor.

27 ACCEL

28 DC_BUS

1. Correct timing of the MC3PHAC is based on a 4.00 MHz crystal or ceramic resonator. Follow the crystal/resonator

Table 2. MC3PHAC Pin Descriptions (Sheet 2 of 2)

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

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The MC3PHAC is a high-performance intelligent controller designed specifically to meet the requirements for low-cost, variable-speed, 3-phase ac motor control systems. The device is adaptable and configurable, based on its environment. Constructed with high-speed CMOS (complementary metal- oxide semiconductor) technology, the MC3PHAC offers a high degree of performance and ruggedness in the hostile environments often found in motor control systems. The device consists of:  6-output pulse-width modulator (PWM)  4-channel analog-to-digital converter (ADC)  Phase-lock loop (PLL) based system oscillator  Low-power supply voltage detection circuit  Serial communications interface (SCI) The serial communications interface is used in a mode, called PC master software mode, whereby control of the MC3PHAC is from a host or master personal computer executing PC master software or a microcontroller emulating PC master software commands. In either case, control via the internet is feasible. Included in the MC3PHAC are protective features consisting of dc bus monitoring and a system fault input that will immediately disable the PWM module upon detection of a system fault. Included motor control features include:  Open loop volts/Hertz speed control  Forward or reverse rotation  Start/stop motion  System fault input  Low-speed voltage boost  Internal power-on reset (POR)

Features

3-Phase Waveform Generation — The MC3PHAC generates six PWM signals which have been modulated with variable voltage and variable frequency information in order to control a 3-phase ac motor. A third harmonic signal has been superimposed on top of the fundamental motor frequency to achieve full bus voltage utilization. This results in a 15 percent increase in maximum output amplitude compared to pure sine wave modulation. The waveform is updated at a 5.3 kHz rate (except when the PWM frequency is 15.9 kHz), resulting in near continuous waveform quality. At 15.9 kHz, the waveform is updated at 4.0 kHz. DSP Filtering — A 24-bit IIR digital filter is used on the SPEED input signal in standalone mode, resulting in enhanced speed stability in noisy environments. The sampling period of the filter is 3 ms (except when the PWM frequency is 15.9 kHz) and it mimics the response of a single pole analog filter having a pole at

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 9 High Precision Calculations — Up to 32-bit variable resolution is employed for precision control and smooth performance. For example, the motor speed can be controlled with a resolution of 4 mHz. Smooth Voltage Transitions — When the commanded speed of the motor passes through ±1 Hz, the voltage is gently applied or removed depending on the direction of the speed change. This eliminates any pops or surges that may occur, especially under conditions of high-voltage boost at low frequencies. High-Side Bootstrapping — Many motor drive topologies (especially high-voltage drives) use optocouplers to supply the PWM signal to the high-side transistors. Often, the high-side transistor drive circuitry contains a charge pump circuit to create a floating power supply for each high-side transistor that is dependent on low-side PWMs to develop power. When the motor has been off for a period of time, the charge on the high-side power supply capacitor is depleted and must be replenished before proper PWM operation can resume. To accommodate such topologies, the MC3PHAC will always provide 100 ms of 50 percent PWM drive to only the low-side transistors each time the motor is turned on. Since the top transistors remain off during this time, it has the effect of applying zero volts to the motor, and no motion occurs. After this period, motor waveform modulation begins, with PWM drive also being applied to the high-side transistors. Fast Velocity Updating — During periods when the motor speed is changing, the rate at which the velocity is updated is critical to smooth operation. If these updates occur too infrequently, a ratcheting effect will be exhibited on the motor, which inhibits smooth torque performance. However, velocity profiling is a very calculation intensive operation to perform, which runs contrary to the previous requirement. In the MC3PHAC, a velocity pipelining technique is employed which allows linear interpolation of the velocity values, resulting in a new velocity value every 189 µs (252 µs for 15.9 kHz PWMs). The net result is ultra smooth velocity transitions, where each velocity step is not perceivable by the motor. Dynamic Bus Ripple Cancellation — The dc bus voltage is sensed by the MC3PHAC, and any deviations from a predetermined norm (3.5 V on the dc bus input pin) result in corrections to the PWM values to counteract the effect of the bus voltage changes on the motor current. The frequency of this calculation is sufficiently high to permit compensation for line frequency ripple, as well as slower bus voltage changes resulting from regeneration or brown out conditions. See Figure 4. Selectable Base Frequency — Alternating current (ac) motors are designed to accept rated voltage at either 50 or 60 Hz, depending on what region of the world they were designed to be used. The MC3PHAC can accommodate both types of motors by allowing the voltage profile to reach maximum value at either 50 or 60 Hz. This parameter can be specified at initialization in standalone mode, or it can be changed at any time in PC master software mode. Selectable PWM Polarity — The polarity of the PWM outputs may be specified such that a logic high on a PWM output can either be the asserted or negated state of the signal. In standalone mode, this parameter is specified at initialization and applies to all six PWM outputs. In PC master software mode, the polarity of the top PWM signals can be specified separately from the polarity of the bottom PWM signals. This specification can be done at any time, but once it is done, the polarities are locked and cannot be changed until a reset occurs. Also, any commands from PC master software that would have the effect of enabling PWMs are prevented by the MC3PHAC until the polarity has been specified.

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

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Figure 4. Dynamic Bus Ripple Cancellation initialization by connecting either pin 25, 26, 27, or 28 exclusively to the PWMPOL_BASEFREQ input. connected to the PWMPOL_BASEFREQ input. Table 3. PWM Polarity and Base Frequency Specification in Standalone Mode

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 11 Selectable PWM Frequency — The MC3PHAC accommodates four discrete PWM frequencies and can be changed dynamically while the motor is running. This resistor can be a potentiometer or a fixed resistor in the range shown in Table 4. In standalone mode, the PWM frequency is specified by applying a voltage to the MUX_IN pin while the PWMFREQ_RxD pin is being driven low. Table 4 shows the required voltage levels on the MUX_IN pin and the associated PWM frequency for each voltage range. NOTE The PWM frequencies are based on a 4.00 MHz frequency applied to the oscillator input. Selectable PWM Dead Time — Besides being able to specify the PWM frequency, the blanking time interval between the on states of the complementary PWM pairs can also be specified. Refer to the graph in Figure 9 for the resistance value versus dead time. Figure 9 assumes a 6.8 kΩ ±5% pullup resistor. In standalone mode, this is done by supplying a voltage to the MUX_IN pin while the DT_FAULTOUT pin is being driven low. In this way, dead time can be specified with a scaling factor of 2.075 µs per volt, with a minimum value of 0.5 µs. In PC master software mode, this value can be selected to be anywhere between 0 and 32 µs. In both standalone and PC master software modes, the dead time value can be written only once. Further updates of this parameter are locked out until a reset condition occurs. Speed Control — The synchronous motor frequency can be specified in real time to be any value from 1 Hz to 128 Hz by the voltage applied to the SPEED pin. The scaling factor is 25.6 Hz per volt. This parameter can also be controlled directly from PC master software in real time. The SPEED pin is processed by a 24-bit digital filter to enhance the speed stability in noisy environments. This filter is only activated in standalone mode. Acceleration Control — Motor acceleration can be specified in real time to be in the range from 0.5 Hz/second, ranging to 128 Hz/second, by the voltage applied to the ACCEL pin. The scaling factor is 25.6 Hz/second per volt. This parameter can also be controlled directly from PC master software in real time. Voltage Profile Generation — The MC3PHAC controls the motor voltage in proportion to the specified frequency, as indicated in Figure 5. An ac motor is designed to draw a specified amount of magnetizing current when supplied with rated voltage at the base frequency. As the frequency decreases, assuming no stator losses, the voltage must decrease in exact proportion to maintain the required magnetizing current. In reality, as the frequency decreases, the voltage drop in the series stator resistance increases in proportion to the voltage across the magnetizing inductance. This has the effect of further reducing the voltage across the magnetizing inductor, and consequently, the magnetizing current. A schematic representation of this effect is Table 4. MUX_IN Resistance Ranges and Corresponding PWM Frequencies

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

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illustrated in Figure 6. To compensate for this voltage loss, the voltage profile is boosted over the normal voltage curve in Figure 5, so that the magnetizing current remains constant over the speed range. Figure 5. Voltage Profiling, Including Voltage Boost Figure 6. AC Motor Single Phase Model Showing Parasitic Stator Impedances this way, voltage boost can be specified from 0 to 40 percent, with a scaling factor of 8 percent per volt.

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 13 logic, and can cause the device to malfunction. The same noise spike applied to the input of a PLL clock circuit is perceived by the PLL as a change in its reference frequency, and the PLL output frequency begins to change in an attempt to lock on to the new frequency. However, before any appreciable change can occur, the spike is gone, and the PLL settles back into the true reference frequency. Fault Protection — The MC3PHAC supports an elaborate range of fault protection and prevention features. If a fault does occur, the MC3PHAC immediately disables the PWMs and waits until the fault condition is cleared before starting a timer to re-enable the PWMs. Refer to the graph in Figure 10 for the resistance value versus retry time. Figure 10 assumes a 6.8 kΩ pullup resistor. In standalone mode, this timeout interval is specified during the initialization phase by supplying a voltage to the MUX_IN pin while the RETRY_TxD pin is being driven low. In this way, the retry time can be specified from 1 to 60 seconds, with a scaling factor of 12 seconds per volt. In PC master software mode, the retry time can be specified from 0.25 second to over 4.5 hours and can be changed at any time. The fault protection and prevention features are:  External Fault Monitoring — The FAULTIN pin accepts a digital signal that indicates a fault has been detected via external monitoring circuitry. A high level on this input results in the PWMs being immediately disabled. Typical fault conditions might be a dc bus over voltage, bus over current, or over temperature. Once this input returns to a logic low level, the fault retry timer begins running, and PWMs are re-enabled after the programmed timeout value is reached.  Lost Clock Protection — If the signal on the OSC1 pin is lost altogether, the MC3PHAC will immediately disable the PWM outputs to protect the motor and power electronics. This is a special fault condition in that it will also cause the MC3PHAC to be reset. Lost clock detection is an important safety consideration, as many safety regulatory agencies are now requiring a dead crystal test be performed as part of the certification process.  Low V DD Protection — Whenever V DD falls below VLVR1, an on-board power supply monitor will reset the MC3PHAC. This allows the MC3PHAC to operate properly with 5 volt power supplies of either 5 or 10 percent tolerance.  Bus Voltage Integrity Monitoring — The DC_BUS pin is monitored at a 5.3 kHz frequency (4.0 kHz when the PWM frequency is set to 15.9 kHz), and any voltage reading outside of an acceptable window constitutes a fault condition. In standalone mode, the window thresholds are fixed at 4.47 volts (128 percent of nominal), and 1.75 volts (50 percent of nominal), where nominal is defined to be 3.5 volts. In PC master software mode, both top and bottom window thresholds can be set independently to any value between 0 volts (0 percent of nominal), and greater than 5 volts (143 percent of nominal), and can be changed at any time. Once the DC_BUS signal level returns to a value within the acceptable window, the fault retry timer begins running, and PWMs are re- enabled after the programmed timeout value is reached. During power-up, it is possible that V DD could reach operating voltage before the dc bus capacitor charges up to its nominal value. When the dc bus integrity is checked, an under voltage would be detected and treated as a fault, with its associated timeout period. To prevent this, the MC3PHAC monitors the dc bus voltage during power-up in standalone mode, and waits until it is higher than the under voltage threshold before continuing. During this time, all MC3PHAC functions are suspended. Once this threshold is reached, the MC3PHAC will continue normally, with any further under voltage conditions treated as a fault. If dc bus voltage monitoring is not desired, a voltage of 3.5 volts ± 5 percent should be supplied to the DC_BUS pin through an impedance of between 4.7 kΩ and 15 kΩ.

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

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 Regeneration Control — Regeneration is a process by which stored mechanical energy in the motor and load is transferred back into the drive electronics, usually as a result of an aggressive deceleration operation. In special cases where this process occurs frequently (for example, elevator motor control systems), it is economical to incorporate special features in the motor drive to allow this energy to be supplied back to the ac mains. However, for most low cost ac drives, this energy is stored in the dc bus capacitor by increasing its voltage. If this process is left unchecked, the dc bus voltage can rise to dangerous levels, which can destroy the bus capacitor or the transistors in the power inverter. The MC3PHAC incorporates two techniques to deal with regeneration before it becomes a problem: – Resistive Braking — The DC_BUS pin is monitored at a 5.3 kHz frequency (4.0 kHz when the PWM frequency is set to 15.9 kHz), and when the voltage reaches a certain threshold, the RBRAKE pin is driven high. This signal can be used to control a resistive brake placed across the dc bus capacitor, such that mechanical energy from the motor will be dissipated as heat in the resistor versus being stored as voltage on the capacitor. In standalone mode, the DC_BUS threshold required to assert the RBRAKE signal is fixed at 3.85 volts (110 percent of nominal) where nominal is defined to be 3.5 volts. In PC master software mode, this threshold can be set to any value between 0 volts (0 percent of nominal) and greater than 5 volts (143 percent of nominal) and can be changed at any time. – Automatic Deceleration Control — When decelerating the motor, the MC3PHAC attempts to use the specified acceleration value for deceleration as well. If the voltage on the DC_BUS pin reaches a certain threshold, the MC3PHAC begins to moderate the deceleration as a function of this voltage, as shown in Figure 7. The voltage range on the DC_BUS pin from when the deceleration begins to decrease, to when it reaches 0, is 0.62 volts. In standalone mode, the DC_BUS voltage where deceleration begins to decrease is fixed at 3.85 volts (110 percent of nominal) where nominal is defined to be 3.5 volts. In PC master software mode, this threshold can be set to any value between 0 volts (0 percent of nominal) and greater than 5 volts (143 percent of nominal) and can be changed at any time. Figure 7. Deceleration as a Function of Bus Voltage

Digital Power Supply Bypassing MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 15 Digital Power Supply Bypassing VDD and VSS are the digital power supply and ground pins for the MC3PHAC. Fast signal transitions connected internally on these pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the VDD and VSS pins. Place the bypass capacitors as close as possible to the MC3PHAC. Use a high- frequency-response ceramic capacitor, such as a 0.1 µF, paralleled with a bulk capacitor in the range of 1 µF to 10 µF for bypassing the digital power supply. Analog Power Supply Bypassing VDDA and VSSA are the power supply pins for the analog portion of the clock generator and analog-to- digital converter (ADC). On the schematics in this document, analog ground is labeled with an A and other grounds are digital grounds. Analog power is labeled as +5 A. It is good practice to isolate the analog and digital +5 volt power supplies by using a small inductor or a low value resistor less than 5 ohms in series with the digital power supply, to create the +5 A supply. ADC VREF is the power supply pin used for setting the ADC’s voltage reference. Decoupling of these pins should be per the digital power supply bypassing, described previously. ADC VREF (pin 1) and VDDA (pin 3) shall be connected together and connected to the same potential as VDD. Grounding Considerations Printed circuit board layout is an important design consideration. In particular, ground planes and how grounds are tied together influence noise immunity. To maximize noise immunity, it is important to get a good ground plane under the MC3PHAC. It is also important to separate analog and digital grounds. That is why, shown on the schematics, there are two ground designations, analog ground is marked with an A and other grounds are digital grounds. GND is the digital ground plane and power supply return. GNDA is the analog circuit ground. They are both the same reference voltage, but are routed separately, and tie together at only one point. Power-Up/Power-Down When power is applied or removed, it is important that the inverter’s top and bottom output transistors in the same phase are not turned on simultaneously. Since logic states are not always defined during power- up, it is important to ensure that all power transistors remain off when the controller’s supply voltage is below its normal operating level. The MC3PHAC’s PWM module outputs make this easy by switching to a high impedance configuration whenever the 5-volt supply is below its specified minimum. The user should use pullup or pulldown resistors on the output of the MC3PHAC’s PWM outputs to ensure during power-up and power-down, that the inverter’s drive inputs are at a known, turned off, state.

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

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The MC3PHAC motor controller will operate in two modes. The first is standalone operation, whereby the MC3PHAC can be used without any intervention from an external personal computer. In standalone mode, the MC3PHAC is initialized by passive devices connected to the MC3PHAC and input to the system at power-up/reset time. In standalone mode, some parameters continue to be input to the system as it operates. Speed, PWM frequency, bus voltage, and acceleration parameters are input to the system on a real-time basis. The second mode of operation is called PC master software mode.That operational mode requires the use of a personal computer and PC master software executing on the personal computer, communicating with the MC3PHAC, or a microcontroller emulating PC master software commands. All command and setup information is input to the MC3PHAC via the PC host. Standalone Operation If the VBOOST_MODE pin is high when the MC3PHAC is powered up, or after a reset, the MC3PHAC enters standalone mode. In this mode of operation, the functionality of many of the MC3PHAC pins change so that the device can control a motor without requiring setup information from an external master. When operated in standalone mode, the MC3PHAC will drive certain pins corresponding to parameters which must be specified, while simultaneously monitoring the response on other pins. In many cases, the parameter to be specified is represented as an analog voltage presented to the MUX_IN pin, while certain other pins are driven low. In so doing, the MC3PHAC can accommodate an external analog mux which will switch various signals on the MUX_IN pin when the signal select line goes low. All signals must be in a range between 0 V and V REF. As an economical alternative, an external passive network can be connected to each of the parameter select output pins and the MUX_IN pin, as shown in Figure 8. The Thevenin equivalent impedance of this passive network as seen by the MUX_IN pin is very important and should be in the range of 5 kΩ to 10 kΩ. If the resistance is too high, leakage current from the input/output (I/O) pins will cause an offset voltage that will affect the accuracy of the reading. If the resistance is too low, the parameter select pins will not be able to sink the required current for an accurate reading. Using a pullup resistor value of 6.8 kΩ (as indicated in Figure 8), the resulting value for each parameter as a function of the corresponding pulldown resistor value is shown in Figure 9, Figure 10, Figure 11, and Table 4. The START input pin is debounced internally and a switch can be directly accommodated on this pin. The input is level sensitive, but a logic 1 level must exist on the pin before a logic 0 level will be processed as a start signal. This will prevent an accidental motor startup in the event of the MC3PHAC being powered up, where the switch was left in the start position. The FWD input pin is debounced internally and can directly accommodate a switch connection. The input is also level sensitive. Figure 8 shows the jumper arrangement connected to the PWMPOL_BASEFREQ input pin. For proper operation, one and only one jumper connection can be made at any given time. Table 3 shows the polarity and base frequency selections as a function of the jumper connection.

Figure 8. Standalone MC3PHAC Configuration

1. If no external fault circuit is provided, connect to VSS.
2. Use bypass capacitors placed close to the MC3PHAC.
3. Consult crystal/resonator manufacturer for component values.

4.0 MHz

50 Hz – PWM POLARITY

50 Hz + PWM POLARITY

60 Hz – PWM POLARITY

60 Hz + PWM POLARITY+5 V

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Figure 9. Dead Time as a Function of the RDEADTIME Resistor Figure 10. Fault Retry Time as a Function of the RRETRY Resistor Figure 11. Voltage Boost as a Function of the RBOOST Resistor

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 19 Standalone Application Example Figure 12 shows an application example of the MC3PHAC, configured in standalone mode. Resistor values and jumpers have been selected to provide the following performance: 1. Base frequency of 60 Hz and positive PWM polarity (from Table 3) 1.82 volts 3. Dead-time resistor = 5.1 k Ω, which implies 4.5 µs (from Figure 9) 4. Fault retry time resistor = 8.2 k Ω, which implies 32.8 seconds (from Figure 10). 5. Voltage boost resistor = 12 k Ω, which implies 25.5 percent (from Figure 11). 6. The wiper of the acceleration potentiometer is set at 2.5 V = 64 Hz/second acceleration rate (from the Acceleration Control description on page 11.) The potentiometer, in this case, could have been a resistor divider. If a resistor divider is used in place of the acceleration potentiometer, keep the total resistance of the two resistors less than 10 kΩ. Always use 4.7kΩ in series with the center of the acceleration voltage divider resistors, connected to the ACCEL (pin 27) as shown in the application example, Figure 12. 7. Crystal/resonator capacitor values are typica l values from the manufacturer. Refer to the manufacturers data for actual values. PC Master Software Operation Introduction to PC Master Host Software The MC3PHAC is compatible with Freescale’s PC master host software serial interface protocol. Communication occurs over an on-chip UART, on the MC3PHAC at 9600 baud to an external master device, which may be a microcontroller that also has an integrated UART or a personal computer via a COM port. With PC master software, an external controller can monitor and control all aspects of the MC3PHAC operation. When the MC3PHAC is placed in PC master software mode, all control of the system is provided through the integrated UART, resident on the MC3PHAC. Inputs such as START, FWD, SPEED, ACCEL, MUX_IN, and PWMPOL_BASEFREQ have no controlling influence over operation of the system. Even though the SPEED, START, and FWD inputs are disabled while the system is in PC master software mode, through PC master software, it is possible to monitor the state of those inputs. The most popular master implementation is a PC, where a graphical user interface (GUI) has been layered on top of the PC master software command protocol, complete with a graphical data display, and an ActiveX interface. Figure 13 shows the MC3PHAC configured in PC master software mode. It is beyond the scope of this document to describe the PC master software protocol or its implementation on a personal computer. For further information on these topics, refer to other Freescale documents relating to the PC master software protocol and availability of PC master host software.

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Figure 12. MC3PHAC Application Example in Standalone Mode

1. If no external fault circuit is provided, connect to VSS.
2. Use bypass capacitors placed close to the MC3PHAC.
3. Consult crystal/resonator manufacturer for component values.

Figure 13. MC3PHAC Configuration for Using a PC as a Master Table 5. Recognized PC Host Software Commands

1. If no external fault circuit is provided, connect to VSS.
2. Use bypass capacitors placed close to the MC3PHAC.
3. Consult crystal/resonator manufacturer for component values.

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valid range for each variable. See Table 6 for a list of valid data values and valid write addresses. Table 6. User Interface Variables for Use with PC Master Software outputs are positive polarity. This is a write-once parameter.

60 Hz — $60

50 Hz — $61

frequency(3) $0062 R/W 2 Commanded frequency in Hz. Voltage boost $006C R/W 1 0 Hz voltage.

1. The commanded PWM frequency cannot be written until the PWM outputs exit the high-impedance state. The default PWM
2. The PWM output pins remain in a high-impedance state until this parameter is specified.
3. This parameter must be specified before motor motion can be initiated by the MC3PHAC.
4. This is a write-once parameter. The first write to this address will execute normally. Further attempts at writing this

parameter will result in an illegal operation response from the MC3PHAC.

1. The value of this parameter is not valid until the PWM outputs exit the high-impedance state.
2. The data in this field is only valid for one read. Further reads will return a value of $00.
3. See register bit descriptions following this table.
4. Acceleration is an unsigned value with the upper seven bits range of $00 to $7F = acceleration value of 0 to

$1FF which equals 0 to ~1. Therefore, the range of acceleration is 0 to 127.99 Hertz/second.

1. Commanded motor frequency and actual frequency are signed values with the upper byte range of

a 5 volt full scale input. The value is equal to the voltage applied to the DC_BUS input pin/VREF * $03FF. Table 6. User Interface Variables for Use with PC Master Software (Continued)

24 Freescale Semiconductor

Each bit variable listed in Table 6 is defined in Figure 14, Figure 15, Figure 16, and Figure 17. Figure 14. Status Register Table 7. Status Register Field Descriptions accelerating or declerating. 0 Motor is at a steady speed. 1 Motor is accelerating or decelerating. 0 Motor is rotating in the reverse direction. $0085 and $0086) is 0, the motor is stopped. 0 The PWM outputs are inactive or the bottom PWM outputs are in the pre-charge cycle. 1 All PWM outputs are active. 0 The RBRAKE output pin is inactive and no braking is in progress. 1 The RBRAKE output pin is acti ve. Braking is in progress. a logic 1 applied to the FAULTIN pin. 0 A logic 0 is applied to the FAULTIN pin and no FAULT timeout is in progress. 1 A logic 1 was applied to the FAULTIN pin and a FAULT timeout is still in progress. Bus over voltage located at address $0068 and $0069.

0 The voltage applied to the DC_BUS pin is less than the preset value of V Bus over voltage and

a FAULT timeout is not in progress.

1 The voltage applied to the DC_BUS pin has exceeded the preset value of V Bus over voltage

and a FAULT timeout is still in progress. than the present value of VBus brownout located at address $0066 and $0067.

0 The voltage applied to the DC-BUS pin is greater than the preset value of V Bus under voltage

and a FAULT timeout is not in progress.

1 The voltage applied to the DC_BUS pin is less than the present value of V Bus under voltage

and a FAULT timeout is still in progress.

Figure 15. Setup Register Table 8. Setup Register Field Descriptions 0 Base frequency parameter has not been set. 1 Base frequency parameter has been set. SPEED SET Bit — This read-only bit indicates if the speed parameter has been set. 0 Speed parameter has not been set. 1 Speed parameter has been set. 0 Acceleration rate parameter has not been set. 1 Acceleration rate parameter has been set. POLARITY SET Bit — This read-only bit indicates if the PWM polarity parameters has been set. 0 PWM polarity parameters has not been set. 1 PWM polarity parameters has been set. DEAD TIME SET Bit — This read-only bit indicates if the dead time parameter has been set. 0 Dead time parameter has not been set. 1 Dead time parameter has been set.

26 Freescale Semiconductor

Figure 16. Switch In Register Table 9. Switch In Register Field Descriptions START/STOP Bit — This read-only bit indicates the state of the START input pin. 0 The START input pin is at a logic 0. 1 The START input pin is at a logic 1. FWD/REVERSE Bit — This read-only bit indicates the state of the FWD input pin. FAULT OUT Bit — This read-only bit indicates the state of the DT_FAULTOUT output pin. 0 The DT_FAULTOUT output pin is indicating a fault condition. 1 The DT_FAULTOUT output pin is indicating no fault condition. RESISTIVE BRAKE Bit — This read-only bit indicates the st ate of resistive brake pin (RBRAKE). 0 The RBRAKE output pin in inactive and no braking is in progress. 1 The RBRAKE output pin in active. Braking is in progress.

Figure 17. Reset Status Register Table 10. Reset Status Register Field Descriptions

0 Power-up reset was not the source of the reset or a read of the reset status register after the

1 The last reset was caused by an initial power-up of the MC3PHAC.

0 The RESET

1 Last reset was caused by an exte rnal reset applied to the RESET input pin. the result of an internal system error.

0 The FUNCTIONAL FAULT was not the source of the reset or a read of the reset status register

1 MC3PHAC internal system error

reset was the result of a PC master software reset command.

0 The PC master software RESET COMMAND was no t the source of the reset or a read of the

reset status register after the first read.

1 The MC3PHAC was reset by the PC master software command reset as the result of a write

1 The last reset was caused by the low power supply detection circuit.

28 Freescale Semiconductor

Figure 18. It illustrates the sequence of commands which are necessary to bring the device from the reset will remain within a given state unless the conditions shown for a transition are met. decelerating, or in a steady state. Each state is described here in more detail. and polarity to be initialized. be modified, unless the reset state is first re-entered. modified, unless the reset state is first re-entered. and acceleration to be initialized. or CmdRev command is received.

Figure 18. PC Host Software Command State Diagram

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

30 Freescale Semiconductor

 PWMPump — This state is entered from the PWM0RPM state when a CmdFwd or CmdRev command is received. In this state the top PWM outputs are driven off while the bottom PWM outputs are driven with a 50 percent duty cycle. This allows high side transistor gate drive circuits which require charge pumping from the lower transistors to be charged up prior to applying full PWMs to energize the motor. This state is automatically exited after the defined amount of time tPump (see Electrical Characteristics).  FwdAccel — This state is entered from the PWMPump state after a CmdFwd command is received and the timeout interval from the PWMPump state is completed. This state can also be entered from the FwdSteady state if the Speed In variable is increased above the actual current speed and the RevDecel state if the actual motor speed equals 0 r.p.m. when a CmdFwd command has been received. In this state the motor is accelerated forward according to the chosen parameters.  FwdSteady — This state is entered from the FwdAccel state after the actual motor speed has reached the requested speed defined by the Speed In variable. In this state, the motor is held at a constant forward speed.  FwdDecel — This state is entered from the FwdAccel or FwdSteady states whenever a CmdStop or CmdRev command is received. This state can also be entered from the FwdSteady state if the Speed In variable is decreased below the actual current speed. In this state, the motor is decelerated forward according to the chosen parameters.  RevAccel — This state is entered from the PWMPump state. After a CmdRev command is received and the timeout interval from the PWMPump state is completed. This state can also be entered from the RevSteady state if the Speed In variable is increased above the actual current speed and the FwdDecel state if the actual motor speed equals 0 r.p.m. when a CmdRev command has been received. In this state, the motor is accelerated in reverse according to the chosen parameters.  RevSteady — This state is entered from the RevAccel state after the actual motor speed has reached the requested speed defined by the Speed In variable. In this state, the motor is held at a constant reverse speed.  RevDecel — This state is entered from the RevAccel or RevSteady states whenever a CmdStop or CmdFwd command is received. This state can also be entered from the RevSteady state if the Speed In variable is decreased below the actual current speed. In this state, the motor is decelerated in reverse according to the chosen parameters.  SetBaseFreq — This state is entered from any state whenever a CmdBaseFreqxx command is received. In this state, the motor frequency at which full voltage is applied is configured and the state is then automatically exited and the original state is re-entered.  SetAccel — This state is entered from any state w henever a write to the Acceleration variable occurs. In this state, the motor acceleration is configured and the state is then automatically exited and the original state is re-entered.  SetSpeed — This state is entered from any state whenever a write to the Speed In variable occurs. In this state, the requested motor speed is configured and the state is then automatically exited and the original state is re-entered.  Fault — This state is entered from any state whenever a fault condition occurs (see Fault Protection on page 13). In this state, the PWM outputs are driven off (unless the fault state was entered from the PWMHighZ state, in which case, the PWM outputs remain in the High Z state). When the problem causing the fault condition is removed, a timer is started which will wait a specified amount of time (which is user programmable) before exiting this state. Under normal

used with the MC3PHAC to isolate the serial port of the PC from the motor control system. terminal interface provides a margin of safety between the motor control system and a personal computer. into an input and output section simplifies the explanation of the circuit. Figure 19. Optoisolated RS232 Circuit

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

32 Freescale Semiconductor

Optoisolated RS232 Interface Application Example shifting from the PC to the MC3PHAC’s serial port. An RS-232 line receiver, such as an MC1489, serves the same purpose without the optoisolation function. To send data from the MC3PHAC to the PC’s serial port input, it is necessary to satisfy the PC’s receive data (RxD) input requirements. In an idle condition, the RxD input to the PC must be at Mark (–3 to –25 volts). The data terminal ready output (DTR) on the PC outputs a Mark when the port is initialized. The request to send (RTS) output is set to a Space (+3 to +25 volts) when the PC’s serial port is initialized. Because the interface is half-duplex, the PC’s TxD output is also at a Mark, as it is idle. The idle state of the MC3PHAC’s serial port output is a logic 1. The logic 1 out of the MC3PHAC’s serial port output port forces the diode in U2 to be turned off. With the diode in U2 turned off, the transistor in U2 is also turned off. The junction of D2 and D3 are at a Mark (–3 to –25 volts). With the transistor in U2 turned off, the input is pulled to a Mark through current limiting resistor R3, satisfying the PC’s serial input in an idle condition. When a start bit is sent from the MC3PHAC’s serial port, it transitions to a logic 0. That logic 0 turns on the diode in U2, thus turning on the transistor in U2. The conducting transistor in U2 passes the voltage output from the PC’s RTS output, that is now at a Space (+3 to +25 volts), to the PC’s receive data (RxD) input. Capacitor C1 is a bypass capacitor used to stiffen the Mark signal. The output half of the circuit provides output isolation, signal inversion, and level shifting from the MC3PHAC’s serial output port to the PC’s serial port. An RS-232 line driver, such as a MC1488, serves the same purpose without the optoisolation function.

34 Freescale Semiconductor

Figure 22. Plastic 32-Pin QFP (Case 873A)

1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM

THE BOTTOM OF THE PARTING LINE.

1. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
2. DIMENSIONS S AND V TO BE DETERMINED AT
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

DETERMINED AT DATUM PLANE –AB–.

1. DIMENSION D DOES NOT INCLUDE DAMBAR
2. MINIMUM SOLDER PLATE THICKNESS SHALL BE
3. EXACT SHAPE OF EACH CORNER MAY VARY

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 Freescale Semiconductor 35

Rev. 2, 7/2005 How to Reach Us: USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P .O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor H.K. Ltd.

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