RE46C180E16F

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Document overview

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Technical content

Features

• 6 – 12V Operation
• Low Quiescent Current Consumption
• Programmable Standby Sensitivity
• Programmable HUSH Sensitivity
• Programmable Hysteresis
• Programmable Chamber Voltage for Push-to-Test (PTT) and Chamber Test
• Programmable ±150 mV Low Battery Set Point
• Internal Ionization Chamber Test
• Internal Low Battery Test
• Internal Power-On Reset and Power-up Low Battery Test
• Alarm Memory
• Auto Alarm Locate
• Horn Synchronization
• IO Filter and Charge Dump
• Smart Interconnect
• Interconnect up to 40 Detectors
• ±5% All Internal Oscillator
• 9 Minute or 80 Second Timer for Sensitivity Control
• Temporal or Continuous Horn Pattern
• Guard Outputs for Ion Detector Input
• ±0.75 pA Detect Input Current
• 10-year End-of-Life Indication

Description

The RE46C180 is a next generation low power, CMOS ionization-type, smoke detector IC. With minimal exter- nal components, this circuit will provide all the required features for an ionization-type smoke detector. An on-chip oscillator strobes power to the smoke detection circuitry for 5 ms every 10 seconds to keep the standby current to a minimum. A check for a Low Battery condition is performed every 80s and an ionization chamber test is performed once every 320s when in Standby. The temporal horn pattern complies with the National Fire Protection Association NFPA 72 ® National Fire Alarm and Signaling Code® for emergency evacuation signals. An interconnect pin allows multiple detectors to be con- nected, such that when one unit alarms, all units will sound. A charge dump feature quickly discharges the interconnect line when exiting a Local Alarm condition. The interconnect input is also digitally filtered. An internal 9 minute or 80s timer can be used for a Reduced Sensitivity mode. An alarm memory feature allows the user to determine whether the unit has previously entered a Local Alarm condition. Utilizing low-power CMOS technology, the RE46C180 is designed for use in smoke detectors that comply with the Standard for Single and Multiple Station Smoke Alarms, UL217 and the Standard for Smoke Detectors for Fire Alarm Systems, UL268. Package Types RE46C180 PDIP, SOIC TEST 1 IO GLED CHAMBER RLED VDD TESTOUT FEED GUARD2 DETECT GUARD1 HS HB V SS CMOS Programmable Ionization Smoke Detector ASIC with Interconnect, Timer Mode and Alarm Memory

DS22275A-page 2  2011 Microchip Technology Inc. Functional Block Diagram VDD (6) TEST (1) GUARD1 (14) DETECT (15) GUARD2 (16) VSS (9) IO (2) FEED (8) HS (11) RLED (5) HB (10) CHAMBER (4) T3 (13) Logic and Timing BIAS, Power Reset and Trimmable Oscillator Programmable Trim Trimmable Low Batt Reference Trimmable Smoke Reference GLED (3) Chamber Voltage T2 (12) TESTOUT (7)Test and Program Mode Sel Low Batt Comp Smoke Comp Guard Amp Trimmable Low Batt Setting

 2011 Microchip Technology Inc. DS22275A-page 3 RE46C180 Typical Application Note 1: R3, R4 and C1 are typical values, and may be adjusted to maximize sound pressure. 2: C2 should be located as close as possible to the device power pins. 3: Route the pin 8 PC board trace away from pin 4 to avoid coupling. 4: No internal reverse battery protection. External reverse battery protection circuitry required. Battery 1 µF 390 100 To Other Units TEST and HUSH 220K 1.5M .001 µF Rled TEST IO GLED CHAMBER RLED VDD TESTOUT FEED GUARD2 DETECT GUARD1 HS HB V SS 8 9 Gled 390 RE46C180 C310 µF

DS22275A-page 4  2011 Microchip Technology Inc.

1.0 ELECTRICAL

1.1 Absolute Maximum Ratings†

† Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD =9 V , VSS =0 V (Note 1) Parameter Symbol Test Pin Min Typ Max Units Conditions Supply Voltage V DD 6 6 — 12 V Operating Supply Current I DD1 6 — 3.8 5.3 µA Operating, RLED off, GLED off IDD2 6 — — 6 µA Operating, V DD =1 2 V , RLED off, GLED off IDD3 6 — 9.6 13.9 µA Operating, RLED off, GLED off, Smoke check IDD4 6 — 21.4 30 µA Operating, RLED off, GLED off, Low Battery check Input Voltage High V IH1 86 ——V VIH2 2 3 — — V No Local Alarm, IO as an input VIH3 15 . 6 — — V VIH4 12 5.6 — — V Input Voltage Low V IL1 8— —2 . 8V VIL2 2 — — 1 V No Local Alarm, IO as an input VIL3 1— —3 . 4V VIL4 12 — — 3.4 Input Leakage Low IL DET1 15 — — -0.75 pA V DD =9 V , D E T E C T=VSS, 0-40% RH, TA = +25°C ILDET2 15 — — -1.5 pA V DD =9 V , D E T E C T=VSS, 85% RH, TA = +25°C (Note 2) ILFD1 8 — — -50 µA FEED = -10V ILFD2 8 — — -100 nA FEED = V SS Note 1: Production tested at room temperature with temperature guard banded limits. 2: Sample test only. 3: Not 100% production tested. 4: Same limit range at each programmable step, see Table 4-1.

 2011 Microchip Technology Inc. DS22275A-page 5 RE46C180 Input Leakage High IH DET1 15 — — 0.75 pA V DD = 9V, DETECT = VDD, 0–40% RH, TA = +25°C IHDET2 15 — — 1.5 pA V DD = 9V, DETECT = VDD, 85% RH, TA = +25°C (Note 2) IHFD1 8 — — 50 µA FEED = 22V IHFD2 8 — — 100 nA FEED = V DD IIOL2 2 — — 150 µA No Alarm, V IO =1 5 V Output Off Leakage High I IOHZ 3, 5 — — 1 µA Outputs Off, VRLED = 9V, VGLED = 9V Input Pull Down Current I PD1 1 20 50 80 µA TEST = 9V IPD2 12 0.4 0.8 1.3 mA T2 = 9V Output High Voltage V OH1 10,11 6.3 — — V I OH = -16 mA, VDD = 7.2V Output Low Voltage V OL1 10,11 — — 0.9 V I OL = 16 mA, VDD = 7.2V VOL3 3, 5 — — 1 V I OL = 10 mA, VDD = 7.2V Output Current I IOL1 2 25 — 60 µA No Alarm, V IO = VDD -2V IIOH1 2 -4 — -16 mA Alarm, V IO = 4V or VIO = 0V IIODMP 2 5 — — mA At conclusion of Local Alarm or PTT, VIO = 1V Low Battery Voltage V LB 6 6.75 6.9 7.05 V LBTR[2:1] = 1 0 7.05 7.2 7.35 V LBTR[2:1] = 1 1 7.35 7.5 7.65 V LBTR[2:1] = 0 0 7.65 7.8 7.95 V LBTR[2:1] = 0 1 Offset Voltage V GOS1 14,15 -50 — 50 mV Guard amplifier VGOS2 15,16 -50 — 50 mV Guard amplifier VGOS3 15 -50 — 50 mV Smoke comparator Common Mode Voltage V CM1 14,15 2 — V DD–.5 V Guard amplifier ( Note 3) VCM2 15 0.5 — V DD–2 V Smoke comparator ( Note 3) Output Impedance Z OUT 14,16 — 10 — k  Guard amplifier outputs (Note 3) Chamber Voltage in PTT/Chamber Test VCHAMBER 4 4.49 4.5 4.51 V User programmable (2.1V to 6.75V) (Note 4) Hysteresis V HYS 13 140 150 160 mV No Alarm to Alarm condition, user programmable (50 to 225 mV) (Note 4) DC ELECTRICAL CHARACTERISTICS (CONTINUED) VDD =9 V , VSS =0 V (Note 1) Parameter Symbol Test Pin Min Typ Max Units Conditions Note 1: Production tested at room temperature with temperature guard banded limits. 2: Sample test only. 3: Not 100% production tested. 4: Same limit range at each programmable step, see Table 4-1.

DS22275A-page 6  2011 Microchip Technology Inc. AC ELECTRICAL CHARACTERISTICS VDD = 9V, VSS = 0V. Parameter Symbol Test Pin Min Typ Max Units Conditions Time Base Internal Oscillator Period T POSC 7 593 625 657 µs Test mode ( Note 1) Internal Clock Period T PCLK 9.5 10 10.5 ms Operating RLED Indicator On Time T ON1 5 9.5 10 10.5 ms Operating Period T PLED1 5 304 320 336 s Standby TPLED2 5 0.95 1 1.05 s Local alarm TPLED3 5 9.5 10 10.5 s HUSH mode, No Local Alarm GLED Indicator Period T PLED4 3 38 40 42 s Alarm Memory Indication GLED period, No Alarm, no PTT TPLED5 3 237 250 263 ms Alarm Memory Indication GLED period upon PTT, AMLEDEn = 1 Off Time T OFLED1 3 0.95 1 1.05 s Alarm Memory Indication GLED off time between pulses TOFLED2 3 36 38 40 s Alarm Memory Indication GLED off time between pulse trains (3x) Alarm Memory Indication Timeout Period TAMTO 3 22.8 24 25.2 Hour AMTO[2:1] = 0 0 45.6 48 50.4 Hour AMTO[2:1] = 0 1 0 0 0 Hour AMTO[2:1] = 1 0, No Alarm Memory Indication Alarm Memory Indication never times out, as long as Alarm Memory Latch is set Smoke Check Smoke Check Time T SCT — 4.7 5 5.3 ms Operating Smoke Check Period T PER0 — 9.5 10 10.5 s Standby, No Alarm TPER1 — 0.95 1 1.05 s Standby, after one valid smoke sample and before entering Local Alarm, no PTT T PER2 — 237 250 263 ms Standby, upon start of PTT and before entering Local Alarm T PER3 — 0.95 1 1.05 s Local Alarm (after three con- secutive valid smoke samples) or Remote Alarm Chamber Test Period T PCT1 — 304 320 336 s Operating Note 1: TPOSC is 100% production tested. All other timing is verified by functional testing. 2: See timing diagram for CO alarm horn pattern. 3: See timing diagram for smoke alarm temporal and non-temporal horn pattern. 4: See timing diagram for horn synchronization and Auto Alarm Locate (AAL).

 2011 Microchip Technology Inc. DS22275A-page 7 RE46C180 Low Battery Low Battery Check Period TPLB1 — 76 80 84 s Standby, No Alarm, No Low Battery TPLB2 — 304 320 336 s Standby, No Alarm, Low Battery Horn Operation Horn Delay T HDLY1 10, 11 475 500 525 ms From Local Alarm to Horn Active, temporal horn pattern THDLY2 10, 11 380 400 420 ms From Local Alarm to Horn Active, continuous horn pattern Horn Period T HPER1 10, 11 38 40 42 s Low Battery, No Alarm THPER2 10, 11 38 40 42 s Chamber Failure, No Alarm THPER3 10, 11 237 250 263 ms Alarm Memory Indication upon PTT, AMHCEn=1 THPER4 10, 11 5.5 5.8 6.1 s CO Alarm horn period (Note 2) Horn On Time T HON1 10, 11 9.5 10 10.5 ms 1. Low Battery, No Alarm 2. Chamber Failure 3. Alarm Memory Indication upon PTT, AMHCEn = 1 THON2 10, 11 475 500 525 ms Smoke Alarm, temporal horn pattern (Note 3) THON3 10, 11 332 350 368 ms Smoke Alarm, continuous horn pattern (Note 3) THON4 10, 11 95 100 105 ms CO Alarm, COEn = 1 Horn Off Time T HOF1 10, 11 475 500 525 ms Smoke Alarm, temporal horn pattern (Note 3) THOF2 10, 11 1.43 1.5 1.58 s Smoke Alarm, temporal horn pattern (Note 3) THOF3 10, 11 143 150 158 ms Smoke Alarm, continuous horn pattern (Note 3) THOF4 10, 11 37 39 41 s Chamber Fail horn off time between pulse trains (3x) THOF5 10, 11 465 490 515 ms Chamber Fail horn off time between pulses THOF6 10, 11 95 100 105 ms CO Alarm horn off time between pulses, COEn = 1 (Note 2) THOF7 10, 11 4.8 5.1 5.4 s CO alarm horn off time between pulse trains, COEn = 1 (Note 2) AC ELECTRICAL CHARACTERISTICS (CONTINUED) VDD = 9V, VSS = 0V. Parameter Symbol Test Pin Min Typ Max Units Conditions Note 1: TPOSC is 100% production tested. All other timing is verified by functional testing. 2: See timing diagram for CO alarm horn pattern. 3: See timing diagram for smoke alarm temporal and non-temporal horn pattern. 4: See timing diagram for horn synchronization and Auto Alarm Locate (AAL).

DS22275A-page 8  2011 Microchip Technology Inc. Interconnect IO Active Delay T IODLY1 2 3.5 3.7 3.9 s From start of Local Alarm to IO Active. SyncEn = 1 2 3.1 3.3 3.5 s From start of Local Alarm to IO Active. SyncEn = 0 Remote Smoke Alarm Delay TIODLY2 2 769 810 851 ms No Local Alarm, from IO Active to Alarm, temporal horn pattern TIODLY3 2 299 315 331 ms No Local Alarm, from IO Active to alarm, continuous horn pattern IO Filter for Remote Smoke Alarm TIOFILT 2 — — 291 ms IO pulse-width to be filtered IO as input, no Local Alarm IO Pulse On Time for CO Alarm TIOPW1 2 37 — 290 ms No Local Alarm, 2 valid pulses required for CO IO Pulse Off Time for CO Alarm TIOTO1 2—— 5 . 4s I O = L o w IO Dump T IODMP1 2 475 500 525 ms At conclusion of Local Alarm or PTT Horn Synchronization IO Pulse Period T PIO1 2 3.8 4 4.2 s Local Alarm, temporal horn pattern, SyncEn =1 (Note 4) IO Pulse On Time T ONIO 2 3.41 3.59 3.77 s Local Alarm, temporal horn pattern, SyncEn =1 (Note 4) Horn Sync IO Dump T IODMP2 2 95 100 105 ms Local Alarm, SyncEn =1 (Note 4) Horn Sync IO Dump Delay TIODLY4 2 285 300 315 ms Local Alarm, SyncEn =1 (Note 4) Auto Alarm Locate (AAL) IO Cycle Period T PIO2 2 15.2 16 16.8 s Local Alarm, temporal horn pattern, SyncEn =1, NoAAL = 0 (Note 4) IO Cycle Off Time T OFIO 2 4.19 4.41 4.63 s Local Alarm, temporal horn pattern, SyncEn = 1, No AAL = 0, IO off time between IO pulse trains (3x) (Note 4) HUSH Timer Operation HUSH Timer Period T TPER — 8.5 9 9.5 min No Alarm, ShrtTO = 0 — 76 80 84 s No Alarm, ShrtTO = 1 EOL End-of-Life Age Sample T EOL — 346 364 382 Hours Standby, EOLEn = 1 AC ELECTRICAL CHARACTERISTICS (CONTINUED) VDD = 9V, VSS = 0V. Parameter Symbol Test Pin Min Typ Max Units Conditions Note 1: TPOSC is 100% production tested. All other timing is verified by functional testing. 2: See timing diagram for CO alarm horn pattern. 3: See timing diagram for smoke alarm temporal and non-temporal horn pattern. 4: See timing diagram for horn synchronization and Auto Alarm Locate (AAL).

 2011 Microchip Technology Inc. DS22275A-page 9 RE46C180 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 9V, VSS = 0V Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T A -10 — +60 °C Storage Temperature Range T STG -55 — +125 °C Thermal Package Resistances Thermal Resistance, 16L-PDIP θJA —7 0— ° C / W Thermal Resistance, 16L-SOIC (150 mil.) θJA — 86.1 — °C/W

DS22275A-page 10  2011 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE RE46C180 PDIP, SOIC Symbol Function

1 TEST This input is used to invoke Push-to-Test, Timer mode and Alarm Memory

Indication. This input has an internal pull-down.

2 IO This bidirectional pin provides the capability to interconnect many detectors

in a single system. This pin has an internal pull-down device and a charge dump device.

3 GLED Open drain NMOS output, used to drive a visible LED to provide visual

indication of an Alarm Memory condition. 4 CHAMBER Connect to the ionization smoke chamber. This pin provides power to the chamber 5 RLED Open drain NMOS output, used to drive a visible LED. This pin provides the load current for the Low Battery test, and is a visual indicator for alarm and HUSH mode. DD Connect to the positive supply voltage 7 TESTOUT This output is an indicator of the internal IO dump signal. This pin is also used for Test modes.

8 FEED Usually connected to the feedback electrode through a current limiting

resistor. If not used, this pin must be connected to VDD or VSS. 9V SS Connect to the negative supply voltage. 10 HB This pin is connected to the metal electrode of a piezoelectric transducer.

11 HS This pin is a complementary output to HB, connected to the ceramic

electrode of the piezoelectric transducer. 12 T2 Test input to invoke Test modes. This pin has an internal pull-down. 13 T3 Test output for Test modes. 14 GUARD1 Output of the guard amplifier. This allows for measurement of the DETECT input without loading the ionization chamber. 15 DETECT Connect to the CEV of the ionization smoke chamber. 16 GUARD2 Output of the guard amplifier. This allows for measurement of the DETECT input without loading the ionization chamber.

 2011 Microchip Technology Inc. DS22275A-page 11 RE46C180

3.0 DEVICE DESCRIPTIONS

3.1 Standby Internal Timing

The internal oscillator is manufactured to ±5% toler- ance. The oscillator period, TPOSC, is 625 µs. The inter- nal clock period, TPCLK, of 10 ms is derived from the internal oscillator period. In Standby, once every 10s, the smoke detection cir- cuitry is powered on for 5 ms. At the conclusion of the 5 ms, the status of the smoke comparator is latched. If a Smoke condition is present, the period to the next detection decreases and additional checks are made. In Standby, once every 80s, the Low Battery detection circuitry is powered on for 10 ms. At the conclusion of the 10 ms, the status of the Low Battery comparator is latched. RLED is enabled for 10 ms every 320s to provide a battery load in the loaded battery test. In Standby, once every 320s, the chamber test circuitry is powered on for 5 ms. At the conclusion of the 5 ms, the status of the chamber test is latched. See Section 3.3 “Supervisory Tests” for details.

3.2 Smoke Detection Circuitry

The collection electrode voltage (CEV) of the ionization chamber is compared to the stored reference voltage at the conclusion of the 5 ms smoke sample period. After the first Smoke condition is detected, the smoke detec- tion rate increases to once every 1s. Three consecutive smoke detections will cause the device to go into Local Alarm, and the horn circuit and IO will be active. RLED will turn on for 10 ms at 1 Hz rate. In Local Alarm, the smoke reference voltage (smoke sensitivity) is internally increased to provide alarm hysteresis. There are three separate smoke sensitivity settings (all user programmable):

• Standby sensitivity
• Local alarm (hysteresis) sensitivity
• HUSH sensitivity During PTT, the standby smoke sensitivity is used in smoke detection; but the CHAMBER voltage is user programmable. The guard amplifier and outputs are always active, and will be within 50 mV of the DETECT input to reduce surface leakage. The guard outputs also allow for measurement of the DETECT input without loading the ionization chamber.

3.3 Supervisory Tests

Once every 80s, the status of the battery voltage is checked by comparing a fraction of the V DD voltage to an internal reference. In each period of 320s, the bat- tery is checked four times. Of these four battery checks, three are unloaded and one is loaded with RLED enabled, which provides a battery load. Low bat- tery status is latched at the end of the 10 ms RLED pulse. If the Low Battery test fails, the horn will chirp for 10 ms every 40s, and will continue to chirp until the next loaded Low Battery check is passed. The unloaded Low Battery checks are skipped in Low Battery condition. As a user programmable option, a Low Battery Hush mode can be selected. If a Low Battery condition exists, upon release of PTT, the unit will enter the Low Battery Hush mode, and the 10 ms horn chirp will be silenced for 8 hours. At the conclusion of the 8 hours the audible indication will resume, if the Low Battery condition still exists In addition, every 320s, a background chamber test is performed by internally lowering the CHAMBER volt- age to a pre-determined level (user programmable) for 3.7s. This will emulate a Smoke condition. At the end of this 3.7s period, the smoke detection circuitry is pow- ered on for 5 ms, and the Smoke condition is detected. If two consecutive chamber tests failed to detect a sim- ulated Smoke condition, the chamber fail latch is set and the failure warning is generated. The horn will chirp three times every 40s. Each chirp is 10 ms long and three chirps are spaced at a 0.5s interval. The chamber fail warning chirp is separated from the Low Battery warning chirp by about 20s. The horn will continue this pattern until the chamber fail latch is reset. The chamber fail latch resets when any one of the followings is active:

• Two consecutive chamber tests pass
• Local smoke alarm
• PTT smoke alarm After the chamber test is completed, the CHAMBER voltage goes back to its normal standby level. Chamber test is performed approximately 140s after the loaded Low Battery test. In a Local Alarm, PTT Alarm or Remote Alarm condi- tion, the chamber test is not performed, and the Low Battery chirping is prohibited.

DS22275A-page 12  2011 Microchip Technology Inc.

3.4 Push-to-Test (PTT)

PTT is an event when TEST is activated (V IH3). Release of PTT is an event when TEST is deactivated IL3). PTT has different functions for different circum- stances. In Standby, PTT tests the unit. Upon start of PTT, the CHAMBER voltage is lowered to a pre-deter- mined level (user programmable) to emulate a Smoke condition. The smoke detection rate increases to once every 250 ms. After three consecutive smoke detec- tions, the unit will go into a Local Alarm condition. In alarm, the smoke detection rate decreases to once every 1s. Upon release of PTT, the unit is immediately reset out of Local Alarm, and the horn is silenced. The chamber voltage goes back to the normal standby level, and the detection rate goes back to once every 10s. When the unit exits a Local Alarm condition, the alarm memory latch is set. PTT will activate the alarm mem- ory indication if the alarm memory latch is set and if the alarm memory indication function has been enabled. If the alarm memory indication function has not been enabled and the alarm memory latch is set, PTT will test the unit as described above. The release of PTT will always reset the alarm memory latch. In Standby and Low Battery conditions, PTT tests the unit and RLED will be constantly enabled. This allows the user to easily identify the low battery unit without waiting for 40s to hear a horn chirp. Upon release of PTT, RLED goes back to normal standby pulse rate. The Low Battery HUSH mode is then activated, if this function is enabled.

3.5 Interconnect Operation

The bidirectional IO pin allows the interconnection of multiple detectors. In a Local Alarm condition, this pin is driven high 3.7s after a Local Alarm condition is sensed through a constant current source. Shorting this output to ground will not cause excessive current. The IO is ignored as input during a Local Alarm. The IO also has an NMOS discharge device that is active for 0.5s after the conclusion of any type of Local Alarm. This device helps to quickly discharge any capacitance associated with the interconnect line. If a remote active high signal is detected, the device goes into Remote Alarm and the horn will be active. RLED will be off, indicating a Remote Alarm condition. Internal protection circuitry allows the signaling unit to have higher supply voltage than the signaled unit, with- out excessive current draw. The interconnect input has a 291 ms maximum digital filter. This allows for interconnection to other types of alarms (CO, for example) that may have a pulsed interconnect signal. As a user-programmable option, the smart intercon- nect (smart IO) function can be selected. If the IO input is pulsed high twice with a nominal pulse on time greater than 37 ms and within 5.4s, a CO Alarm condi- tion is detected, and the CO temporal horn pattern will sound. The CO temporal pattern will sound at least two times, if a CO Alarm condition is detected.

3.6 Reduced Sensitivity Mode

(HUSH Mode) Upon release of PTT, the unit may or may not go into a HUSH mode, depending on the user’s selection. If the hush-in-alarm-only option is selected, then only the release of PTT in a Local Alarm condition can initi- ate a HUSH mode. Upon release of PTT, the unit is immediately reset out of alarm, and the horn is silenced. If the hush-in-alarm-only option is not selected, then anytime a release of PTT occurs, the HUSH mode is initiated. In HUSH mode, the smoke sensitivity is lowered to a pre-determined level, which is user programmable. RLED is turned on for 10 ms every 10s. The HUSH mode period is user programmable – it can be either 9 minutes or 80s. After this period times out, the unit goes back to its standby sensitivity. If the unit is currently in a HUSH mode, then PTT will test the unit with the standby sensitivity. Upon release of PTT, a new HUSH mode will be initiated. As another user-programmable option, HUSH mode can be terminated earlier by a smart hush function. This function allows the HUSH mode to be canceled by either a high smoke alarm, or a remote smoke alarm. High smoke alarm is the local smoke alarm caused by a smoke level that exceeds the reduced sensitivity level.

3.7 Alarm Memory

Alarm memory is a user-programmable option. If a unit has entered a Local Alarm, when exiting that Local Alarm, the alarm memory latch is set. The GLED can be used to visually identify any unit that had previously been in a Local Alarm condition. The GLED is pulsed on three times every 40s. Each GLED pulse is 10 ms long and 1s spaced from the next pulse. This alarm memory indication period can be 0, 24, 48 hours or no limit, depending on the user’s selection. The user will be able to identify a unit with an active alarm memory anytime by PTT. Upon start of PTT, the alarm memory indication will be activated. Depending on the user’s selection, it can be 4 Hz horn chirp, 4 Hz GLED pulse, or both. Upon release of PTT, the alarm memory latch will be reset. Anytime a release of PTT occurs, the alarm memory latch will be reset. The initial visual GLED indication is not displayed if a Low Battery condition exists.

 2011 Microchip Technology Inc. DS22275A-page 13 RE46C180

3.8 End-of-Life (EOL) Indicator

The EOL indicator is a user-programmable function. If the EOL indicator function is enabled, then approxi- mately every 15 days of continuous operation, T EOL, the circuit will read an age count stored in EEPROM, and will increment this age. After 10 years of operation, an audible indication will be given to signal that the unit should be replaced. The EOL indicator is the same as the chamber test failure warning.

3.9 Tone Pattern

The smoke alarm tone pattern can be either a temporal pattern, or a continuous pattern, depending on the user’s selection. The temporal horn pattern supports the NFPA 72 ® National Fire Alarm and Signaling Code® for emergency evacuation signals. The continuous pattern is a 70% duty cycle continuous pattern. If a CO alarm is detected through the IO, the unit will sound the CO tone pattern. The CO tone pattern con- sists of 4 horn beeps in every 5.8s. Each horn beep is 100ms long and separated by 100ms.

3.10 Horn Synchronization

The horn synchronization function is programmable by the user. In an interconnected system, if one unit goes into Local Alarm, other units will also go into Remote Alarm. The IO line is driven high by the origination local smoke unit, and stays high during the alarm. If the Horn Synchronization function is enabled, at the end of every temporal horn pattern and when the horn is off, the origination unit will drive IO low, then high again. This periodic IO pulsing high and low will cause the remote smoke units to go into and out of the Remote Alarm repeatedly. Each time a unit goes into a Remote Alarm, its timing is reset. The horn sound of all remote smoke units will be synchronized with the horn sound of the origination unit. A protection circuit ensures that the unit that goes first into a Local Alarm will be the master unit that conducts the horn synchronization. The units that go later into Local Alarm will not drive the IO line. This prevents bus contention problem. This function works with the temporal tone pattern only.

3.11 Auto Alarm Locate

Auto Alarm Locate (AAL) is also a user-programmable function. To use AAL, the horn synchronization has to be selected first. The purpose of AAL is to let users quickly find the local alarm units just by listening. The local alarm units will sound the temporal pattern without interruption. The remote alarm units will sound the pat- tern with interruption. Every four temporal patterns (or 16s), the remote units are kept silenced for one pat- tern (or 4s). The originating unit conducts the IO cycling. Every four temporal patterns the IO is driven low for one temporal pattern. In the remaining three temporal patterns, the IO is still pulsing to keep the horn synchronized. The RLED of the origination unit and other local smoke units will be turned on 10 ms every 1s. The RLED of the remote smoke units will be off.

DS22275A-page 14  2011 Microchip Technology Inc. NOTES:

 2011 Microchip Technology Inc. DS22275A-page 15 RE46C180

4.0 USER PROGRAMMING MODES

Tables 4-1 to 4-6 show the parameters for user smoke calibration. TABLE 4-1: PARAMETRIC PROGRAMMING Parametric Programming Range Resolution Standby Smoke Sensitivity (VSTD) 2.9  6.0V (Note 1)1 0 0 m V (Note 1) Hysteresis (VHYS)+ 5 0  +225 mV (Note 2) 25 mV (Note 2) HUSH Smoke Sensitivity (VHSH) -1600 mV-100 mV (Note 3) 100 mV (Note 3) CHAMBER Voltage at PTT/Chamber Test (V CHAMBER) 2.10  6.75V (Note 4) 150 mV (Note 4) Note 1: VSTD listed is based on VDD =9 V . T h e actual range is (29/90)VDD  (60/90)VDD, resolution is VDD/90. 2: VHYS is a positive offset from VSTD. The listed value is based on VDD = 9V. The actual range is +(0.5/90)VDD  +(2.25/90)VDD, resolution is (0.25/90)VDD. 3: VHSH is a negative offset from VSTD. The listed value is based on VDD = 9V. The actual range is –(16/90)VDD  –(1/90)VDD, resolution is VDD/90 4: VCHAMBER listed value is based on VDD = 9V. Actual range is (21/90)VDD  (67.5/90)VDD, resolution is (1.5/90)VDD. TABLE 4-2: STANDBY SENSITIVITY (V STD) PROGRAMMING CONFIGURATION AT V DD =9 V VSTD Register STTR [5:1] Configuration Values STTR5 STTR4 STTR3 STTR2 STTR1 V STD 00000 4.5V 00001 4.6V 00010 4.7V 00011 4.8V 00100 4.9V 00101 5.0V 00110 5.1V 00111 5.2V 01000 5.3V 01001 5.4V 01010 5.5V 01011 5.6V 01100 5.7V 01101 5.8V 01110 5.9V 01111 6.0V 10000 2.9V 10001 3.0V 10010 3.1V 10011 3.2V 10100 3.3V 10101 3.4V 10110 3.5V 10111 3.6V 11000 3.7V 11001 3.8V 11010 3.9V 11011 4.0V 11100 4.1V 11101 4.2V 11110 4.3V 11111 4.4V

DS22275A-page 16  2011 Microchip Technology Inc. TABLE 4-3: HYSTERESIS (V HYS) PROGRAMMING CONFIGURATION AT V DD =9 V VHYS Register HYTR[3:1] Configuration Values HYTR3 HYTR2 HYTR1 V HYS 00 0 150 mV 00 1 175 mV 01 0 200 mV 01 1 225 mV 10 0 50 mV 10 1 75 mV 11 0 100 mV 11 1 125 mV TABLE 4-4: HUSH SENSITIVITY (V HSH) PROGRAMMING CONFIGURATION AT V DD =9 V VHSH Register TMTR[4:1] Configuration Values TMTR4 TMTR3 TMTR2 TMTR1 VHSH 000 0 VSTD –8 0 0m V 000 1 VSTD –7 0 0m V 001 0 VSTD –6 0 0m V 001 1 VSTD –5 0 0m V 010 0 VSTD –4 0 0m V 010 1 VSTD –3 0 0m V 011 0 VSTD –2 0 0m V 011 1 VSTD –1 0 0m V 100 0 VSTD – 1600 mV 100 1 VSTD – 1500 mV 101 0 VSTD – 1400 mV 101 1 VSTD – 1300 mV 110 0 VSTD – 1200 mV 110 1 VSTD –1 1 0 0m V 111 0 VSTD – 1000 mV 111 1 VSTD –9 0 0m V TABLE 4-5: CHAMBER VOLTAGE (VCHAMBER) PROGRAMMING CONFIGURATION AT V DD =9 V VCHAMBER Register PTTR[5:1] Configuration Values PTTR5 PTTR4 PTTR3 PTTR2 PTTR1 VCHAMBER 0 0000 4.50V 0 0001 4.65V 0 0010 4.80V 0 0011 4.95V 0 0100 5.10V 0 0101 5.25V 0 0110 5.40V 0 0111 5.55V 0 1000 5.70V 0 1001 5.85V 0 1010 6.00V 0 1011 6.15V 0 1100 6.30V 0 1101 6.45V 0 1110 6.60V 0 1111 6.75V 1 0000 2.10V 1 0001 2.25V 1 0010 2.40V 1 0011 2.55V 1 0100 2.70V 1 0101 2.85V 1 0110 3.00V 1 0111 3.15V 1 1000 3.30V 1 1001 3.45V 1 1010 3.60V 1 1011 3.75V 1 1100 3.90V 1 1101 4.05V 1 1110 4.20V 1 1111 4.35V

 2011 Microchip Technology Inc. DS22275A-page 17 RE46C180

4.1 Calibration and Programming

Sixteen separate programming and Test modes are available for user customization. The T2 input is used to enter these modes and step through them. To enter these modes, after power-up, T2 must be driven to V DD and held at that level. To step through the modes, the TEST input must first be driven to V DD. T2 is then clocked. TEST has to be high when clocking T2. Any- time T2 and TEST are both driven to low, the unit will come out of these modes and go back to the normal operation mode. FEED and IO are re-configured to become Test mode inputs. A T2 clock occurs when it switches from V SS to VDD. The Test mode functions are outlined in the Table 4-7. TABLE 4-6: FEATURE PROGRAMMING Features Options Low Battery Detection Selection 6.9V 7.2V 7.5V 7.8V

10 Year End-of-Life Indicator Enable/Disable

Auto Alarm Locate Enable/Disable Horn Synchronization Enable/Disable Low Battery Hush Enable/Disable Alarm Memory Indicator at PTT: Horn Chirping Enable/Disable Alarm Memory Indicator at PTT: GLED Flashing Enable/Disable Alarm Memory Indicator at Standby Time Out Period 0/24/48 hr or no limit Alarm Memory Enable/Disable HUSH Time Out Period 9 minutes or 80s Smart HUSH Enable/Disable HUSH In Alarm Only Enable/Disable HUSH Enable/Disable Tone Select Temporal or Continuous TABLE 4-7: TEST MODE FUNCTIONS Mode Descriptions T2 Clock TEST T2 FEED IO T3 TESTOUT Note 1 Normal Operation 0 PTT/HUSH 0 FEED IO Not Used IO Dump Note 2 TM0 Speedup Mode 1 PTT/HUSH V DD CLK IO Not Used IO Dump Note 2 TM1 Load Timer for Spill 2 EOL Timer Clock V DD HUSH/LB HUSH Timer Clock Alarm Mem Timer Clock Not Used Not Used TM2 User Feature Programming

3 ProgData V DD ProgClk ProgEn Not Used Not Used

TM3 Horn Test/LED On; IO High/Low

4 HornEnB

TM4 Standby Sen Set 5 SmkCompEnB T3EnB VDD CalClk ReadReg V SEN SmkCompOut Note 5 TM5 Hyst Sen Set 6 SmkCompEnB T3EnB VDD CalClk ReadReg V SEN SmkCompOut Note 5 Note 1: After power-up, the unit is in M0, the normal operation mode. When in M0, if T2 is driven to VDD, the unit will enter TM0. 2: In M0 and TM0, the digital output TESTOUT is driven by the internal IO dump signal. 3: In TM3, if TEST = VSS, the horn is turned on. IO is in weak pull-down; If TEST = VDD, the horn is off. FEED controls IO and HB/HS. 4: Valid when TEST = VDD; 5: SmkCompOut – digital comparator output (high if DETECT < VSEN; low if DETECT > VSEN). 6: LBCompOut – digital comparator output (high if VDD < LB trip point; low if VDD > LB trip point).

DS22275A-page 18  2011 Microchip Technology Inc. TM6 HUSH Sen Set 7 SmkCompEnB T3EnB VDD CalClk ReadReg V SEN SmkCompOut Note 5 TM7 PTT/Chamber Test Set

8 SmkCompEnB

VDD CalClk ReadReg V SEN SmkCompOut Note 5 TM8 Program Calibration 9 Not Used V DD Not Used ProgEn Not Used Not Used TM9 Not Used 10 TM10 Serial Read/Write Calibration

11 ProgData V DD ProgClk ProgEn Not Used Not Used

TM12 Standby Sen Check 13 SmkCompEnB T3EnB VDD Not Used Not Used V SEN SmkCompOut Note 5 TM13 Hyst Sen Check 14 SmkCompEnB T3EnB VDD Not Used Not Used V SEN SmkCompOut Note 5 TM14 HUSH Sen Check 15 SmkCompEnB T3EnB VDD Not Used Not Used V SEN SmkCompOut Note 5 TM15 PTT/Chamber Test CHAMBER Voltage Check

16 SmkCompEnB

VDD Not Used Not Used V SEN SmkCompOut Note 5 TM16 Not Used 17 TM17 LB Test 18 Not Used V DD Not Used LB Test En RLED En Not Used LBCompOut Note 6 TM18 Serial Read/Write Feature and Calibration

19 ProgData V DD ProgClk ProgEn Not Used Serial Out

TM19 User EE Lock Bit 20 LockSetEn V DD Not used ProgEn Not Used Lock Out TABLE 4-7: TEST MODE FUNCTIONS (CONTINUED) Mode Descriptions T2 Clock TEST T2 FEED IO T3 TESTOUT Note 1: After power-up, the unit is in M0, the normal operation mode. When in M0, if T2 is driven to VDD, the unit will enter TM0. 2: In M0 and TM0, the digital output TESTOUT is driven by the internal IO dump signal. 3: In TM3, if TEST = VSS, the horn is turned on. IO is in weak pull-down; If TEST = VDD, the horn is off. FEED controls IO and HB/HS. 4: Valid when TEST = VDD; 5: SmkCompOut – digital comparator output (high if DETECT < VSEN; low if DETECT > VSEN). 6: LBCompOut – digital comparator output (high if VDD < LB trip point; low if VDD > LB trip point).

 2011 Microchip Technology Inc. DS22275A-page 19 RE46C180 FIGURE 4-1: Nominal Application Circuit for Programming.

4.2 Smoke Calibration

A separate calibration mode is entered for each mea- surement mode (Normal, Hysteresis, HUSH and PTT/Chamber Test) so that independent limits can be set for each. In all calibration modes the V SEN voltage, which repre- sents the smoke sensitivity level, can be accessed at T3 output. The SmkCompOut output voltage is the result of the comparison of DETECT and V SEN, and can be accessed at TESTOUT output. The FEED input can be clocked to cycle through the available smoke sensitivity levels. Once the desired smoke sensitivity level is reached, the IO input is pulsed low to high to store the result. The detailed procedure is described in the following steps: 1. Power up with the bias condition shown in Figure 4-1. At power-up: TEST = IO = FEED = T2 = V SS, DETECT = VDD. Now in mode M0. 2. Drive T2 input from V SS to VDD and hold at VDD to enter TM0. 3. Drive TEST from V SS to VDD and hold at VDD. 4. Apply four clock pulses to the T2 input (V DD to VSS and back to V DD) to enter in TM4 mode. This initiates the Calibration mode for the normal sensitivity setting. Drive TEST from V DD to VSS to turn on the smoke comparator and enable the T3 switch. The standby smoke sensitivity V SEN will appear at T3. The smoke comparator output will appear at TESTOUT. Clock FEED to increase or decrease the V SEN levels as needed. The IO input is pulsed low-to-high to save the result. 5. Drive TEST from V SS to V DD and hold at V DD. Apply another clock pulse to the T2 input, to enter in TM5 mode. This initiates the Calibration mode for the hysteresis setting. Drive TEST from V DD to VSS to turn on the smoke compara- tor and enable the T3 switch. The local alarm smoke sensitivity V SEN will appear at T3. The smoke comparator output will appear at TES- TOUT. Clock FEED to increase or decrease the V SEN levels as needed. The IO input is pulsed low-to-high to save the result. Battery R1 1 k TEST IO GLED CHAMBER RLED DD TESTOUT FEED GUARD2 DETECT HS HB VSS 8 9 RE 46C180 1 k V2 V3 V4 V5 V6 Monitor TESTOUT, T3 and CHAMBER GUARD1 V

DS22275A-page 20  2011 Microchip Technology Inc. 6. Drive TEST from V SS to V DD and hold at V DD. Apply another clock pulse to the T2 input, to enter in TM6 mode. This initiates the calibration mode for the HUSH sensitivity setting. Drive TEST from V DD to V SS to turn on the smoke comparator and enable the T3 switch. The HUSH smoke sensitivity VSEN will appear at T3. The smoke comparator output will appear at TESTOUT. Clock FEED to increase or decrease the V SEN levels as needed. The IO input is pulsed low-to-high to save the result 7. Drive TEST from V SS to V DD and hold at V DD. Apply another clock pulse to the T2 input to enter in TM7 mode. This initiates the calibration mode for the CHAMBER voltage at PTT/Cham- ber Test. Drive TEST from V DD to VSS to turn on the smoke comparator and enable the T3 switch. The standby smoke sensitivity VSEN will appear at T3. The smoke comparator output will appear at TESTOUT. Clock FEED to increase or decrease the CHAMBER voltages as needed. The IO input is pulsed low-to-high to save the result. 8. After sensitivity settings and CHAMBER voltage calibrations have been made, pulse IO to store all results into memory. Before this step, no settings are stored into memory.

 2011 Microchip Technology Inc. DS22275A-page 21 RE46C180 FIGURE 4-2: Timing Diagram for Smoke Calibration (Mode TM4 ~ TM8). VDD TEST VSS Min THOLD1 = 10 µs Min T SETUP2 = 100 µs Min T SETUP1 = 10 µs Min TSETUP1 = 10 µs Min T HOLD1 = 10 µs VDD VSS Min PW1= 10 µs Min PW1 = 10 µs Min T1 = 20 µs VDD FEED VSS Min PW2 = 10 ms VDD IO VSS T3 Undefined VSEN at Standby Undefined VSEN at Alarm Undefined VSEN at HUSH UndefinedVSEN at Standby Undefined (Analog Voltage) CHAMBER Undefined Chamber Voltage at Undefined (Analog Voltage) PTT/Chamber Test MODE M0 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 TM8

DS22275A-page 22  2011 Microchip Technology Inc.

4.3 Serial Read/Write Calibration

As an alternative to the steps in Section 4.2, Smoke Calibration, the sensitivity settings can be entered directly from a Serial Read/Write Calibration mode (if the system has been well characterized). To enter this mode, follow these steps: 1. Power up with the bias condition shown in Figure 4-1 to enter M0. At power-up: TEST = IO = FEED = T2 = V SS, DETECT = VDD, 2. Drive T2 input from V SS to VDD and hold at VDD to enter TM0. 3. Drive TEST from V SS to VDD and hold at VDD. 4. Apply 10 clock pulses to the T2 input (V DD to VSS and back to V DD) to enter in TM10 mode. This enables the Serial Read/Write Calibration mode. 5. TEST now acts as a data input (High = V DD, Low = VSS). FEED acts as the clock input (High = VDD, Low = VSS). Clock in the sensitivity settings. The data sequence should be as follows: 6. After all 17 bits have been entered, pulse IO to store into the EEPROM memory. 5 bit Standby Sensitivity (LSB first) 3 bit Hysteresis (LSB first) 4 bit HUSH Sensitivity (LSB first) 5 bit CHAMBER voltage in PTT/Chamber Test (LSB first)

 2011 Microchip Technology Inc. DS22275A-page 23 RE46C180 REGISTER 4-1: CALIBRATION CONFIGURATION REGISTER W-x PTTR5 bit 17 W-x W-x W-x W-x W-x W-x W-x W-x PTTR4 PTTR3 PTTR2 PTTR1 TMTR4 TMTR3 TMTR2 TMTR1 bit 16 bit 8 W-x W-x W-x W-x W-x W-x W-x W-x HYTR3 HYTR2 HYTR1 STTR5 STTR4 STTR3 STTR2 STTR1 bit 8 bit 1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 17 PTTR5: MSB (See Table 4-5) bit 16 PTTR4: 4SB bit 15 PTTR3: 3SB bit 14 PTTR2: 2SB bit 13 PTTR1: LSB bit 12 TMTR4: MSB (See Table 4-4) bit 11 TMTR3: 3SB bit 10 TMTR2: 2SB bit 9 TMTR1: LSB bit 8 HYTR3: MSB (See Table 4-3) bit 7 HYTR2: 2SB bit 6 HYTR1: LSB bit 5 STTR5: MSB (See Table 4-2) bit 4 STTR4: 4SB bit 3 STTR3: 3SB bit 2 STTR2: 2SB bit 1 STTR1: LSB

DS22275A-page 24  2011 Microchip Technology Inc. FIGURE 4-3: Timing Diagram for Mode TM10. Min THOLD1 = 10 µs VDD TEST D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D17 VSS VDD VSS Min TSETUP1 = 10 µs Min PW1 = 10 µs Min T1 = 20 µs VDD FEED VSS Min TSETUP1 = 10 µs Min T HOLD1 = 10 µs Min PW1 = 10 µs Min T3 = 30 µs VDD IO VSS Min PW2 = 10 ms MODE M0 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 TM8 TM9 TM10 TM10

 2011 Microchip Technology Inc. DS22275A-page 25 RE46C180

4.4 User Feature Selections

User feature selections can be clocked in serially using TEST as data input, and FEED, as a clock input, then stored in the internal EEPROM. The detailed steps are as follows: 1. Power up with the bias condition shown in Figure 4-1. At power-up: TEST = IO = FEED = T2 = V SS, DETECT = VDD. Now in mode M0. 2. Drive T2 input from V SS to VDD and hold at VDD to enter TM0. 3. Drive TEST from V SS to VDD and hold at VDD. 4. Apply two clock pulses to the T2 input (V DD to VSS and then back to VDD) to enter in TM2. 5. Using TEST as data and FEED as clock, shift in values of 18 bits as selected from Register 4-2. 6. After shifting in data, pull IO input to V DD, then VSS (minimum pulse-width of 10 ms) to store shift register contents in the memory. 7. If any changes are required, power down the part and return to Step 1. All bit values must be reentered. REGISTER 4-2: USER FEATURE CONFIGURATION REGISTER UW - x —L B T R 2 bit 18 bit 17 W-x W-x W-x W-x W-x W-x W-x W-x LBTR1 EOLEn COEn NoAAL SyncEn LBHshEn AMHCEn AMLEDEn bit 16 bit 8 W-x W-x W-x W-x W-x W-x W-x W-x AMTO2 AMTO1 AMEn ShrTO SmrtH HIAO HushEnB TSEL bit 8 bit 1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 18 Unimplemented: Read as ‘x’ bit 17 LBTR2: MSB bit 16 LBTR1: LSB 00 =7 . 5 V 01 =7 . 8 V 10 =6 . 9 V 11 =7 . 2 V bit 15 EOLEn: End-of-Life Indicator Enable Bit 1 = Enable 0 = Disable bit 14 COEn: CO Alarm Function (Smart IO) Enable Bit 1 = Enable 0 = Disable bit 13 NoAAL: Auto Alarm Locate Disable Bit 1 = AAL is Disabled 0 = AAL is Enabled bit 12 SyncEn: Horn Synchronization Enable Bit 1 = Enable 0 = Disable

DS22275A-page 26  2011 Microchip Technology Inc. The minimum pulse-width for FEED is 10 µs, while the minimum pulse-width for TEST is 100 µs. For example, for the following options, the sequence would be: bit 11 LBHshEn: Low Battery Hush Enable Bit 1 = Enable 0 = Disable bit 10 AMHCEn: Alarm Memory PTT Indicator Horn Chirp Enable Bit 1 = Enable 0 = Disable bit 9 AMLEDEn: Alarm Memory PTT Indicator LED Flashing Enable Bit 1 = Enable 0 = Disable bit 8 AMTO2: MSB bit 7 AMTO1: LSB 00 = 24 Hours Timeout 01 = 48 Hours Timeout 10 = 0 Hour Timeout 11 = Never Timeout bit 6 AMEn: Alarm Memory Enable Bit 1 = Enable 0 = Disable bit 5 ShrTO: HUSH Timer Time Out Select Bit 1 = 80 seconds 0 = 9 minutes bit 4 SmrtH: Smart HUSH Bit 1 = Enable (Hush is canceled by either high smoke, or remote smoke) 0 = Disable (Hush is never canceled until timeout) bit 3 HIAO: HUSH-in-Alarm -Only Bit 1 = Enable (Hush is activated upon release of PTT during local smoke only) 0 = Disable (Hush is activated upon release of PTT at anytime) bit 2 HushEnB: HUSH Enable Bit 1 = Enable (Hush is disabled) 0 = Disable (Hush is enabled) bit 1 TSEL: Tone Select Bit 1 = Continuous Tone Pattern 0 = Temporal Tone Pattern REGISTER 4-2: USER FEATURE CONFIGURATION REGISTER (CONTINUED) Data – X 1 0 1 1 1 1 0 1 Bit – 18 17 16 15 14 13 12 11 10 Data – 0 0 0 1 0 0 1 0 0 B i t –987654321 Low battery Trip Point = 6.9V End of Life Enable = Yes CO Enable = Yes Auto Alarm Locate Disable = Yes Horn Synchronization Enable = Yes Low Battery Hush Enable = No Alarm Memory PTT Indicator Horn Chirp Enable =Y e s Alarm Memory PTT Indicator LED Flashing Enable =N o Alarm memory LED indicator time out = 24 hours Alarm Memory Enable = Yes HUSH time out = 9 minutes Smart HUSH = No Hush in alarm only = Yes Hush Enable = Yes Tone Select = Temporal

 2011 Microchip Technology Inc. DS22275A-page 27 RE46C180 FIGURE 4-4: Timing Diagram for Mode TM2. Min THOLD1 = 10 µs VDD TEST D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D18 VSS VDD VSS Min TSETUP1 = 10 µs Min PW1 = 10 µs VDD FEED VSS Min TSETUP1 = 10 µs Min T HOLD1 = 10 µs Min PW1 = 10 µs Min T1 = 30 µs VDD IO VSS Min PW2 = 10 ms MODE M0 TM0 TM1 TM2 TM2

DS22275A-page 28  2011 Microchip Technology Inc.

4.5 Sensitivity Verification

After all sensitivity levels and CHAMBER voltage at PTT/Chamber Test have been entered and stored into the memory, additional Test modes are available to ver- ify if the sensitivities are functioning as expected. Table 4-8 describes several verification tests. TABLE 4-8: SENSITIVITY VERIFICATION DESCRIPTION Sensitivity Test Description Standby Sensitivity Clock T2 to Mode TM12 (12 clocks). With appropriate smoke level in the chamber, pull TEST to VSS and hold for at least 1 ms. The TESTOUT output will indicate the detection status (High = smoke detected). Hysteresis Clock T2 to Mode TM13 (13 clocks). Pulse TEST and monitor TESTOUT. HUSH Sensitivity Clock T2 to Mode TM14 (14 clocks). Pulse TEST and monitor TESTOUT. CHAMBER voltage at PTT/Chamber Test Clock T2 to Mode TM15 (15 clocks). Pulse TEST and monitor TESTOUT.

 2011 Microchip Technology Inc. DS22275A-page 29 RE46C180 FIGURE 4-5: Timing Diagram for Sensitivity Verification in Mode TM12 ~ TM15. VDD TEST VSS Min THOLD1 = 10 µs Min T SETUP1 = 10 µs Min T2 = 100 µs Min TSETUP1 = 10 µs Min THOLD1 = 10 µs VDD VSS Min PW1= 10 µs TESTOUT Undefined SmokeCmpOut Undefine SmokeCmpOut Undefine SmokeCmpOut Undefine SmokeCmpOut MODE M0 TM0 TM1 TM2 TM3 TM12 TM13 TM14 TM15

DS22275A-page 30  2011 Microchip Technology Inc.

4.6 Serial Read/Write Calibration and

As an alternative to the steps in Section 4.2, Smoke Calibration and Section 4.4, User Feature Selec- tions, the sensitivity settings and user feature selec- tions can be entered directly from a Serial Read/Write Calibration mode. To enter this mode, follow these steps: 1. Power up with the bias condition shown in Figure 4-1 to enter M0. At power-up: TEST = IO = FEED = T2 = V SS, DETECT = VDD. 2. Drive T2 input from V SS to VDD and hold at VDD to enter TM0. 3. Drive TEST from V SS to VDD and hold at VDD. 4. Apply 18 clock pulses to the T2 input (V DD to VSS and then back to V DD) to enter in TM18 mode. This enables the Serial Read/Write Calibration and User Features modes. 5. TEST now acts as a data input (High = V DD, Low = VSS). FEED acts as the clock input (High = VDD, Low = VSS). Clock in the sensitivity settings. The data sequence should be as follows: 6. After all 35 bits have been entered, pulse IO to store into the EEPROM memory. D1 ~ D18 User Features (18 bits, LSB first) D19 ~ D35 Calibration (17 bits, LSB First) REGISTER 4-3: SERIAL READ/WRITE REGISTER W-x W-x W-x PTTR5 PTTR4 PTTR3 bit 35 bit 33 W-x W-x W-x W-x W-x W-x W-x W-x PTTR2 PTTR1 TMTR4 TMTR3 TMTR2 TMTR1 HYTR3 HYTR2 bit 32 bit 25 W-x W-x W-x W-x W-x W-x U W-x HYTR1 STTR5 STTR4 STTR3 STTR2 STTR1 — LBTR2 bit 24 bit 17 W-x W-x W-x W-x W-x W-x W-x W-x LBTR1 EOLEn COEn NoAAL SyncEn LBHshEn AMHCEn AMLEDEn bit 16 bit 8 W-x W-x W-x W-x W-x W-x W-x W-x AMTO2 AMTO1 AMEn ShrTO SmrtH HIAO HushEnB TSEL bit 8 bit 1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 35 PTTR5: MSB (See Table 4-5) bit 34 PTTR4: 4SB bit 33 PTTR3: 3SB bit 32 PTTR2: 2SB bit 31 PTTR1: LSB bit 30 TMTR4: MSB (See Table 4-4)

 2011 Microchip Technology Inc. DS22275A-page 31 RE46C180 bit 29 TMTR3: 3SB bit 28 TMTR2: 2SB bit 27 TMTR1: LSB bit 26 HYTR3: MSB (See Table 4-3) bit 25 HYTR2: 2SB bit 24 HYTR1: LSB bit 23 STTR5: MSB (See Table 4-2) bit 22 STTR4: 4SB bit 21 STTR3: 3SB bit 20 STTR2: 2SB bit 19 STTR1: LSB bit 18 Unimplemented: Read as ‘x’ bit 17 LBTR2: MSB bit 16 LBTR1: LSB 00 =7 . 5 V 01 =7 . 8 V 10 =6 . 9 V 11 =7 . 2 V bit 15 EOLEn: End-of-Life Indicator Enable Bit 1 = Enable 0 = Disable bit 14 COEn: CO Alarm Function (Smart IO) Enable Bit 1 = Enable 0 = Disable bit 13 NoAAL: Auto Alarm Locate Disable Bit 1 = AAL is Disabled 0 = AAL is Enabled bit 12 SyncEn: Horn Synchronization Enable Bit 1 = Enable 0 = Disable bit 11 LBHshEn: Low Battery Hush Enable Bit 1 = Enable 0 = Disable bit 10 AMHCEn: Alarm Memory PTT Indicator Horn Chirp Enable Bit 1 = Enable 0 = Disable bit 9 AMLEDEn: Alarm Memory PTT Indicator LED Flashing Enable Bit 1 = Enable 0 = Disable bit 8 AMTO2: MSB bit 7 AMTO1: LSB 00 = 24 Hours Timeout 01 = 48 Hours Timeout 10 = 0 Hours Timeout 11 = Never Timeout bit 6 AMEn: Alarm Memory Enable Bit 1 = Enable 0 = Disable REGISTER 4-3: SERIAL READ/WRITE REGISTER (CONTINUED)

DS22275A-page 32  2011 Microchip Technology Inc. bit 5 ShrTO: HUSH Timer Time Out Select Bit 1 = 80 secondse 0 = 9 minutes bit 4 SmrtH: Smart HUSH Bit 1 = Enable (Hush is canceled by either high smoke, or remote smoke) 0 = Disable (Hush is never canceled until timeout) bit 3 HIAO: HUSH-in-Alarm-Only Bit 1 = Enable (Hush is activated upon release of PTT during local smoke only) 0 = Disable (Hush is activated upon release of PTT at anytime) bit 2 HushEnB: HUSH Enable Bit 1 = Enable (Hush is disabled) 0 = Disable (Hush is enabled) bit 1 TSEL: Tone Select Bit 1 = Continuous Tone Pattern 0 = Temporal Tone Pattern REGISTER 4-3: SERIAL READ/WRITE REGISTER (CONTINUED)

 2011 Microchip Technology Inc. DS22275A-page 33 RE46C180 FIGURE 4-6: Timing Diagram for Serial Read/Write Calibration and User Features in Mode TM18. Min THOLD1 = 10 µs VDD TEST D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D35 VSS VDD VSS Min TSETUP1 = 10 µs Min PW1 = 10 µs Min T1 = 20 µs VDD FEED VSS Min TSETUP1 = 10 µs Min T HOLD1 = 10 µs Min T PW1 = 10 µs Min T3 = 30 µs VDD IO VSS Min PW2 = 10 ms MODE M0 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM17 TM18 TM18

DS22275A-page 34  2011 Microchip Technology Inc.

4.7 Horn Test

Test mode TM3 allows the horn to be enabled indefinitely for audibility testing. To enter this mode, follow the next steps: 1. Power up with the bias condition shown in Figure 4-1 to enter M0. At power-up: TEST = IO = FEED = T2 = V SS, DETECT = VDD. 2. Drive T2 input from V SS to VDD and hold at VDD to enter TM0. 3. Drive TEST from V SS to VDD and hold at VDD. 4. Apply three clock pulses to the T2 input (V DD to VSS and then back to V DD) to enter in TM3 mode. 5. Drive TEST from V DD to VSS to enable the horn. FIGURE 4-7: Timing Diagram for Horn Test in Mode TM3. VDD Horn Enabled TEST VSS Min T1 = 20 µs VDD VSS Min TSETUP1 =1 0µ s M i n P W 1=1 0µ s MODE M0 TM0 TM1 TM2 TM3

 2011 Microchip Technology Inc. DS22275A-page 35 RE46C180

4.8 Low Battery Test

Test mode TM17 allows the low battery trip point to be tested. To enter this mode, follow these steps: 1. Power up with the bias condition shown in Figure 4-1 to enter M0. At power-up: TEST = IO = FEED = T2 = VSS, DETECT = VDD. 2. Drive T2 input from V SS to VDD and hold at VDD to enter TM0. 3. Drive TEST from V SS to VDD and hold at VDD. 4. Apply 17 clock pulses to the T2 input (V DD to VSS and then back to V DD) to enter in TM17 mode. 5. Drive IO from V SS to V DD to enable the low battery testing and turn on the RLED. Sweep VDD from high to low and monitor TESTOUT output. The TESTOUT output will indicate the Low Battery status (High = Low Battery detected). FIGURE 4-8: Timing Diagram for Low Battery Test in Mode TM17. VDD TEST VSS VDD VSS Min TSETUP1 = 10 µs Min T PW1 = 10 µs Min T1 = 20 µs VDD Low Battery Test Enabled IO VSS VDD 7.5V VDD TESTOUT VSS MODE M0 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM16 TM17 Note: Assume the 7.5V low battery trip point is selected.

DS22275A-page 36  2011 Microchip Technology Inc.

4.9 User Lock Bit Programming

Test mode TM19 allows users to program the user EE lock bit. Once the user EE lock bit is set, the pro- grammed user EE data can not be changed unless the lock bit is reset. To enter this mode, follow these steps: 1. Power up with the bias condition shown in Figure 4-1 to enter M0. At power-up: TEST = IO = FEED = T2 = V SS, DETECT = VDD. 2. Drive T2 input from V SS to VDD and hold at VDD to enter TM0. 3. Drive TEST from V SS to VDD and hold at VDD. 4. Apply 19 clock pulses to the T2 input (V DD to VSS and then back to V DD) to enter in TM19 mode. 5. Hold TEST at V DD and pulse IO once to set the lock bit and store into the EEPROM memory. 6. To reset the lock bit from Step 5, drive TEST to VSS and pulse IO once. FIGURE 4-9: Timing Diagram for User Lock Bit Programming in Mode TM19 To set user EE lock bit VDD TEST VSS VDD VSS Min TSETUP1 = 10 µs Min TPW1 = 10 µs Min T1 = 20 µs Min PW2 = 10 ms VDD IO VSS MODE M0 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM18 TM19 To reset user EE lock bit VDD TEST VSS VDD VSS Min TSETUP1 = 10 µs Min TPW1 = 10 µs Min T1 = 20 µs Min PW2 = 10 ms VDD IO VSS MODE M0 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM18 TM19

 2011 Microchip Technology Inc. DS22275A-page 37 RE46C180

5.0 APPLICATION NOTES

5.1 Standby Current Calculation

A calculation of the standby current is shown in Table 5-1, based on the following conditions:

5.1.1 FIXED I DD

The fixed IDD is the current from the constantly active internal oscillator, bias circuit and guard amplifier.

5.1.2 SMOKE CHECK

The current draw from the smoke detection circuitry during the 5 ms smoke check period.

5.1.3 LOW BATTERY CHECK

(UNLOADED) The current drawn by the low battery detection circuitry during the 10 ms unloaded low battery check period.

5.1.4 LOW BATTERY CHECK (LOADED)

The current drawn by the RLED during the 10 ms loaded low battery check period.

5.1.5 CHAMBER TEST (SMOKE CHECK)

The current drawn by the smoke detection circuitry dur- ing the 5 ms smoke check period, while the chamber is pulled low.

5.1.6 CHAMBER TEST (CHAMBER LOW)

The current drawn to pull the chamber low when the chamber test is performed.

5.1.7 END-OF-LIFE

(READING EE AND COUNTING) The current drawn to read EOL bits from EE and then increase by 1.

5.1.8 END-OF-LIFE (WRITING EE)

The current drawn to write EOL bits back to EE.

5.1.9 TOTAL CURRENT

The average total current drawn in Standby VDD =9 V LED current in loaded battery check =1 0 m A EOLEn = 1 TABLE 5-1: STANDBY CURRENT CALCULATION IDD Component Current (µA) Duration (s) Per iod (s) Factor Average Current (µA) Fixed IDD 3.8 Always Always 1 3.8 Smoke Check 9.6 0.005 10 0.0005 0.0048 Low Battery Check (unloaded) 21.4 0.01 80 0.00013 0.0028 Low Battery Check (loaded) 10000 0.01 320 3.10E-05 0.31 Chamber Test (smoke check) 9.6 0.005 320 1.60E-05 0.00015 Chamber Test (chamber low) 3.2 3.7 320 0.012 0.038 End-of-Life (reading EE and counting) 35 0.14 1310400 1.10E-07 3.74E-06 End-of-Life (writing EE) 100 0.01 1310400 7.40E-09 7.63E-07 Total 4.16

DS22275A-page 38  2011 Microchip Technology Inc.

5.2 FUNCTIONAL TIMING DIAGRAMS

Figures 5-1 to 5-8 show the timing diagrams for the smoke detector functions described in Section 3.0, Device Descriptions. FIGURE 5-1: Timing Diagram – Standby, No Alarm. Standby, No Alarm (not to Scale) TPER0 TSCT Smoke Sample (Internal Signal) TPCT1 Chamber Test (Internal Signal) TPLB1 TPLB1 Low Battery Test (Internal Signal) TON1 RLED TPLED1

 2011 Microchip Technology Inc. DS22275A-page 39 RE46C180 FIGURE 5-2: Timing Diagram – Low Battery Test Failure and Chamber Test Failure. Low Battery Test Failure (not to Scale) TPLB2 Low Battery Test (Internal Signal) THON1 HORN THPER1 TON1 RLED TPLED1 Chamber Test (not to Scale) TPCT1 Chamber Test (Internal Signal) THON1 THOF4 HORN THOF5 THPER2

DS22275A-page 40  2011 Microchip Technology Inc. FIGURE 5-3: Timing Diagram – From Standby to Local Smoke and Push-To-Test. From no alarm to local alarm then back to no alarm (not to scale) /g39/g40/g55/g40/g38/g55/g3/g33/g3/g57/g54/g40/g49 /g39/g40/g55/g40/g38/g55/g3/g31/g3/g57/g54/g40/g49 /g39/g40/g55/g40/g38/g55/g3/g33/g3/g57/g54/g40/g49 /g54/g80/g82/g78/g72/g3/g47/g72/g89/g72/g79 /g81/g82/g3/g86/g80/g82/g78/g72/g3/g68/g79/g68/g85/g80 /g86/g80/g82/g78/g72/g3/g68/g79/g68/g85/g80 /g81/g82/g3/g86/g80/g82/g78/g72/g3/g68/g79/g68/g85/g80 /g54/g80/g82/g78/g72 /g11/g44/g81/g87/g72/g85/g81/g68/g79/g3/g86/g76/g74/g81/g68/g79/g12 /g54/g80/g82/g78/g72/g3/g54/g68/g80/g83/g79/g72 /g11/g44/g81/g87/g72/g85/g81/g68/g79/g3/g54/g76/g74/g81/g68/g79/g12 /g55/g51/g40/g53/g19 /g55/g51/g40/g53/g20 /g55/g51/g40/g53/g22 /g55/g44/g50/g39/g48/g51/g20 /g55/g40/g54/g55/g50/g56/g55 /g11/g44/g50/g3/g39/g56/g48/g51/g12 Push-to-Test (not to scale) /g55/g40/g54/g55 /g54/g80/g82/g78/g72 /g11/g76/g81/g87/g72/g85/g81/g68/g79/g3/g86/g76/g74/g81/g68/g79/g12 /g54/g80/g82/g78/g72/g3/g54/g68/g80/g83/g79/g72 /g11/g76/g81/g87/g72/g85/g81/g68/g79/g3/g86/g76/g74/g81/g68/g79/g12 /g55/g51/g40/g53/g19 /g55/g51/g40/g53/g21 /g55/g51/g40/g53/g22 /g55/g44/g50/g39/g48/g51/g20 /g55/g40/g54/g55/g50/g56/g55

 2011 Microchip Technology Inc. DS22275A-page 41 RE46C180 FIGURE 5-4: Timing Diagram – Local Smoke Alarm. Local Smoke Alarm (Not to Scale) No Smoke Alarm Smoke Alarm Smoke (internal signal) THDLY1 THON2 THOF1 THOF2 HORN (Temporal Pattern) THDLY2 THON3 THOF3 HORN (Continuous Pattern) TSCT Smoke Sample (internal signal) TPER3 TPLED2 RLED TON1 IO TIODLY1

DS22275A-page 42  2011 Microchip Technology Inc. FIGURE 5-5: Timing Diagram – IO Smoke Alarm. IO Alarm (Not to Scale) TIOFILT IO as input TIODLY2 HORN (Temporal Pattern) TIODLY3 HORN (Continuous Pattern)

 2011 Microchip Technology Inc. DS22275A-page 43 RE46C180 FIGURE 5-6: Timing Diagram – Alarm Memory and HUSH Timer. Alarm Memory (not to scale) Alarm Memory Alarm, No Low Battery Alarm Memory, No Alarm, No Low Battery Alarm Memory, after 24 hour Indication RLED TON1 TPLED2 TPLED1 TPLED1 TOFLED1 TPLED5 GLED TON1 TOFLED2 TON1 TPLED4 THPER3 TAMTO HORN TEST HUSH Timer (not to scale) Alarm, No Low Battery HUSH Timer, No Alarm, No Low Battery Standby, No Alarm, No Low Battery RLED TPLED3 TTPER TPLED1 HORN TEST

DS22275A-page 44  2011 Microchip Technology Inc. FIGURE 5-7: Timing Diagram – CO Alarm. CO Alarm TIOPW1 IO as Input TIOTO1 CO Alarm (Internal Signal) THON4 THOF7 HORN THOF6 THPER4

 2011 Microchip Technology Inc. DS22275A-page 45 RE46C180 FIGURE 5-8: Timing Diagram – Horn Synchronization and AAL. Horn Synchronization and AAL no alarm alarm Smoke (internal signal) HORN TIODMP2 TIODLY4 Horn Sync IO Dump (internal signal) TPIO1 TONIO TOFIO IO TPIO2

DS22275A-page 46  2011 Microchip Technology Inc. NOTES:

 2011 Microchip Technology Inc. DS22275A-page 47 RE46C180

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend:XX...XCustomer-specific information YYear code (last digit of calendar year) YYYear code (last 2 digits of calendar year) WWWeek code (week of January 1 is week ‘01’) NNNAlphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) *This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for cus- tomer-specific information. 16-Lead Narrow SOIC (3.90 mm) Example RE46C180 V/SL 3e 1123256 16-Lead PDIP (300 mil) Example RE46C180-V/P 1123256

DS22275A-page 48  2011 Microchip Technology Inc. /g20/g25/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g39/g88/g68/g79/g3/g44/g81/g16/g47/g76/g81/g72/g3/g11/g51/g12/g3/g177/g3/g22/g19/g19/g3/g80/g76/g79/g3/g37/g82/g71/g92/g3/g62/g51/g39/g44/g51/g64 /g49/g82/g87/g72/g86/g29 /g20/g17 /g51/g76/g81/g3/g20/g3/g89/g76/g86/g88/g68/g79/g3/g76/g81/g71/g72/g91/g3/g73/g72/g68/g87/g88/g85/g72/g3/g80/g68/g92/g3/g89/g68/g85/g92/g15/g3/g69/g88/g87/g3/g80/g88/g86/g87/g3/g69/g72/g3/g79/g82/g70/g68/g87/g72/g71/g3/g90/g76/g87/g75/g76/g81/g3/g87/g75/g72/g3/g75/g68/g87/g70/g75/g72/g71/g3/g68/g85/g72/g68/g17 /g21/g17 /g134/g3/g54/g76/g74/g81/g76/g73/g76/g70/g68/g81/g87/g3/g38/g75/g68/g85/g68/g70/g87/g72/g85/g76/g86/g87/g76/g70/g17 /g22/g17 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g86/g3/g39/g3/g68/g81/g71/g3/g40/g20/g3/g71/g82/g3/g81/g82/g87/g3/g76/g81/g70/g79/g88/g71/g72/g3/g80/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85/g3/g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g17/g3/g48/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85/g3/g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g3/g86/g75/g68/g79/g79/g3/g81/g82/g87/g3/g72/g91/g70/g72/g72/g71/g3/g17/g19/g20/g19/g5/g3/g83/g72/g85/g3/g86/g76/g71/g72/g17 /g23/g17 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48/g17 /g37/g54/g38/g29 /g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g49/g82/g87/g72/g29/g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87/g3 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g56/g81/g76/g87/g86 /g44/g49/g38/g43/g40/g54 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g48/g44/g49 /g49/g50/g48 /g48/g36/g59 /g49/g88/g80/g69/g72/g85/g3/g82/g73/g3/g51/g76/g81/g86 /g49 /g20/g25 /g51/g76/g87/g70/g75 /g72 /g17/g20/g19/g19/g3/g37/g54/g38 /g55/g82/g83/g3/g87/g82/g3/g54/g72/g68/g87/g76/g81/g74/g3/g51/g79/g68/g81/g72 /g36 /g177 /g177 /g17/g21/g20/g19 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g36/g21 /g17/g20/g20/g24 /g17/g20/g22/g19/g17/g20/g28/g24 /g37/g68/g86/g72/g3/g87/g82/g3/g54/g72/g68/g87/g76/g81/g74/g3/g51/g79/g68/g81/g72 /g36/g20 /g17/g19/g20/g24 /g177 /g177 /g54/g75/g82/g88/g79/g71/g72/g85/g3/g87/g82/g3/g54/g75/g82/g88/g79/g71/g72/g85/g3/g58/g76/g71/g87/g75 /g40 /g17/g21/g28/g19/g17/g22/g20/g19/g17/g22/g21/g24 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g58/g76/g71/g87/g75 /g40/g20 /g17/g21/g23/g19/g17/g21/g24/g19/g17/g21/g27/g19 /g50/g89/g72/g85/g68/g79/g79/g3/g47/g72/g81/g74/g87/g75 /g39 /g17/g26/g22/g24 /g17/g26/g24/g24 /g17/g26/g26/g24 /g55/g76/g83/g3/g87/g82/g3/g54/g72/g68/g87/g76/g81/g74/g3/g51/g79/g68/g81/g72 /g47 /g17/g20/g20/g24 /g17/g20/g22/g19/g17/g20/g24/g19 /g47/g72/g68/g71/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g70 /g17/g19/g19/g27 /g17/g19/g20/g19 /g17/g19/g20/g24 /g56/g83/g83/g72/g85/g3/g47/g72/g68/g71/g3/g58/g76/g71/g87/g75 /g69/g20 /g17/g19/g23/g24 /g17/g19/g25/g19 /g17/g19/g26/g19 /g47/g82/g90/g72/g85/g3/g47/g72/g68/g71/g3/g58/g76/g71/g87/g75 /g69 /g17/g19/g20/g23 /g17/g19/g20/g27 /g17/g19/g21/g21 /g50/g89/g72/g85/g68/g79/g79/g3/g53/g82/g90/g3/g54/g83/g68/g70/g76/g81/g74/g3/g3/g134 /g72/g37 /g177 /g177 /g17/g23/g22/g19 N E1NOTE 1 D 12 3 A A1 b1 b e L E eB c /g48/g76/g70/g85/g82/g70/g75/g76/g83 /g55/g72/g70/g75/g81/g82/g79/g82/g74/g92 /g39/g85/g68/g90/g76/g81/g74 /g38/g19/g23/g16/g19/g20/g26/g37

 2011 Microchip Technology Inc. DS22275A-page 49 RE46C180 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS22275A-page 50  2011 Microchip Technology Inc. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

 2011 Microchip Technology Inc. DS22275A-page 51 RE46C180 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS22275A-page 52  2011 Microchip Technology Inc. NOTES:

 2011 Microchip Technology Inc. DS22275A-page 53 RE46C180 APPENDIX A: REVISION HISTORY Revision A (August 2011) Original Release of this Document.

DS22275A-page 54  2011 Microchip Technology Inc. NOTES:

 2011 Microchip Technology Inc. DS22275A-page 55 RE46C180 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device DSTEMP: CMOS Programmable Ionization Smoke Detector ASIC DSTEMPT: CMOS Programmable Ionization Smoke Detector ASIC (Tape and Reel, SOIC only) Package E = Plastic Dual In-Line, 150 mil. Body, 16-Lead (PDIP) S = Small Plastic Outline - Narrow, 3.90 mm Body, 16-Lead (SOIC) Examples: a) RE46C180E16F: 16LD PDIP Package b) RE46C180S16F: 16LD SOIC Package c) RE46C180S16TF: 16LD SOIC Package, Tape and Reel PART NO. X PackageDevice XX Number of Pins

DS22275A-page 56  2011 Microchip Technology Inc. NOTES:

 2011 Microchip Technology Inc. DS22275A-page 57 RE46C180 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-346-3 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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