SDC1740 AD | Alldatasheet
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ANALOG 12- and 14-Bit Hybrid Synchro/ DEVICES Resolver-to-Digital Converters FEATURES FUNCTIONAL BLOCK DIAGRAM Internal Isolating Transformers Military Temperature Range Three Accuracy Options oe 14-Bit or 12-Bit Resolution wmode > eR oo High, Continuous Tracking Rate yy Ke | a 32-Pin Welded Metal Package ba [as y Hermetically Sealed ude b wom Ratiometric Conversion ome rsd Laser Trimmed - No External Adjustment > ia Three-State Latched Outputs ward i ANS tion SH = |e : enema “t— Whe Military Servo Control Systems i Artillery Fire Control Systems iveerre pare Avionic Systems fe } i Antenna Monitoring 14 on sha Betas OUTPUT WORD | Sopine Gontrolers MODELS AVAILABLE . The three synchro/resolver-to-digital converters described in this j Coordinate Conversion data sheet differ primarily in the areas of resolution, accuracy ! ‘Axis Transformation z and dynamic performance as follows: CNC Machine Tooling Process Control Model SDCI740XYZ is a 14-bit converter with an overall accu- racy of 5.3 arc minutes and a resolution of 1.3 arc minutes. GENERAL DESCRIPTION Model SDCI741XYZ is # 12-bit converter with en overall accu- The SDCIRDC1740/1741/1742 are hybrid 14- or 12-bit conti- racy of #15.3 arc minutes and a resolution of 5.3 arc minutes. i pee eee ope In Si care obad de Model SDCITA2KYZ isa 12-bit converter with an over accu eae cneesris performed by 1 monolithic IC manufac: "7 Of £85 ae minutes and « resolution of 5.3 arc minutes. tured in Analog Devices proprietary BiMOS II process that Each mode! has two operating temperature range versions, those combines the advantages of CMOS logic and bipolar high accu- covering the industrial temperature range (0 to +70°C) and the vecy linear eeuts on the same chip. Internal isolating micro- military temperature range (~55°C to + 125°C). The XYZ code trunsformers are used to provide truc isolation of the signal and defines the option as follows: (X) signifies the operating temper- reference inputs. The 14 or 12-bit digital word is in a threc- ature range, (Y) signifies the reference frequency, (2) signifies State digital form available in two bytes. Using separate EN- the signal and reference voltage whether it will accept synchro ABLE inputs for the most significant 8 bits and the least ot resolver format, To ensure a high level of reliability each con- significant 6 or 4 bits not only simplifies mulplexing of more_ verter receives stringent precap vitual inspection, environmental than one device onto a single data bus, but also enables the IN- screening and final electrical test. input to be used without interrupting the operation of —_litary temperature range devices and those processed to high the tricking loop. The converters are hermetically sealed in ® selsbility screening standards (suffix B) receive further levels of 32+pin welded metal package testing and screening to ensure high levels of reliability. More information about the option codes is given under the heading Ordering Information. REV. A Information furnished by Anelog Devices is believed to be accurate and 0. , 91 cee aero mutt from ie use..NO license ie granted by implication or —_ West Coast Centra} Atlantic otherwise under any patent o patent rights of Analog Devices. 714/641-9381 214/231-5094 215/643-7790
SDC/RDC1740/1741/1742—SPECIFICATIONS tats vous: cerns speten Parameter _ | spompci | sboRDei | SDCRDCI7A | Unite | Comments Notes CONVERTER PERFORMANCE rr Accuracy 25.3 max 15.3 max £85 max arc min | 13 Tracking Rate 2 min 18 min “* revis | i4 Resolution 4 | 2 ” Bits | Output Coding Parallel | (LsB=13 0 | GLsBes3 | | Natural Binary | are min) | arc min) j i Signal & Reference Frequency | 400 i . | He Option X1Z, | 26 . ‘ kHz | Option X4Z Repeatability of Position Output | 1 |. ' | Ls 4 Bandwidth 130 | 180 bal | He 4 SIGNAL INPUT IMPEDANCE | : 90V Signal | 200 . . n Resistive Tolerance 22% | 4 26V Signal 57.7 . fs Ka + 1L.8V Signal 6 . * kn H 4 REFERENCE INPUTS | ~~ ~ Reference Voltage 114,265 | * . Vims | See Ordering Reference Impedance | | Information | SV Ref 120 . ‘ | kA | Resistive Tolerance +5% 4 26V Ref n Je . peo | 4 LBV Ref 123 ie . | xo 4 ACCELERATION CONSTANT | 56000 80000 * t wee? | Symbol K, 4 LARGE STEP RESPONSE | 85 0p "@ op - ms “TF Step for Seuting wo | 1,3 {100 max j 7Smax « ms 1 LSB of Ecror POWER LINES i ~ - +Vee 4 15V | 28 typ 35 max * [* mA Quiescent Condition 13 Vy" 15V | 28 cyp 35 max ‘ . mA Quiescent Condition 13 Vir ssv 35 typ 56 max . . mA | Quiescent Condition 43 Power Dissipetion 1.4 max . * Ww DIGITAL INPUTS INTHBIT, | ~ | i ENABLE L, ENABLE M) 1 H i V input High) 2 min | * . Vide Vi- 75 43 V (input Low) 0.7 max bd . | Vdc Vi++5V 3 1 «tapout High) 20 max i- . uA V2 43 I dnput Low) 400 max ie ‘ fs Vu=04V 3 ENABLE AND DISABLE TIME | 80 max * ° =| zy INHIBIT tT ~~ | to INHIBIT . . Time to Data Stable (after | | | j { Negative-Going Edge | | | i of INHIBIT) 640 max . ‘ | os 4 BUSY OUTPUT ~ Sense ‘Active Logic High when converter pasion ourpur changing Timing Positive going edge 50mm before change in position output. Width | | | | 400 wp \\- : » ‘ 200 min 7 ie om | ‘ 600 max ‘ * os | 4 Load | 2 min * . TIL 4 DIGITAL OUTPUTS ~ an : Voltage Levels 1 i Logic High 24 min . . | ¥ae | Vue tsvy 13 j ! Toy=—240nA Logic Low 0.4 max | * . Vde Viarsv 3 To. =9.6mA Load 6mx it TIL ee -2- REV. A
inane [sieancre | SocaDena | socanena [tas | Comme va OPERATING ‘TEMPERATURE RANGE Option SYZ Ow +70 . c ‘Option 4YZ S30 +125 . *c { DIMENSIONS TTL 10.28 Tach | See Package ry (44.2%28.9*7.1) mm Information ‘WEIGHT ~ 0.86 max ce ie 25 max grams i NOTES "Specified over the appeopriate operating temperature range and for: () £10% signal and reference amplitude variation; (b) £10% signal wd reference har- monic distortion; (c) +5% power supply variation; (d) +10% variation in reference frequency. JENABLE M ensbles most significant 8 birs. ENABLEL enables lest significant 4 bits (r 6 bits for SDC/RDC1740). 2100% tested at nominal values of power supplies, input signal voltages and operating frequency. “Guaranteed by design. *Specifications same as SDC/RDC1740. ‘**Specifications same as SDC/RDC1741. ‘Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS FVLZOGND oo cs cscs ccs ececeececeeceeect7V de CAUTION:
ORDERING INFORMATION
For full definition, the converter part number should be suf- fixed by an option code. All the standard options and their ‘option codes are shown below. For options not shown, please consult Analog Devices. SDC IMA XY ZB TL— High-Ret Processing Z=1 Signal 11.8V Reference 26V_ Synchro = Sync it Z=2 Signal 90V. Reference 115V_ Synchro Boca healer Convener Z=3 Signal 11.8V Reference 11.8V Resolver Resol Z=4 Signal 26V. Reference 26V_ Resolver Z=8 Signal 11.8V Reference 26V Resolver 1740 14-Bit Resolution, +5.3 arc min Accuracy Y= 400Hz Reference Frequency 1741=12-Bit Resolution, +15.3 arc min Accuracy Y=4 2.6kllz Reference Frequency 1742=12-Bit Resolution, 8.5 arc min Accuracy X-4 55°C to +125°C Operating Temperature Range X=5 O10 +70°C Operating Temperature Range REV. A -3-
wanes | © Ol» 1-14 Bit 1-14 (1740) Parallel output data bits. 1 @® @ | vow 1S REFLO Input pins for the reference signal. option. NIC for Synchro option. nt! @ © |aaae 19 Sz Synchro/Resolver input signals. « ® GWE © | ne 2 NK No Connection. nl @ ®@ | ow 2 NIC No Connection. «nl @ @ | we 23° CASE Should be connected to UV GND. «nl @ ® Jue m4 NIC No Connection. au! @® @|« least significant bits. vrreresance | @) @ | se nore significant bits. ror. rom i AND 1 An 4 to the output pins.
7 Nebo eight in Degrove data should not be transferred
5 11.2500 0 +Vs Main positive power supply. H red 30 OVGND Power supply ground. 8 1.4063 310 -Vs, Main negative power supply. 9 0.7031 32+, Logic power supply. Table 1. Bit Weight Table
ed] see esoven- | CONTROL bv.
- on 2.07 OrTAL OUTPUT WORD
Figure 1. Functional Diagram of the SOC/RDC1740/1741/1742 aan the ENABLE inputs has no effect on the conversion process. where @ is the angle of the synchro shaft. To understand the conversion process, then assume thatthe cur- BUSY pulse ourput.
BUSY OUTPUT . DYNAMIC PERFORMANCE ] ‘The validity of the output date is indicared by the state of the The transfer function of the converter is given below. BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at ‘TTL levels. A BUSY is initiated each time the input moves by an analog equivalent of an LSB and the internal counter is K 1st, our incremented or decremented or the INHIBIT input is released. ° (+) > —= ° ‘Typically the width of the BUSY pulse is 400ns during the posi- - tion data output updates. The trailing edge, positive to negative transition, of the BUSY pulse indicates that the position data ourput has been updated and is ready for transfer (data valid). The maximum load on the BUSY output using the trailing edge Figure 3. Transfer Function of of the BUSY pulse is 2 TTL Inads. SDCMRDC1740/1741/1742 CONNECTING THE CONVERTER ‘The power supply voltages connected to +V, and ~Vs pins Open loop gain: should be £15V and must not be reversed. The digital logic four. Ky 4ST; supply Vz, is connected to +5V. ot. St In is suggested that 2 parallel combination of a 0.1,F ceramic a aa: and a 6.8uF electrolytic capacitor is placed from each of the loop gain: three supply pins to GND. for ___1+8h ‘The pin marked CASE is connected electrically to the case este Ct R and should be taken to a convenient zero volt potential in the * system. The digital output is taken from Pin 1 through to Pin 12 for Model SDC/RDC1740 the SDC/RDC1741/1742 and Pin 1 through to Pin 14 for the Where K,=56,000 SDC/RDC1740 where Pin | is the MSB. T1=0.01 ‘The reference connections are made to REF HI and REF LO. T2=0.001525 In the case of a synchro, the signals are connected to $1, S2.and The gain and phase diagrams are shown in Figures # and 5. $3 according to the following convention: Model SDC/RDC1741/1742 Eg.ss”Emio.nnt sin wt sin @ Where K,=80,000 Eg3.s2=Faco-nin sin wt sin (0+ 120") T1=0.0087 Eses*Enzosem fin ot sin (64240") Ti=0.001569 For a resolver, the signals are connected to S1, $2, $3 and S4 The gain and phase diagrams are shown in Figures 6 and 7. according to the following convention: ACCELERATION ERROR Es,.s3=Epro-nen sin wt sin A tracking converter employing a type 2 servo loop does not Esz.sa=Epatt-azo sin wt cos @ suffer any velocity lag, however, there is an additional error due The BUSY, INHIBIT and ENABLE pins should be connected to acceleration. This additional error can be defined using the as described under the heading Data Transfer. scccleration constant K, of the converter. _ _Input Acceleration RESISTIVE SCALING OF INPUTS K,= Error in Ourput Angle A feature of these converters is that the signal and reference ‘The numerator and denominator have the same units. K, does inputs can be resistively scaled to accommodate any change of not define maximum acceleration, only the error due to accelera- input signal and reference voltages. tion, maximum acceleration is in the region of $ times the K, ‘This mcans that a standard converter can be used with a person- figure. The following is an example using the K, of the ality card in systems where a wide range of input and reference SDC1740. voltages are encountered. Acceleration of $0 revolutions sec“? with K,=56000 Note: The accuracy of the converter will be affected by the . 50x 16384 matching accuracies of resistors used for external scaling. Error in LSBs = —sgayyy— = 14.62LSBs To calculate the values of the external scaling resistors in the case of a synchro converter, add 1.11k0 per extra volt of signal in series with $1, $2 and $3 and 1k2 per extra volt of reference in series with RHI. In the case of a resolver-to-digital converter, add 2.22K00 in series with $1 and S2 per extra volt of signal and Ik0t per extra volt of reference in series with RHI. — REV. A
synchro data are manufactured by Analog Devices, some of provide a maximum power ouput of 1.5 watts, over a frequency which are listed below. If you have any questions about our range of 0 to 10kH2. products or require advice about their use for a particular appli- The DRCI745 and DRCI746 are 14- and 16-bit natural binary cation, please contact our Applications Enginecring Department. arched output hybrid digital-to-resolver converters. The accura- The SDC/RDC1767 and SDC/RDCI768 are hybrid synchro- cies availabe are 2 and 4 are mins, and the outputs can sup- to the SDC/RDC1740/41/42 described on this data sheet with the additonal features of analog velocity ourput and de error ouput. OUTLINE DIMENSIONS ‘Dimensions shown in inches and (mm). aoa Beets on. pod (SOCMRBC 1740 ornon [23 | : (——h ; ad emwasere | Eb} [ abmewme | [rte etre cuseue aa me FJ vorouvew — tone ‘Oo Pocccccocccce _ ever -8- REV. A