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Military Temperature Range vena w Ore] scan Le n300 dev. Three Accuracy Options 81 Oe] ResIsTORS | sttits 14-Bit or 12-Bit Resolution 2 $-| sien. saath a bi High, Continuous Tracking Rate sa Ge| Formers ona al 9 oe ates 32-Pin Welded Metal Package picciGan pees | ey ae Hermetically Sealed ene > doy Ratiometric Conversion ward . Laser Trimmed — No External Adjustment aaatew Oe! conor dl: ——il Three-State Latched Outputs BABE Oe] “Lue Berane oe APPLICATIONS VESTCUCUSCSTSS: Flight Instrumentation Systems Military Servo Control Systems use veal ionic Antenna Mositoriag Functional Diagram of the SDC/RDC1740/1741/1742 Robotics MODELS AVAILABLE Engine Controllers The three synchro/resolver-to-digital converters described in this Coordinate Conversion data sheet differ primarily in the areas of resolution, accuracy Axis Transformation and dynamic performance as follows: CNC Machine Tooling Model SDC1740XYZ is a 14-bit converter with an overall accu- Process Control racy of +5.3 arc minutes and a resolution of 1.3 arc minutes. GENERAL DESCRIPTION Model SDC1741XYZ is a 12-bit converter with an overall accu- The SDC/RDC1740/1741/1742 are hybrid 14- or 12-bit continu- __‘“#Y of *15.3 are minutes and a resolution of 5.3 are minutes. ous tracking synchro or resolver to digital converters contained Model SDC1742XYZ is a 12-bit converter with an overall accu- in 32-pin welded metal packages. In the core of this hybrid the racy of +8.5 arc minutes and a resolution of 5.3 arc minutes. conversion process is performed by a monolithic IC manufac- Each model has two operating temperature range versions, those tured in Analog Devices proprietary BiMOS II process that covering the industrial temperature range (0 to +70°C) and the combines the advantages of CMOS logic and bipolar high accu- military temperature range (—55°C to +125°C). The XYZ code racy linear circuits on the same chip. Internal isolating micro- defines the option as follows: (X) signifies the operating temper- transformers are used to provide true isolation of the signal and ature range, (Y) signifies the reference frequency, (Z) signifies reference inputs. The 14- or 12-bit digital word is in a three- the signal and reference voltage whether it will accept synchro state digital form available in two bytes. Using separate or resolver format. To ensure a high level of reliability each con- ENABLE inputs for the most significant 8 bits and the least verter receives stringent precap visual inspection, environmental significant 6 or 4 bits not only simplifies multiplexing of more screening and final electrical test. than one device onto a single data bus, but also enables the fe ace wnat dt hi INHIBIT input to be used without interrupting the operation of ilitary temperature range devices and those Processed to high the tracking loop. The converters are hermetically sealed in a reliability screening standards (suffix B) receive further levels of 32-pin welded metal package. testing and screening to ensure high levels of reliability. More information about the option codes is given under the heading Ordering Information. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its “ ss which may result from its use. No license is granted by implication or Tel: 617/329-4700 Twx: 710/394-6577 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cables: ANALOG NORWOODMASS
SPEC IFl CATI ONS (typical at 25°C unless otherwise specified) CONVERTER PERFORMANCE ‘Accuracy £5.3 max =15.3 max 8.5 max arc min 1,3 Tracking Rate 27 min 18 min ” revis 4 Resolution 4 | 2 ” Bits | Output Coding Parallel (I LSB=13 (LsB=5.3. | * Natural Binary arc min) | arc min) Signal & Reference Frequency | 400 | * * Hz Option X1Z 2.6 * * kHz | Option X4z Repeatability of Position Output | 1 b* * LSB 4 _ Bandwidth 130 | 150 Ls Hz 4 SIGNAL INPUT IMPEDANCE | | 90V Signal | 200 \\* * ka Resistive Tolerance +2% | 4 26V Signal [57 | * | * Ka 4 IL8V Signal {2s + [+ ka 4 REFERENCE INPUTS | | Reference Voltage 11.8, 26,115 | * * Vims | See Ordering Reference Impedance | | Information LISV Ref 120 | * * ) ko Resistive Tolerance 5% | 4 26V Ref Pa | * ka 4 11.8V Ref 12.3 | * * ka 4 ‘ACCELERATION CONSTANT | 56000 80000 [= | Symbol K, 4 LARGE STEP RESPONSE 85 typ 60 typ * 179° Step for Settling to | 1,3 100 max 75 max ” 1 LSB of Error POWER LINES | | +V5=+15V 28 typ 35 max | * * mA — | Quiescent Condition 1,3 -V5=-15V | 28 typ 35 max | * * mA | Quiescent Condition 1,3 Vi=+5V [35 typ 56 max | * * | mA — | Quiescent Condition 1,3 __Power Dissipation 14 max ~ * w DIGITAL INPUTS (INHIBIT, | | ENABLE L, ENABLE M) | V (Input High) | 2min | * * Vde | V=+5V 1,3 V (Input Low) | 0.7 max * * Vdc | V,=+5V 1,3 I (Input High) 20 max * * } pA | Vin=24V 13 1 (Input Low) | -400 max * * wA | Vy=0.4V 1,3 "ENABLE AND DISABLE Tine | max * * ns 2,4 INHIBIT Sense Logic Low * * to INHIBIT * * Time to Data Stable (after Negative-Going Edge | of INHIBIT) | 640 max * * ns 4 BUSY OUTPUT | Sense | Active Logic High when converter position output changing. Timing Positive going edge 5Ons before change in position output. Width 400 typ * * ns 1,3 200 min * * ns 1,3 600 max | * * ns 1,3 Load 2min * * TIL 4 DIGITAL OUTPUTS Voltage Levels Logic High 24 min i . Vde | Vi=+5V, 1,3 | Ton=—240HA Logic Low 0.4 max * « Vde | V.=+5V 1,3 | | To. =9.6mA Load 6 max * * TTL -2-
Parameter SDC/RDC1740 SDC/RDC1741 | SDC/RDC1742 ‘Comments Notes OPERATING TEMPERATURE RANGE Option SYZ Oto + 70 * *c Option 4YZ —55 to +125 * bo DIMENSIONS 1.74 1.14«0.28 * Inch See Package 4 (44.2x28.9x7.1) 7 mm Information WEIGHT ; 0.86 max * oz 4 25 mx Cn ncn] a NOTES ‘Specified over the appropriate operating temperature range and for: (a) +10% signal and reference amplitude variation; (b) +10% signal and reference harmonic distortion; (c) +5% power supply variation; (d) + 10% variation in reference frequency. *ENABLE M enables most significant 8 bits. ENABLE L enables least significant 4 bits (or 6 bits for SDC/RDC1740). 100% tested at nominal values of power supplies, input signal voltages and operating frequency. ‘Guaranteed by design. *Specifications same as SDC/RDC1740. **Specifications same as SDC/RDCI741. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS HV tOGND. occ e cece cece eens eee o#IT.25V de <Vgt0GND ooo eee eee c cere eee ees -=17.25V de FV,2 toGND 2... eee eee ETV de Case toGND 00... cece eee eee eee eee es -£20V de CAUTION: 'Correct polarity voltages must be maintained on the +V, and —V, pins. ?The +5V power supply must never go below GND potential. NOTE Absolute maximum ratings are those values beyond which damage to the device may occur.
ORDERING INFORMATION
For full definition, the converter part number should be suf- fixed by an option code. Alll the standard options and their option codes are shown below. For options not shown, please consult Analog Devices. SDC 174A X Y ZB T— High-Rel Processing Z=1 Signal 11.8V Reference 26V_ Synchro SDC=Synchro-to-Digital Converter i ae eV Refocas dney Bieta RDC=Resolver-to-Digital Convert Pa te py) te, Gate ee aitiaiiai aliaaie Z=4 Signal 26V Reference 26V_ Resolver Z=8 Signal 11.8V Reference 26V_ Resolver 1740=14-Bit Resolution, +5.3 are min Accuracy Y=1 400Hz Reference Frequency 1741=12-Bit Resolution, +15.3 arc min Accuracy Y=4 2.6kHz Reference Frequency 1742=12-Bit Resolution, 8.5 arc min Accuracy X=4 ~35°C to +125°C Operating Temperature Range X=5 0 to +70°C Operating Temperature Range -3-
PIN CONFIGURATION PIN FUNCTION DESCRIPTION Pin Mnemonic Description mse) ars | @) @]« 1-14 Bit 1-14 (1740) Parallel output data bits. er21 @ ® |. 1-12 Bit 1-12 (1741/1742) era] © ov eno 15 REF LO Input pins for the reference signal. ors] © @|™ 16 REF HI ors! ® @ | wen 17 S4OR NIC S4 signal input for Resolver ui option. N/C for Synchro option. ore] © ® 8 83 a7! @ @ | ennoem 19 82 Synchro/Resolver input signals. srs} @ qgebemOe. @® | enasiet 20 Sl ere] @ werte sens) @) | wre 21 NIC No Connection. arto @ | case 22. NIC No Connection. arn! @ @ | we 23 CASE Should be connected to OV GND. ari] @ @ J we 24 NIC No Connection. sevon,| "| © @}s 23 ENABLEL ENABLE L enables the 6 or 4 aru! @ @ |x least significant bits. ue rerenenceo| ©) @|= 26 ENABLEM | ENABLE M enables the 8 most ve nerenence 4! | @) @ | seenores significant bits. Logic High sets the output data bits to a high impedance state; a NOTE FOR THE SYNCHRO OPTON P17 1S Logic Low presents the data in the Nor connected ; latches to the output pins. NOTE 2 FOR THE 1741 ANO 1742 PINS 12 AND 14 a aa le 27‘ BUSY | Converter busy. A Logic High | output indicates that the output . +403 | latches are being updated and Bie Number Weteht mn Desrees data should not be transferred. ee ey 28 INHIBIT Logic Low inhibits the data 3 45.0000 transfer from the counter to the 4 22.5000 output latches. 5 11.2500 29° -+Vs Main positive power supply. 6 5.6250 30. O0VGND Power supply ground. 7 2.8125 ay iG . , 8 1.4063 s jain negative power supply. 9 0.7031 32. +V, Logic power supply. 10 0.3516 ~ ul 0.1758 12 (LSB for 1741/1742) 0.0879 1B 0.0439 14 (LSB for 1740) it 0.0220 Table |. Bit Weight Table -4-
72385678 FUNRB
Figure 1. Functional Diagram of the SDC/RDC1740/1741/1742 a the ENABLE inputs has no effect on the conversion process. where @ is the angle of the synchro shaft.
BUSY OUTPUT in series with RHI. In the case of a resolver-to-digital converter, The validity of the output data is indicated by the state of the add 2.22kQ in series with $1 and $2 per extra volt of signal and BUSY output. When the input to the converter is changing, the 1kQ per extra volt of reference in series with RHI. signal appearing on the BUSY output is a series of pulses at TTL levels. A BUSY is initiated each time the input moves by DYNAMIC PERFORMANCE . an analog equivalent of an LSB and the internal counter is The transfer function of the converter is given below. incremented or decremented or the INHIBIT input is released. Typically the width of the BUSY pulse is 400ns during the posi- tion data output updates. The trailing edge, positive to negative On asst. our transition, of the BUSY pulse indicates that the position data ° +) — ry output has been updated and is ready for transfer (data valid). 146Ts The maximum load on the BUSY output using the trailing edge of the BUSY pulse is 2 TTL loads. CONNECTING THE CONVERTER Figure 3. Transfer Function of The power supply voltages connected to +Vg and —Vg pins SDC/RDC1740/1741/1742 should be +15V and must not be reversed. The digital logic supply V;, is connected to +5V. It is suggested that a parallel combination of a 0.1.F ceramic Open loop gain: and a 6.8,F electrolytic capacitor is placed from each of the Sour _ Ky 1+ST) three supply pins to GND. On ~ S? | I¥ST2 The pin marked CASE is connected electrically to the case Closed loop gain: and should be taken to a convenient zero volt potential in the Sour _ 1+ 8ST; system. oN 14ST) 4 S? + ST, The digital output is taken from Pin 1 through to Pin 12 for RR the SDC/RDC1741/1742 and Pin 1 through to Pin 14 for the SDC/RDC1740 where Pin 1 is the MSB. Mode! SDC/RDC1740 The reference connections are made to REF HI and REF LO. Where K,=56,000 In the case of a synchro, the signals are connected to S1, $2 and T1=0.01 $3 according to the following convention: T2=0.001525 Esi-ss—Ervo-rin sin ot sin @ The gain and phase diagrams are shown in Figures 4 and 5. Es3.s2=Epvo.run sin wt sin (6+ 120°) Model SDC/RDC1741/1742 Es2.5:=Egno-ret Sin wt sin (0+240°) Where K,=80,000 For a resolver, the signals are connected to $1, $2, $3 and S4 T1=0.0087 according to the following convention: T2=0.001569 Es1.s3=Epto-rin Sin ot sin 0 The gain and phase diagrams are shown in Figures 6 and 7. Es2.s4=Eputrvo Sin wt cos @ ‘The BUSY, INHIBIT and ENABLE pins should be connected ACCELERATION ERROR as described under the heading Data Transfer. A tracking converter employing a type 2 servo loop does not suffer any velocity lag, however, there is an additional error due RESISTIVE SCALING OF INPUTS to acceleration. This additional error can be defined using the A feature of these converters is that the signal and reference sccolceetion communt Kot the converter. inputs can be resistively scaled to accommodate any change of K. = input Acceleration input signal and reference voltages. »” Error in Output Angle This means that a standard converter can be used with a person- _-_‘The numerator and denominator have the same units. K, does ality card in’eysterms where'a wide ‘fange‘of inpur'and eference not define maximum acceleration, only the error due to accelera- voltages are encountered tion, maximum acceleration is in the region of 5 times the K, : ; figure. The following is an example using the K, of the Note: The accuracy of the converter will be affected by the SDC1740. matching accuracies of resistors used for external scaling. Acceleration of 50 revolutions sec-? with K,=56000 To calculate the values of the external scaling resistors in the 50x 16384 case of a synchro converter, add 1.11kQ per extra volt of signal Error in LSBs = —xgqqq— = 14.62LSBs in series with $1, $2 and $3 and 1kQ per extra volt of reference
2 Z| > 4 \\
Figure 4. SDC/RDC1740 Gain Plot Figure 6. SDC/RDC1741/1742 Gain Plot Figure 5. SDC/RDC1740 Phase Plot Figure 7. SDC/RDC1741/1742 Phase Plot
64 . environmental conditions are available on request.
° —— ditions for SDC/RDC1740/41/42. Figure 8. SDC/RDC1740/41/42 MTBF Curve
OUTLINE DIMENSIONS OTHER PRODUCTS Dimensions shown in inches and (mm). Many other hybrid products concerned with the conversion of synchro data are manufactured by Analog Devices, some of which are listed below. If you have any questions about our ANAI products or require advice about their use for a particular appli- >| ANLOG cation, please contact our Applications Engineering Department. Meson O€VICE8 OF The SDC/RDC1767 and SDC/RDC1768 are hybrid synchro- beter detent ae to-digital converters with isolating microtransformers similar soc/noc 1740 to the SDC/RDC1740/41/42 described on this data sheet with ormion £2223 the additional features of analog velocity output and de error 8 \\_ ae output. at BRzeh | Aw toewmeen Bae, The OSCI7S8 is a hybrid sine/cosine power oscillator which can § + provide a maximum power output of 1.5 watts, over a frequency 2 of | jf, The DRCI745 and DRC1746 are 14- and 16-bit natural binary cal Le cro cases re ~T p—ca 229] (0835 ——_Jatched output hybrid digital-to-resolver converters. The accura- 1.80 (38.1) cies available are +2 and +4 arc mins, and the outputs can sup- ee ply 2VA at 7V rms. Sa il ne ee PROCESSING FOR HIGH RELIABILITY DIFERENT 00s De 20010 COLOR | (2.03 DIA. +0254) Process Conditions a, sortom view 5 |rvieso, 1. Preseal Burn In 64 hrs at +125°C 2, Precap Visual Inspection 2017 9 3, Temperature Cycling 10 Cycles, —65°C to +150°C clecccccccccccce Untess ormenwise svareo’ 4, Constant Acceleration 5000G, Y1 Plane "aoe janne) 5. Interim Electrical Tests 6. Operating Burn In 96 hours @ +125°C 7. Seal Test, Fine and Gross 1014 STANDARD PROCESSING (5YZ OPTION) 8. Final Electrical Testing Performed at Tins Tambient As part of the standard manufacturing procedure, all converters (Group A) and Trax receive the following processing: 9. External Visual Inspection 2009 Process Conditions NoTE 1, Preseal Burn In 64 hrs at +125°C ‘Test and screening data can be supplied. Further information on request. 2. Precap Visual Inspection _In-house criteria 3. Seal Test, Fine and Gross In-house criteria 4, Final Electrical Test Performed at +25°C Extended temperature range versions receive additional processing as follows: Final Electrical Test Performed at max and min operating temperatures Q Fe fey -B-