TPA3116D2_V01 TI | Alldatasheet
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Technical content
4.5 V-26 V
Capable of synchronizing to other devices GAIN/SLVGAIN control and Master /Slave setting AM2,1,0 PLIMITPower Limit PBTL Detect Copyright © 2016, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPA3116D2,TPA3118D2,TPA3130D2 SLOS708G –APRIL 2012–REVISED DECEMBER 2017 TPA3116D215-W,30-W,50-WFilter-FreeClass-DStereoAmplifierFamilyWithAM Avoidance
1 Features
1• Supports Multiple Output Configurations – 2 × 50 W Into a 4-Ω BTL Load at 21 V (TPA3116D2) – 2 × 30 W Into a 8-Ω BTL Load at 24 V (TPA3118D2) – 2 × 15 W Into a 8-Ω BTL Load at 15 V (TPA3130D2)
- Wide Voltage Range: 4.5 V to 26 V
- Efficient Class-D Operation – >90% Power Efficiency Combined With Low Idle Loss Greatly Reduces Heat Sink Size – Advanced Modulation Schemes
- Multiple Switching Frequencies – AM Avoidance – Master and Slave Synchronization – Up to 1.2-MHz Switching Frequency
- Feedback Power-Stage Architecture With High PSRR Reduces PSU Requirements
- Programmable Power Limit
- Differential and Single-Ended Inputs
- Stereo and Mono Mode With Single-Filter Mono Configuration
- Single Power Supply Reduces Component Count
- Integrated Self-Protection Circuits Including Overvoltage, Undervoltage, Overtemperature, DC- Detect, and Short Circuit With Error Reporting
- Thermally Enhanced Packages – DAD (32-Pin HTSSOP Pad Up) – DAP (32-Pin HTSSOP Pad Down)
- –40°C to 85°C Ambient Temperature Range
2 Applications
- Mini-Micro Component, Speaker Bar, Docks
- After-Market Automotive
- CRT TV
- Consumer Audio Applications
3 Description
The TPA31xxD2 series are stereo efficient, digital amplifier power stage for driving speakers up to 100 W / 2 Ω in mono. The high efficiency of the TPA3130D2 allows it to do 2 × 15 W without external heat sink on a single layer PCB. The TPA3118D2 can even run 2 × 30 W / 8 Ω without heat sink on a dual layer PCB. If even higher power is needed the TPA3116D2 does 2 × 50 W / 4 Ω with a small heat- sink attached to its top side PowerPAD. All three devices share the same footprint enabling a single PCB to be used across different power levels. The TPA31xxD2 advanced oscillator/PLL circuit employs a multiple switching frequency option to avoid AM interferences; this is achieved together with an option of either master or slave option, making it possible to synchronize multiple devices. The TPA31xxD2 devices are fully protected against faults with short-circuit protection and thermal protection as well as overvoltage, undervoltage, and DC protection. Faults are reported back to the processor to prevent devices from being damaged during overload conditions. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPA3116D2 DAD (32) 11.00 mm × 6.20 mm TPA3118D2 TPA3130D2 DAP (32) 11.00 mm × 6.20 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Application Circuit
TPA3116D2,TPA3118D2,TPA3130D2 SLOS708G –APRIL 2012–REVISED DECEMBER 2017 www.ti.com Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated Table of Contents
11.2 Receiving Notification of Documentation Updates 32
12 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision F (February 2017) to Revision G Page Changes from Revision E (September 2015) to Revision F Page Changes from Revision D (January 2015) to Revision E Page Changes from Revision C (April 2012) to Revision D Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision B (May 2012) to Revision C Page
TPA3116D2,TPA3118D2,TPA3130D2 www.ti.com SLOS708G –APRIL 2012–REVISED DECEMBER 2017 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation FeedbackCopyright © 2012–2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
32-Pin HTSSOP With PowerPAD Up TPA3116D2 Only, Top View 32-Pin HTSSOP With PowerPAD Down Top View
TPA3116D2,TPA3118D2,TPA3130D2 SLOS708G –APRIL 2012–REVISED DECEMBER 2017 www.ti.com Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated (1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to AVCC. 2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 3 FAULTZ DO General fault reporting including Over-temp, DC Detect. Open drain. FAULTZ = High, normal operation FAULTZ = Low, fault condition 4 RINP I Positive audio input for right channel. Biased at 3 V. 5 RINN I Negative audio input for right channel. Biased at 3 V. 6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. 7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers. 8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider.
9 GND G Ground
10 LINP I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 11 LINN I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC.
13 AM2 I AM Avoidance Frequency Selection
14 AM1 I AM Avoidance Frequency Selection
15 AM0 I AM Avoidance Frequency Selection
16 SYNC DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal.
17 AVCC P Analog Supply
18 PVCC P Power supply
19 PVCC P Power supply
20 BSNL BST Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL
21 OUTNL PO Negative left channel output
22 GND G Ground
23 OUTPL PO Positive left channel output
24 BSPL BST Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL
25 GND G Ground
26 BSNR BST Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR
27 OUTNR PO Negative right channel output
28 GND G Ground
29 OUTPR PO Positive right channel output
30 BSPR BST Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR
31 PVCC P Power supply
32 PVCC P Power supply
33 PowerPAD G Connect to GND for best system performance. If not connected to GND, leave floating.
TPA3116D2,TPA3118D2,TPA3130D2 www.ti.com SLOS708G –APRIL 2012–REVISED DECEMBER 2017 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation FeedbackCopyright © 2012–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) 100 kΩ series resistor is needed if maximum slew rate is exceeded.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VCC PVCC, AVCC –0.3 30 V Input voltage, VI INPL, INNL, INPR, INNR –0.3 6.3 V PLIMIT, GAIN / SLV, SYNC –0.3 GVDD+0.3 V AM0, AM1, AM2, MUTE, SDZ, MODSEL –0.3 PVCC+0.3 V Slew rate, maximum(2) AM0, AM1, AM2, MUTE, SDZ, MODSEL 10 V/ms Operating free-air temperature, TA –40 85 °C Operating junction temperature , TJ –40 150 °C Storage temperature, Tstg –40 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage PVCC, AVCC 4.5 26 V VIH High-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 2 V VIL Low-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 0.8 V VOL Low-level output voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V IIH High-level input current AM0, AM1, AM2, MUTE, SDZ, MODSEL (VI = 2 V, VCC = 18 V) 50 µA RL(BTL) Minimum load Impedance Output filter: L = 10 µH, C = 680 nF TPA3116D2, TPA3118D2 3.2 4 Ω TPA3130D2 5.6 8 RL(PBTL) Output filter: L = 10 µH, C = 1 µF TPA3116D2, TPA3118D2 1.6 TPA3130D2 3.2 4 Lo Output-filter Inductance Minimum output filter inductance under short-circuit condition 1 µH
TPA3116D2,TPA3118D2,TPA3130D2 SLOS708G –APRIL 2012–REVISED DECEMBER 2017 www.ti.com Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) For the PCB layout please see the TPA3130D2EVM user guide. (3) For the PCB layout please see the TPA3118D2EVM user guide. (4) The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high.
6.4 Thermal Information
THERMAL METRIC(1) TPA3130D2 TPA3118D2 TPA3116D2 UNITDAP(2) DAP(3) DAD(4)
32 PINS 32 PINS 32 PINS
RθJA Junction-to-ambient thermal resistance 36 22 14 °C/WψJT Junction-to-top characterization parameter 0.4 0.3 1.2 ψJB Junction-to-board characterization parameter 5.9 4.7 5.7
6.5 DC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 15 mV ICC Quiescent supply current SDZ = 2 V, No load or filter, PVCC = 12 V 20 35 mA SDZ = 2 V, No load or filter, PVCC = 24 V 32 50 ICC(SD) Quiescent supply current in shutdown mode SDZ = 0.8 V, No load or filter, PVCC = 12 V <50 µA SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 400 rDS(on) Drain-source on-state resistance, measured pin to pin PVCC = 21 V, Iout = 500 mA, TJ = 25°C 120 mΩ G Gain (BTL) R1 = 5.6 kΩ, R2 = Open 19 20 21 dB R1 = 20 kΩ, R2 = 100 kΩ 25 26 27 R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 dB R1 = 47 kΩ, R2 = 75 kΩ 35 36 37 G Gain (SLV) R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 dB R1 = 75 kΩ, R2 = 47 kΩ 25 26 27 R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 dB R1 = 100 kΩ, R2 = 16 kΩ 35 36 37 ton Turn-on time SDZ = 2 V 10 ms tOFF Turn-off time SDZ = 0.8 V 2 µs GVDD Gate drive supply IGVDD < 200 µA 6.4 6.9 7.4 V VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms 6.75 7.90 8.75 V
TPA3116D2,TPA3118D2,TPA3130D2 www.ti.com SLOS708G –APRIL 2012–REVISED DECEMBER 2017 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation FeedbackCopyright © 2012–2017, Texas Instruments Incorporated
6.6 AC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT KSVR Power supply ripple rejection 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs AC- coupled to GND –70 dB PO Continuous output power THD+N = 10%, f = 1 kHz, PVCC = 14.4 V 25 W THD+N = 10%, f = 1 kHz, PVCC = 21 V 50 THD+N Total harmonic distortion + noise VCC = 21 V, f = 1 kHz, PO = 25 W (half-power) 0.1% Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV –80 dBV Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz –100 dB SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted 102 dB fOSC Oscillator frequency AM2=0, AM1=0, AM0=0 376 400 424 kHz AM2=0, AM1=0, AM0=1 470 500 530 AM2=0, AM1=1, AM0=0 564 600 636 AM2=0, AM1=1, AM0=1 940 1000 1060 AM2=1, AM1=0, AM0=0 1128 1200 1278 AM2=1, AM1=0, AM0=1 ReservedAM2=1, AM1=1, AM0=0 AM2=1, AM1=1, AM0=1 Thermal trip point 150+ °C Thermal hysteresis 15 °C Over current trip point TPA3130D2 4.5 A TPA3118D2, TPA3116D2 7.5
6.7 Typical Characteristics
Figure 1. Total Harmonic Distortion + Noise (BTL) vs Figure 2. Total Harmonic Distortion + Noise (BTL) vs Figure 3. Total Harmonic Distortion + Noise (BTL) vs Figure 4. Total Harmonic Distortion + Noise (BTL) vs Figure 5. Total Harmonic Distortion + Noise (BTL) vs Figure 6. Total Harmonic Distortion + Noise (BTL) vs Output
+ – SDZ MUTE TTL Buffer Gain Control GAIN OUTPR_FB RINP RINN Gain Control OUTPNR_FB FAULTZ SYNC GAIN/SLV AM<2:0> PLIMIT AVCC GVDD LDO Regulator LINP LINN GND Input Sense PBTL Select OUTPL_FB Gain Control OUTNL_FB AVDD GVDD PLIMIT Reference Ramp Generator Biases and References Startup Protection Logic SC Detect DC Detect Thermal Detect UVLO/OVLO PVCC GVDD PVCC Gate Drive OUTNL_ FB PVCCGVDD PVCC Gate Drive PWM Logic Modulation and PBTL Select OUTPL_FB GND OUTPL BSPL GND OUTNL BSNL GND BSNR OUTPR GND OUTNR OUTNR_ FB BSPR OUTPR_FB PVCCGVDD PVCC Gate Drive PVCCGVDD PVCC Gate Drive PWM Logic Modulation and PBTL Select PLIMIT PLIMIT Thermal Pad PVCCPVCC Copyright © 2016, Texas Instruments Incorporated TPA3116D2,TPA3118D2,TPA3130D2 www.ti.com SLOS708G –APRIL 2012–REVISED DECEMBER 2017 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation FeedbackCopyright © 2012–2017, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TPA31xxD2 device is a highly efficient Class D audio amplifier with integrated 120m Ohms MOSFET that allows output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio performance without the need for a bulky heat sink. The device can be configured for either master or slave operation by using the SYNC pin. This helps to prevent audible beats noise.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Gain Setting and Master and Slave
The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state and gain:
(1) Resistor tolerance should be 5% or better. Table 1. Gain and Master/Slave Figure 27. Gain, Master/Slave logic levels with compliance to GVDD.
7.3.2 Input Impedance
If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. times lower capacitors can used – for example, a 1 µF can be used. Table 2. Recommended Input AC-Coupling Capacitors
Figure 28. Input Impedance polarized type is used the positive connection should face the input pins which are biased to 3 Vdc.
7.3.3 Startup and Shutdown Operation
unconnected, because amplifier operation would be unpredictable. selected and cannot be changed until the next power-up.
7.3.4 PLIMIT Operation
ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode. Figure 29. Power Limit Example can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.
(1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms.
- POUT (10% THD) = 1.25 × POUT (unclipped)
- RL is the load resistance.
- RS is the total series resistance including RDS(on), and output filter resistance.
- VP is the peak amplitude
- VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP (2)
Table 3. Power Limit Example
7.3.5 GVDD Supply
by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩ or more.
7.3.6 BSPx AND BSNx Capacitors
7.3.7 Differential Inputs
transient performance, the impedance seen at each of the two differential inputs should be the same. which can result in pop if the input components are not well matched.
7.3.8 Device Protection System
Table 4. Fault Reporting
7.3.9 DC Detect Protection
changing the state of the outputs to Hi-Z. negative inputs to avoid nuisance DC detect faults. above the voltage listed in the table for more than 420 ms to trigger the DC detect. Table 5. DC Detect Threshold
7.3.10 Short-Circuit Protection and Automatic Recovery Feature
The TPA31xxD2 family has protection from over current conditions caused by a short circuit on the output stage. the SDZ pin through the low state.
Figure 30. MUTE Driven by Inverted FAULTZ Figure 31. Timing Requirement for SDZ
7.3.11 Thermal Protection
Thermal protection faults are reported on the FAULTZ terminal as a low state.
7.3.12 Device Modulation Scheme
7.3.12.1 MODSEL = GND: BD-Modulation
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage. speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages. reduces any I2R losses in the load.
Figure 32. BD Mode Modulation
7.3.12.2 MODSEL = HIGH: 1SPW-modulation
through the rising output. The result is that only one output is switching during a majority of the audio cycle. care is taken in the selection of the filter components and type of filter used.
Figure 33. 1SPW Mode Modulation
TPA3116D2,TPA3118D2,TPA3130D2 www.ti.com SLOS708G –APRIL 2012–REVISED DECEMBER 2017 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation FeedbackCopyright © 2012–2017, Texas Instruments Incorporated
7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3116D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
7.3.14 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3116D2 amplifier it is possible to design a high efficiency class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the class-D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz. Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3130D2 can be seen in the TPA3130D2EVM user guide SLOU341. A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best. Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to ground. Suggested values for a simple RC series snubber network would be 18 Ω in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the GND pins on the IC.
Figure 34. TPA311xD2 Radiated Emissions
7.3.15 When to Use an Output Filter for EMI Suppression
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. second order Butterworth filter similar to those shown in the figures below can be used. low frequency ferrite material can also be effective at preventing line conducted interference.
Figure 35. TPA31xxD2 Output Filters
7.3.16 AM Avoidance EMI Reduction
switching frequency being demodulated by the AM radio. Table 6. AM Frequencies
7.4 Device Functional Modes
7.4.1 Mono Mode (PBTL)
- Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during power up.
- Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative pin.
- Analog input signal is applied to INPR and INNR.
Figure 36. Mono Mode
TPA3116D2,TPA3118D2,TPA3130D2 www.ti.com SLOS708G –APRIL 2012–REVISED DECEMBER 2017 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation FeedbackCopyright © 2012–2017, Texas Instruments Incorporated
8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes a 2.1 Master and Slave application. The Master is configured as stereo outputs and the Slave is configured as mono PBTL output.
8.2 Typical Application
A 2.1 solution, U1 TPA3116D2 in Master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in Slave, PBTL mode gain of 20 dB. Inputs are connected for differential inputs.
2 L10 10uH
Figure 37. Schematic
TPA3116D2,TPA3118D2,TPA3130D2 www.ti.com SLOS708G –APRIL 2012–REVISED DECEMBER 2017 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Submit Documentation FeedbackCopyright © 2012–2017, Texas Instruments Incorporated Typical Application (continued)
8.2.1 Design Requirements
DESIGN PARAMETERS EXAMPLE VALUE Input voltage range PVCC 4.5 V to 26 V PWM output frequencies 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz Maximum output power 50 W
8.2.2 Detailed Design Procedure
The TPA31xxD2 family is a very flexible and easy to use Class D amplifier; therefore the design process is straightforward. Before beginning the design, gather the following information regarding the audio system.
- PVCC rail planned for the design
- Speaker or load impedance
- Maximum output power requirement
- Desired PWM frequency
8.2.2.1 Select the PWM Frequency
Set the PWM frequency by using AM0, AM1 and AM2 pins.
8.2.2.2 Select the Amplifier Gain and Master/Slave Mode
In order to select the amplifier gain setting, the designer must determine the maximum power target and the speaker impedance. Once these parameters have been determined, calculate the required output voltage swing which delivers the maximum output power. Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the required output swing for maximum power. The analog gain and master/slave mode can be set by selecting the voltage divider resistors (R1 and R2) on the Gain/SLV pin.
8.2.2.3 Select Input Capacitance
Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors should be a low ESR type because they are being used in a high-speed switching application.
8.2.2.4 Select Decoupling Capacitors
Good quality decoupling capacitors need to be added at each of the PVCC inputs to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors. Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order to minimize series inductances.
8.2.2.5 Select Bootstrap Capacitors
Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.22-μF, 25-V capacitors of X5R quality or better.
8.2.3 Application Curves
Figure 38. Total Harmonic Distortion + Noise (BTL) vs Figure 39. Total Harmonic Distortion + Noise (BTL) vs
9 Power Supply Recommendations
external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply. been sized to provide current necessary for internal functions but not for external loading.
10 Layout
10.1 Layout Guidelines
circuit board. The following suggestions will help to meet EMC requirements.
- Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should be placed near the TPA3116D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to the PVCC connections at each end of the chip.
- Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
- Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at the IC GND, which should be used as a central ground connection or star ground for the TPA3116D2.
- Output filter — The ferrite EMI filter (see Figure 35) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded.
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10.2 Layout Example
Figure 40. Layout Example Top
Figure 41. Layout Example Bottom
3 EDGES AFTER
10.3 Heat Sink Used on the EVM
heat sink with three fins (see drawing below). For additional information on the heat sink, go to www.qats.com. Figure 42. EVM Heatsink airflow will lower the requirement for the heat sink size and smaller types can be used.
11 Device and Documentation Support
11.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 7. Related Links
11.2 Receiving Notification of Documentation Updates
that has changed (if any). For change details, check the revision history of any revised document.
11.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 15-Nov-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPA3116D2DAD ACTIVE HTSSOP DAD 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA 3116 TPA3116D2DADR ACTIVE HTSSOP DAD 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA 3116 TPA3118D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118 TPA3118D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118 TPA3130D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130 TPA3130D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 15-Nov-2017 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPA3116D2, TPA3118D2 :
- Automotive: TPA3116D2-Q1 , TPA3118D2-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 9-Jun-2019 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3116D2DADR HTSSOP DAD 32 2000 350.0 350.0 43.0 TPA3118D2DAPR HTSSOP DAP 32 2000 350.0 350.0 43.0 TPA3130D2DAPR HTSSOP DAP 32 2000 350.0 350.0 43.0 PACKAGE MATERIALS INFORMATION www.ti.com 9-Jun-2019 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C TYP8.3 7.9 30X 0.65 32X 0.30 0.19 9.75 (0.15) TYP 0 - 8 0.15 0.05 1.2 1.0 4.36 3.26 4.11 3.31 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 11.1 10.9 B 6.2 6.0 PowerPAD TSSOP - 1.2 mm max heightDAD0032A PLASTIC SMALL OUTLINE 4222646/A 12/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. PowerPAD is a trademark of Texas Instruments. TM 1 32
0.1 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.600
www.ti.com EXAMPLE BOARD LAYOUT (7.5)
0.05 MAX
0.05 MIN
32X (1.5) 32X (0.45) 30X (0.65) (R ) TYP0.05 PowerPAD TSSOP - 1.2 mm max heightDAD0032A PLASTIC SMALL OUTLINE 4222646/A 12/2015 SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE SCALE:8X 16 17 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. TM METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 32X (1.5) 32X (0.45) (7.5) 30X (0.65) (R ) TYP0.05 PowerPAD TSSOP - 1.2 mm max heightDAD0032A PLASTIC SMALL OUTLINE 4222646/A 12/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X SYMM SYMM 16 17
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. TSSOP - 1.2 mm max height TM PowerPADDAP 32 PLASTIC SMALL OUTLINE8.1 x 11, 0.65 mm pitch 4225303/A
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