RD38F1020W0YBQ0

251407-13 NUMONYX | Alldatasheet

Document overview

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• PDF pages: 46

Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Nomenclature
• 1.2 Conventions
• 2.0 Functional Overview
• 2.1 Block Diagram
• 2.2 Flash Memory Map and Partitioning
• 3.0 Package Information
• 4.0 Ballout and Signal Description
• 4.1 Signal Ballout
• 4.2 Signal Descriptions
• 5.0 Maximum Ratings and Operating Conditions
• 5.1 Absolute Maximum Ratings
• 5.2 Operating Conditions
• 5.3 Capacitance
• 6.0 Electrical Specifications
• 6.1 DC Characteristics
• 7.0 AC Characteristics
• 7.1 Flash AC Characteristics
• 7.2 SRAM AC Characteristics
• 7.3 PSRAM AC Characteristics
• 7.4 Device AC Test Conditions
• 8.0 Flash Power Consumption
• 9.0 Device Operation
• 9.1 Bus Operations
• 10.0 Flash Command Definitions
• 11.0 Flash Read Operations
• 12.0 Flash Program Operations
• 13.0 Flash Erase Operations
• 14.0 Flash Security Modes
• 15.0 Flash Read Configuration Register
• 16.0 SRAM Operations
• 16.1 Power-up Sequence and Initialization
• 16.2 Data Retention Mode
• 17.0 PSRAM Operations
• 17.1 Power-Up Sequence and Initialization
• 17.2 Standby Mode/ Deep Power-Down Mode
• 17.3 PSRAM Special Read and Write Constraints

Order Number: 251407-13 November 2007 Numonyx™ Wireless Flash Memory (W18/W30 SCSP) 32WQ and 64WQ Family with Asynchronous RAM Datasheet Product Features „ Device Architecture — Flash Density: 32-Mbit, 64-Mbit — Async PSRAM Density: 16-Mbit, 32-Mbit — Top, Bottom or Dual flash parameter configuration „ Device Voltage — Flash VCC = 1.8 V; Flash VCCQ = 1.8 V or 3.0 V — RAM VCC = 1.8 V or 3.0 V „ Device Packaging — 88 balls (8 x 10 active ball matrix) — Area: 8x10 mm — Height: 1.2 mm to 1.4 mm „ PSRAM Performance — 70 ns initial access, 25 ns async page reads at

1.8 V I/O

— 70 ns initial access async PSRAM at 1.8 V I/O — 70 ns initial access, 25 ns async page reads at 3.0 V I/O „ SRAM Performance — 70 ns initial access at 1.8 V or 3.0 V I/O „ Quality and Reliability — Extended Temperature: –25 °C to +85 °C — Minimum 100K flash block erase cycle — 90 nm ETOX™ IX flash technology — 130 nm ETOX™ VIII flash technology „ Flash Performance — 65 ns initial access at 1.8 V I/O — 70 ns initial access at 3.0 V I/O — 25 ns async page at 1.8 V or 3.0 V I/O — 14 ns sync reads (t CHQV) at 1.8 V I/O — 20 ns sync reads (t CHQV) at 3.0 V I/O — Enhanced Factory Programming: 3.10 µs/Word (Typ) „ Flash Architecture — Read-While-Write/Erase — Asymmetrical blocking structure — 4-KWord parameter blocks (Top or Bottom) — 32-KWord main blocks — 4-Mbit partition size — 128-bit One-Time Programmable (OTP) Protection Register — Zero-latency block locking — Absolute write protection with block lock using F-VPP and F-WP# „ Flash Software — Numonyx™ Flash Data Integrator (FDI) and Common Flash Interface (CFI)

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LLegal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear f acility applications. Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights tha t relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implie d, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com . Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Numonyx B.V., All Rights Reserved.

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Order Number: 251407-13 5 32WQ and 64WQ Family with Asynchronous RAM

Revision History

June 2003 -001 Initial release September 2003 -002 Changed PSRAM Read values. Added new Transient Equivalent Testing Load Circuit figure. General text edits. May 2004 -006 Reformatted the datasheet and moved sections around according to the new layout. August 2004 -007 Added 90 nm product information. Added line items. Added DC and AC specs for the new line items and edits to related sections. January 2005 -008 Added line items. Added 32WQ product information. June 2005 -009 Added line items. October 2005 -010 Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode) specification Updated Ordering Information June 2007 -011 Updated Ordering information with active and retired line items. Updated AC spec & power-up specs for 38F2030W0YxQE & 38F2040W0YxQE August 2007 -012 Rempved 38F2030W0YxQE & 38F2040W0YxQE Line Items Updated ordering information November 2007 13 Applied Numonyx branding.

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32WQ and 64WQ Family with Asynchronous RAM

1.0 Introduction

This document contains information pertaining to the products in the Numonyx™ Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM. The W18/ W30 SCSP 32WQ and 64WQ families offer a wide variety of stacked combinations that include single flash die, two flash die, flash + PSRAM, and flash + SRAM options. This document provides information where this SCSP family differs from the Numonyx Wireless Flash Memory (W18/W30) discrete device. Refer to the discrete datasheets Numonyx™ Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx™ Wireless Flash Memory (W30) Datasheet (order number 290702) for flash product details not included in this SCSP datasheet. The Numonyx Wireless Flash Memory (W18/W30 SCSP) family offers various flash plus static RAM combinations in a common package footprint. The flash memory features

1.8 V low-power operations with flexible, multi-partition, dual-operation Read-While-

Write / Read-While-Erase, asynchronous, and synchronous reads. This SCSP device integrates up to two flash die, and one PSRAM or SRAM die in a low-profile package compatible with other SCSP families with QUAD+ ballout.

1.1 Nomenclature

CFI Common Flash Interface CUI Command User Interface DU Don’t Use ETOX EPROM Tunnel Oxide FDI Numonyx™ Flash Data Integrator (software solution) K(noun) 1 thousand Kb 1024 bits KB 1024 bytes Kword 1024 words M (noun) 1 million Mb 1,048,576 bits MB 1,048,576 bytes OTP One-Time Programmable PLR Protection Lock Register PR Protection Register PRD Protection Register Data RCR Read Configuration Register

Order Number: 251407-13 7 32WQ and 64WQ Family with Asynchronous RAM RFU Reserved for Future Use SCSP Stacked Chip Scale Package SR Status Register SRD Status Register Data Word 16 bits WSM Write State Machine

1.2 Conventions

Group Membership Brackets: Square brackets are used to designate group membership or to define a group of signals with a similar function, such as A[21:1] and SR[4,1]. VCC vs. VCC: When referring to a signal or package-connection name, the notation used is VCC, etc. When referring to a timing or electrical level, the notation used is subscripted such as V CC, etc. Device: This term is used interchangeably throughout this document to denote either a particular die, or the combination of multiple die within a single package. F[3:1]-CE#, F[2:1]-OE#: This is the method used to refer to more than one chip- enable or output enable at the same time. When each is referred to individually, the reference will be F1-CE# and F1-OE# (for die #1), and F2-CE# and F2-OE# (for die #2). F-VCC, P-VCC or S-VCC: When referencing flash memory signals or timings, the notation used is F-VCC or F-VCC, respectively. When the reference is to PSRAM signals or timings, the notation is prefixed with “P-” (e.g., P-VCC, P-VCC). When referencing SRAM signals or timings, the notation is prefixed with “S-” (e.g., S-VCC or S-VCC). P- VCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM. R-OE#, R-LB#, R-UB#, R-WE#: These are used to identify RAM OE#, LB#, UB#, WE# signals, and are usually shared between 2 or more RAM die. R-OE#, R-LB#, R- UB# and R-WE are RFU for stacked combinations that do not include PSRAM or SRAM.

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32WQ and 64WQ Family with Asynchronous RAM

2.0 Functional Overview

This section provides an overview of the features and capabilities of the Numonyx Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM device. The W18/W30 SCSP device provides flash + RAM die combinations. Products range from single flash die, two flash die, flash + PSRAM, or flash + SRAM. You can choose a W18 SCSP device or a W30 SCSP device with SRAM or PSRAM offered with the same package footprint and signal ballout.

2.1 Block Diagram

Show here are all internal package connections for the SCSP family with multiple die. See Table 21, “Ordering Information on Active Line Items” on page 40 for valid combinations of flash and RAM die. Unused connections on combinations with less than three die are reserved and should not be used. Please contact your local Numonyx representative for details regarding any reserved or RFU pins. Figure 1: Block Diagram Flash Die #2 32- or 64-Mbit W18/W30 RAM Die 4-, 8-, 16-Mbit SRAM or 16- or 32-Mbit PSRAM Flash Die #1 32- or 64-Mbit W18/W30 F2-VCC S-VCC/P-VCC F2-CE# F2-OE# R-WE# R-UB# R-LB# S-CS2 VSS F1-VCC F1-CE# F1-OE# A[MAX:0] P-CS#/S-CS1# R-OE# A[MAX:0] D[15:0] CLK F-WP# ADV# F-RST# F-WE# VCCQ F-VPP WAIT P-MODE

Order Number: 251407-13 9 32WQ and 64WQ Family with Asynchronous RAM

2.2 Flash Memory Map and Partitioning

Consult the latest Numonyx™ Wireless Flash Memory (W18) Datasheet (order number 290701) and the Numonyx™ Wireless Flash Memory (W30) Datasheet (order number 290702), for individual flash die memory map and partitioning information. Table 1 and Table 2 show memory map and partitioning information for dual-flash memory die configurations. Flash Die #1 (with F1-CE# as its Chip Select) is configured as a bottom parameter while Flash Die #2 (with F2-CE# as its Chip Select) is configured as top parameter.

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3.0 Package Information

The following two packages are offered with the 32WQ and 64WQ Family. Figure 2: Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm) M illimeters Inches Di mens i ons S ymbol Mi n Nom Max Notes Min Nom Max Package Height A 1.200 0.0472 Ball Height A1 0.200 0.0079 Package Body Thickness A2 0.860 0.0339 Pitch e 0.800 0.0315 Ball (Lead) Count N 88 88 Seating Plane Coplanarity Y 0.100 0.0039 Top View - Ball Down Bottom View - Ball Up A D E Y Drawing not to scale. A C B E D G F J H K L M e 12345678 b A C B E D G F J H K L M A1 Index Mark 123 456 78

Order Number: 251407-13 11 32WQ and 64WQ Family with Asynchronous RAM Figure 3: Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm) M illimeters Inches Dimensions Symbol Min Nom Max Notes Min Nom Max Package Height A 1.400 0.0551 Ball Height A1 0.200 0.0079 Package Body Thickness A2 1.070 0. 0421 Pitch e 0.800 0.0315 Ball (Lead) Count N 88 88 Seating Plane Coplanarity Y 0.100 0.0039 Top View - Ball Down Bottom View - Ball Up A D E Y Drawing not to scale. A C B E D G F J H K L M e 12345678 b A C B E D G F J H K L M Index Mark 12 345 678

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32WQ and 64WQ Family with Asynchronous RAM Table 1: 64-Mbit Flash + 32-Mbit Flash Die W18/W30 SCSP Memory Map and Partitioning Partitioning Block Size (KW) Block # Address Range Flash Die #2 (32-Mbit) Top Parameter Parameter Partition Partition 0 4 63-70 1F8000-1FFFFF 32 56-62 1C0000-1F7FFF Main Partitions Partition 1 32 48-55 180000-1BFFFF Partition 2 32 40-47 140000-17FFFF Partition 3 32 32-39 100000-13FFFF Partitions 4-7 32 0-31 000000-0FFFFF Flash Die #1 (64-Mbit) Bottom Parameter Main Partitions Partitions 8-15 32 71-134 200000-3FFFFF Partitions 4-7 32 39-70 100000-1FFFFF Partition 3 32 31-38 0C0000-0FFFFF Partition 2 32 23-30 080000-0BFFFF Partition 1 32 15-22 040000-07FFFF Parameter Partition Partition 0 32 8-14 008000-03FFFF 4 0-7 000000-007FFF Table 2: 64-Mbit Dual-Flash Die W18/W30 SCSP Memory Map and Partitioning Partitioning Block Size (KW) Block # Address Range Flash Die #2 (64-Mbit) Top Parameter Parameter Partition Partition 0 4 127-134 3F8000-3FFFFF 32 120-126 3C0000-3F7FFF Main Partitions Partition 1 32 112-119 380000-3BFFFF Partition 2 32 104-111 340000-37FFFF Partition 3 32 96-103 300000-33FFFF Partitions 4-7 32 64-95 200000-2FFFFF Partitions 8-15 32 0-63 000000-1FFFFF Flash Die #1 (64-Mbit) Bottom Parameter Main Partitions Partitions 8-15 32 71-134 200000-3FFFFF Partitions 4-7 32 39-70 100000-1FFFFF Partition 3 32 31-38 0C0000-0FFFFF Partition 2 32 23-30 080000-0BFFFF Partition 1 32 15-22 040000-07FFFF Parameter Partition Partition 0 32 8-14 008000-03FFFF 4 0-7 000000-007FFF

Order Number: 251407-13 13 32WQ and 64WQ Family with Asynchronous RAM

4.0 Ballout and Signal Description

4.1 Signal Ballout

Figure 4 shows the 32WQ and 64WQ W18/W30 SCSP family 88-ball (8x10 active ball matrix) device. Figure 4: 88-Ball (8x10 Active Ball Matrix) QUAD+ Ballout Pin 1 12345678 A DU DU DU DU A B A4 A18 A19 VSS F1-VCC F2-VCC A21 A11 B C A5 R-LB# A23 VSS S-CS2 CLK A22 A12 C D A3 A17 A24 F-VPP R-WE# P1-CS# A9 A13 D E A2 A7 A25 F-WP# ADV# A20 A10 A15 E F A1 A6 R-UB# F-RST# F-WE# A8 A14 A16 F G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G H R-OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H J S-CS1# F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J K F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode/ P-CRE K L VSS VSS VCCQ F1-VCC VSS VSS VSS VSS L M DU DU DU DU M 12345678 Top View - Ball Side Down SRAM/PSRAM Specific De-Populated Balls Global Signals Legend: Do Not Use Flash Specific

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM

4.2 Signal Descriptions

Table 3: Signal Descriptions (Sheet 1 of 2) Symbol Type Name and Function A[21:0] Input ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are internally latched during write operations.

• 4-Mbit: A[17:0]
• 8-Mbit: A[18:0]
• 16-Mbit: A[19:0]
• 32-Mbit: A[20:0]
• 64-Mbit: A[21:0] A0 is the lowest-order word address. A[25:22] denote high-order addresses reserved for future device densities D[15:0] Input/ Output DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data are internally latched during writes. CLK Input FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in synchronous-read mode. During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. ADV# Input FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. WAIT Output FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0]. WAIT is High-Z whenever the flash die is deselected (CE# = V IL). WAIT is not gated by OE#. WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. F[3:1]-CE# Input FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are placed in High-Z. F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash die. S-CS1# S-CS2 Input SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are deasserted (S-CS1# = V IH and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die. P[2:1]-CS# Input PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels. P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This ball is RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without PSRAM or with a single PSRAM. F[2:1]-OE# Input FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables the flash output buffers, and places the flash outputs in High-Z. F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and is available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations with only one flash die. R-OE# Input RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high disables the RAM output buffers, and places the RAM outputs in High-Z. R-OE# is only available on SCSP combinations with RAM die.

Order Number: 251407-13 15 32WQ and 64WQ Family with Asynchronous RAM R-UB# R-LB# Input RAM UPPER/ LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM high-order bytes on D[15:8], and R-LB#-low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are only available on SCSP combinations with either SRAM die or PSRAM die. F-WE# Input FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data are latched on the rising edge of WE#. R-WE# Input RAM WRITE ENABLE: Low-true; R-WE# controls writes to the RAM die. R-WE# is only available on SCSP combinations with RAM die. F-WP# Input FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of the flash die. WP#-low enables the lock-down mechanism- locked down blocks cannot be unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. F-RST# Input FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations. RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode. F-VPP F-VPEN Power FLASH PROGRAM/ ERASE POWER: A valid F-VPP voltage on this ball enables flash program/erase operations. Flash memory array contents cannot be altered when F-VPP(VPEN) < VPPLK(VPENLK). Erase/ program operations at invalid F-VPP(VPEN) voltages should not be attempted. Refer to the flash discrete product datasheet for additional details. F-VPEN (Erase/Program/Block Lock Enables) is not available for W18/W30 products. P-MODE Input PSRAM MODE: Low-true; P-MODE is used to enter/exit low power mode. Low power mode is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0. P-Mode is only available on SCSP combinations with PSRAM die. F[2:1]-VCC Power FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2 and #3. Write operations are inhibited when F-V CC < VLKO. Device operations at invalid F-VCC voltages should not be attempted. F2-VCC is only available on SCSP combinations with two or three flash die, and is RFU on SCSP combinations with only one flash die. S-VCC Power SRAM Power Supply: Supplies power to the SRAM die. S-VCC is only available on SCSP combinations with SRAM die. P-VCC Power PSRAM Power Supply: Supplies power to the PSRAM die. P-VCC is only available on SCSP combinations with PSRAM die. VCCQ Power FLASH OUTPUT-BUFFER POWER: Supplies power for the I/O output buffers. VSS Power Ground: Connect to ground. Do not float any VSS connection. RFU — Reserved for Future Use: Reserve for future device functionality/ enhancements. DU — Don’t Use: Do not connect to any other signal, or power supply; must be left floating. Table 3: Signal Descriptions (Sheet 2 of 2) Symbol Type Name and Function

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32WQ and 64WQ Family with Asynchronous RAM

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only.

5.2 Operating Conditions

Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design. Table 4: Absolute Maximum Ratings Parameter Min Max Unit Notes Temperature under Bias Extended –25 +85 °C 7 Storage Temperature –55 +125 °C Voltage On Any Signal (except F[2:1]-VCC, VCCQ, F-VPP, S-VCC and P-VCC) F[2:1]-VCC Voltage –0.5 +2.45 V 2,3 VCCQ, S-VCC and P-VCC Voltage F-VPP Voltage –0.2 +14.0 V 2,3,4,5 ISH Output Short Circuit Current – 100 mA 6 Notes: 1. 90 nm is only avail with the 1.8 V I/O. 2. All Specified voltages are relative to V SS. Minimum DC voltage is –0.2 V on input/output signals, –0.2 V on F[2:1]-VCC and F-VPP signals. For 90 nm devices, during transitions, this level may overshoot to –1.5 V for periods < 20 ns, during transitions, may overshoot to F-VCC + 1.5 V for periods < 20 ns. 3. All Specified voltages are relative to V SS. Minimum DC voltage is –0.2 V on input/output signals, –0.2 V on F[2:1]-VCC and F-VPP signals. For 130 nm devices, during transitions, this level may overshoot to –2 V for periods < 20 ns, during transitions, may overshoot to F-VCC + 2 V for periods < 20 ns. 4. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. 5. F-V PP program voltage is normally V PPL. The maximum DC voltage on F-V PP may overshoot to +14 V for periods < 20 ns. F-VPP can be VPPH for 1000 erase cycles on main blocks, 2500 cycles on parameter blocks. 6. Output shorted for no more than one second. No more than one output shorted at a time. 7. Devices available with -30 o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F2030W0YTQF, 38F2030W0YBQF , 38F2040W0YTQF, 38F2040W0YBQF Table 5: Operating Conditions (Sheet 1 of 2) Symbol Parameter Flash + Flash Flash + SRAM Flash + PSRAM Unit Notes Min Max Min Max Min Max TC Operating Temperature –25 +85 –25 +85 –25 +85 °C 2

Order Number: 251407-13 17 32WQ and 64WQ Family with Asynchronous RAM

5.3 Capacitance

PSRAM and SRAM Supply Voltage Note: 1. F-V PP is normally VPPL. F-VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. 2. Devices available with -30 o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F2030W0YTQF, 38F2030W0YBQF, 38F2040W0YTQF, 38F2040W0YBQF NOTICE: Refer to the Numonyx™ Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx™ Wireless Flash Memory (W30) Datasheet (order number 290702) for flash capacitance details. For SCSP products with two flash die, flash capacitances for each of the flash die need to be considered accordingly. Table 5: Operating Conditions (Sheet 2 of 2) Table 6: SRAM, PSRAM Capacitance Symbol Parameter Typ Unit Condition CIN Input Capacitance 10 pF V IN = 0.0 V, Tc = 25 °C, f = 1 MHz COUT Output Capacitance 10 pF V OUT = 0.0 V, Tc = 25 °C, f = 1 MHz

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32WQ and 64WQ Family with Asynchronous RAM

6.0 Electrical Specifications

6.1 DC Characteristics

SRAM and PSRAM DC characteristics are shown in Table 7 and Table 8. Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and the Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for flash DC characteristics. Table 7: SRAM DC Characteristics Parameter Description Test Conditions 1.8 V SRAM 3.0 V SRAM Unit Min Max Min Max S-VCC Voltage Range 1.7 1.95 2.2 3.3 V VDR VCC for Data Retention 1.0 – 1.5 – V ICC Operating Current at min cycle time IIO = 0 mA

4 M –2 5–4 5

mA8 M –3 5–5 0 16M – 40 – 55 ICC2 Operating Current at max cycle time (1 μs) IIO = 0 mA 4M – 4 – 10 mA8M – 6 – 10 16M – 10 – 15 ISB Standby Current S-CS1# ≥ S-VCC-0.2V or S-CS2 ≤ VSS+0.2V Address/Data toggling at minimum cycle time

4 M –1 2–1 5

μA8 M –2 0–2 5 16M – 30 – 45 IDR Current in Data Retention mode

1.8 V SRAM:

S-VCC = 1.0 V

3.0 V SRAM:

S-VCC = 1.5 V

4 M –6–5

μA8 M –1 0–1 2 16M – 18 – 15 VOH Output HIGH Voltage I OH = -100 μA S-VCC - 0.15 – S-VCC - 0.1 –V VOL Output LOW Voltage IOL = 100 μA, VCCMIN VIH Input HIGH Voltage S-VCC - 0.4 S-VCC+ 0.2 S-VCC - 0.4 S-VCC+ 0.2 V VIL Input LOW Voltage -0.2 0.4 -0.2 0.6 V IOH Output HIGH Current – – – – mA IOL Output LOW Current – – – – mA *IIL Input Leakage Current -0.2 < V IN < S-VCC + 0.2 V -1 +1 -1 +1 μA *ILDR Input Leakage Current in Data Retention Mode -0.2 < VIN < S-VCC + 0.2 V S-VCC = VDR -1 +1 -1 +1 μA * Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs.

Order Number: 251407-13 19 32WQ and 64WQ Family with Asynchronous RAM Table 8: PSRAM DC Characteristics Parameter Description Test Conditions 1.8 V PSRAM 3.0 V PSRAM Unit Notes Min Max Min Max VCC Voltage Range 1.8 1.95 2.7 3.1 V ICC Operating Current at min cycle time IIO = 0 mA 8M – – – 30 mA 2 16M – 30 – 35 16M – 20 – – mA 3 32M – 35 – 45 mA 2 I CC2 Operating Current at max cycle time (1 μs) IIO = 0 mA 8M – – – 5 mA 216M – 5 – 7 32M – – – 7 ISB Standby Current P-CS# ≥ P-VCC- 0.2V. All inputs stable (either high or low) 8M – – – 80 μA2 , 4 16M – 100 – 100 P-CS# ≥ P-VCC- 0.2V or P-Mode ≥ P-VCC- 0.2V Address/Data toggling at minimum cycle time 16M – – – 85 μA2 , 5 32M – 100 – 100 Isbd Deep Power- Down P-Mode ≤ 0.2 V 16M – – – 10 μA2 , 4 32M – 30 – 10 VOH Output HIGH Voltage IOH = -0.5 mA 0.8P - VCC –2 . 4 – V 4 IOH = -0.1 mA 1.4 – P-VCC - 0.3 –V 5 VOL Output LOW Voltage IOL = 1 mA, – 0.2P - V CC –0 . 4 V 4 VIH Input HIGH Voltage 0.8P -VCC P-VCC + 0.3 P-VCC - 0.3 P-VCC + 0.2 V4 P-VCC - 0.3 P-VCC + 0.2 P-VCC- 0.4 P-VCC + 0.2 V5 VIL Input LOW Voltage –0.3 0.2P - V CC -0.2 0.5 V 4 IIL Input Leakage Current -0.2 < VIN < P-VCC + 0.2 V -1 +1 -1 +1 μA1 , 2 IOL Output Leakage Current -0.2 < VIN < P-VCC + 0.2 V P-VCC = VDR Notes: 1. Input Leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. 2. All currents are in RMS unless noted otherwise. 3. Applicable only to parts 38F1030W0YxQF & 38F2030W0YxQF . 4. Applicable to parts with P-Mode pin (38F2030W0ZxQ1, 38F2040W0YxQ0, 28F2240WWYxQ0). 5. Applicable to No-P-Mode (38F1030W0YxQF , 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQF, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0).

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM

7.0 AC Characteristics

7.1 Flash AC Characteristics

Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702)

7.2 SRAM AC Characteristics

Table 9: SRAM AC Characteristics #S y m b o l 1 Parameter Min Max Unit Notes R1 t RC Read Cycle Time 70 – ns 1 R2 t AA Address to Output Delay – 70 ns 1 R3 t CO1 S-CS1# to Output Delay – 70 ns 1 R3 t CO2 S-CS2 to Output Delay – 70 ns 1 R4 t OE R-OE# to Output Delay – 35 ns 1 R5 t BA R-UB#, R-LB# to Output Delay – 70 ns 1 R6 t LZ S-CS1# or S-CS2 to Output in Low-Z 5 – ns 1,3,4 R7 t OLZ R-OE# to Output in Low-Z 0 – ns 1,4 R8 t HZ S-CS1# or S-CS2 to Output in High-Z 0 25 ns 1,2,3,4 R9 t OHZ R-OE# to Output in High-Z 0 25 ns 1,2,4 R10 t OH Output Hold (from Address, S-CS1#, S-CS2 or R-OE# Change, whichever occurs first) 0– n s 1 R11 t BLZ R-UB#, R-LB# to Output in Low-Z 0 – ns 1,4 R12 t BHZ R-UB#, R-LB# to Output in High-Z 0 25 ns 1,4 Note: 1. See Figure 5, “AC Waveform SRAM Read Operations” . 2. Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, t HZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. 4. Sampled, but not 100% tested.

Order Number: 251407-13 21 32WQ and 64WQ Family with Asynchronous RAM Figure 5: AC Waveform SRAM Read Operations Address Stable Valid Data R12 R11 R10 R9R7 R8R3 R1R1Standby ADDRESSES S-CS1# S-CS2 R-OE# R-WE# DATA R-UB#, R-LB#

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM Table 10: SRAM AC Characteristics (Write)

7.3 PSRAM AC Characteristics

#S y m b o l 1 Parameter Min Max Unit Notes W1 t WC Write Cycle Time 70 – ns 1 W2 t AS Address Setup to R-WE# (S-CS1#) and R-UB#/R-LB# Low 0 – ns 1,4 W3 t WP R-WE# (S-CS1#) Pulse Width 55 – ns 1,2,3 W4 t DW Data to Write Time Overlap 30 – ns 1 W5 t AW Address Setup to R-WE# (S-CS1#) High 60 – ns 1 W6 t CW S-CS1# (R-WE#) Setup to R-WE# (S-CS1#) High 60 – ns 1 W7 t DH Data Hold from R-WE# (S-CS1#) High 0 – ns 1 W8 t WR Write Recovery 0 – ns 1,5 W9 t BW R-UB#, R-LB# Setup to R-WE# (S-CS1#) High 60 – ns 1 Notes: 1. See Figure 6, “AC Waveform SRAM Write Operations” . 2. A write occurs during the overlap (t WP) of low S-CS1# and low R-WE#. A write begins when S-CS1# goes low and R- WE# goes low with asserting R-UB# and R-LB# for single byte operation or simultaneously asserting R-UB#R-LB# and R-LB# for double byte operation. A write ends at the earliest high transition of S-CS1# and R-WE#. 3. t WP is measured from S-CS1# low to the end of a write. 4. t AS is measured from the address valid to the beginning of a write. 5. t WR is measured from the end of write to the address change. t WR applied in case a write ends as S-CS1# or R-WE# goes high. Figure 6: AC Waveform SRAM Write Operations Table 11: PSRAM AC Characteristics (85ns or 88ns Initial Access) — Read Operations # Symbol Parameter 5 1.8 V 3.0 V Unit Notes M i nM a xM i nM a x R1 t RC Read Cycle Time 88 4,000 85 4,000 ns R2 t AA A d d r e s s t o O u t p u t D e l a y –8 8–8 5 n s R3 t CO P - C S # t o O u t p u t D e l a y –8 8–8 5 n s Addres s Stable Data In W9W9W2 W7W4 W3W3 W8W6 W1W1Standby ADDRESSES S-CS1# S-CS2 R-OE# R-WE# DATA R-UB#, R-LB#

Order Number: 251407-13 23 32WQ and 64WQ Family with Asynchronous RAM R4 t OE R-OE# to Output Delay – 65 – 40 ns R5 t BA R-UB#, R-LB# to Output Delay – 88 – 85 ns R6 t LZ P-CS# to Output in Low-Z 10 – 10 – ns 1,2 R7 t OLZ R-OE# to Output in Low-Z 5 – 0 – ns 2 R8 t HZ P-CS# to Output in High-Z – 25 0 25 ns 1,2,3 R9 t OHZ R-OE# to Output in High-Z – 25 0 25 ns 2,3 R10 t OH Output Hold (from Address, P-CS# or R- OE# change, whichever occurs first) 5–0– n s R11 t BLZ R-UB#, R-LB# to Output in Low-Z 5 – 0 – ns 2 R12 t BHZ R-UB#, R-LB# to Output in High-Z – 25 0 25 ns 2 PR1 t PC Page Cycle Time 30 – 40 – ns 4 PR2 t PA Page Access Time – 30 – 35 ns 4 Note: 1. At any given temperature and voltage condition, t HZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. 2. Sampled but not 100% tested. 3. Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. 4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM. 5. Applicable to parts with 85ns or 88ns initial access time: 38F2030W0ZxQ1, 38F2040W0YxQ0, 38F2040W0ZxQ0, 28F2240WWYxQ0. Table 11: PSRAM AC Characteristics (85ns or 88ns Initial Access) — Read Operations # Symbol Parameter 5 1.8 V 3.0 V Unit Notes Min Max Min Max

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM Table 12: PSRAM AC Characteristics (70ns Initial Access) — Read Operations #S y m b o l 1 Parameter7 1.8 V 3.0 V Unit Notes Min Max Min Max R1 t RC Read Cycle Time 70 15000 70 15000 ns 70 8000 – – 2 R2 t AA A d d r e s s t o O u t p u t D e l a y –7 0–7 0 n s R3 t CO P - C S # t o O u t p u t D e l a y –7 0–7 0 n s R4 t OE R - O E # t o O u t p u t D e l a y –4 5–4 5 n s R5 t BA R-UB#, R-LB# to Output Delay – 70 – 70 ns R6 t LZ P-CS# to Output in Low-Z 5 – 5 – ns 3 R7 t OLZ R-OE# to Output in Low-Z 0 – 0 – ns R8 t HZ P - C S # t o O u t p u t i n H i g h - Z 02 502 5 n s3 , 4 R9 t OHZ R-OE# to Output in High-Z 0 25 0 25 ns 4 R10 t OH Output Hold (from Address, P-CS# or R-OE# change, whichever occurs first) 0–0– n s R11 t BLZ R-UB#, R-LB# to Output in Low-Z 0 – 0 – ns R12 t BHZ R-UB#, R-LB# to Output in High-Z 0 25 0 25 ns PR1 t PC Page Cycle Time 25 – 25 – ns 5 PR2 t PA Page Access Time – 25 – 25 ns 5 tCEL CE# low-time restriction – 8,000 ns 4 ns 6 Note: 1. See Figure 7, “AC Waveform of PSRAM Read Operations” on page 25 and Figure 8, “AC Waveform of PSRAM 4-Word Page Read Operation” on page 25 2. Spec’s only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF 3. At any given temperature and voltage condition, t HZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. 4. Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 5. 4-Word Page read only available for 16-Mbit PSRAM. No page mode feature for 8-Mbit PSRAM. Parts 38F1030W0YxQF & 38F2030W0YxQF do not support page mode, so this spec will not apply to them 6. CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns 7. Applicable to 70ns initial access P-SRAM’s ( 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQ2, 38F2030W0YxQF , 38F2030W0ZxQ2)

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM W5 tAW Address Setup to R-WE# (P-CS#) Going High 60 – 60 – ns W6 tCW P-CS# (R-WE#) Setup to R-WE# (P-CS#) Going High 60 – 60 – ns W7 tDH Data Hold from R-WE# (P-CS#) High 0– 0 – n s W8 tWR Write Recovery 0 – 0 – ns 5 W9 tBW R-UB#, R-LB# Setup to R-WE# (P-CS#) Going High 60 – 60 – ns tCEL P-CE# low-time restriction – 8,000 – – ns 7,8 W10 tWPH Write High Pulse Width 10 – – – ns 8 Notes: 1. See Figure 9, “AC Waveform PSRAM Write Operation” . 2. A write occurs during the overlap (t WP) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE# goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high. 3. t WP is measured from P-CS# going low to end of a write. 4. t AS is measured from the address valid to the beginning of a write. 5. t WR is measured from the end of a write to the address change. t WR applied in case a write ends as P-CS# or R-WE# going high. 6. W3 is 70 ns for continuous write operations over 50 times. 7. P-CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns 8. Spec’s only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF 9. Applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0. Table 13: PSRAM AC Characteristics—Write (Sheet 2 of 2) #S y m b o l 1 Parameter7 1.8 V 3.0 V Unit Notes Min Max Min Max Figure 9: AC Waveform PSRAM Write Operation Data In W7W4 W3W3 ADDRESSES P-CS# R-UB#, R-LB# R-WE# DAT A

Order Number: 251407-13 27 32WQ and 64WQ Family with Asynchronous RAM

7.4 Device AC Test Conditions

Figure 10: Transient Input/Output Reference Waveform Note: AC test inputs are driven to V CCQ, P-VCC for logic “1” and 0.0 V for logic “0”. input/output timing begins/ends at VCCQ/2, P-VCC/2. Input rise and fall time (10% to 90%) < 5 ns. Worse case speed occurs at V CC = VCCMin. Figure 11: Transient Equivalent Testing Load Circuit Notes: 1. Test configuration component value for worst case specification conditions. 2. C L includes jig capacitance. Test Points VCCQ/2, P-VCC/2 VCCQ/2, P-VCC/2Input Output 0 V VCCQ, P-VCC I/O Output ZO = 50 Ohms CL= 30 pf50 Ohms P-VCC/2 = VCCQ/2

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM

8.0 Flash Power Consumption

Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for detailed information.

Order Number: 251407-13 29 32WQ and 64WQ Family with Asynchronous RAM

9.0 Device Operation

9.1 Bus Operations

Bus operations for the W18/W30 SCSP family involve the following chip enable and output enable signals, respectively:

• F1-CE# for Flash Die#1 and F2-CE# for Flash Die#2
• F1-OE# for Flash Die#1 and F2-OE# for Flash Die#2 All other control signals are shared between the two flash die. Table to Table 16 explain the bus operations of products across this SCSP family. Refer to the W18/W30 discrete datasheets (order numbers 290701 and 290702) for single flash die SCSP bus operations. Table 14: Flash-Only Bus Operations Device Mode F-RST# F1-CE# F1-OE# F-WE# ADV# F-VPP WAIT F2-CE# F2-OE# D[15:0] Notes Flash Die#1 Sync Array Read H L L H L X Active H X Flash DOUT 2, 3, 4 All Async / Sync Non-Array Read H L L H X X Asserted H X Flash DOUT 1, 3, 4, W r i t e HLHLX V PPL or VPPH Asserted H X Flash DIN 3, 4, 6 Output Disable H L H H X X Active X X Flash High-Z 4 S t a n d b y HHXXX XH i g h - Z X X Flash High-Z 4 R e s e t LXXXX XH i g h - Z X X Flash High-Z 4

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM Flash Die#2 Sync Array Read H H X H L X Active L L Flash DOUT 2, 3, 4 All Async / Sync Non-Array Read H H X H X X Asserted L L Flash DOUT 1, 3, 4, Write H H X L X V PPL or VPPH Asserted L H Flash DIN 3, 4, 6 Output Disable H X X H X X Active L H Flash High-Z 4 S t a n d b y HXXXX XH i g h - Z H X Flash High-Z 4 R e s e t LXXXX XH i g h - Z X X Flash High-Z 4 Notes: 1. For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the memory bus. See Section 10.0, “Flash Command Definitions” on page 33 for details regarding flash selection overlap. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. Refer to the W18 or W30 datasheet (order number 290701 and 29702) for further information regarding WAIT Signal. 3. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-OE# will override F-WE#. 4. L means V IL while H means VIH. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 6. Refer to W18/W30 datasheet for valid D IN during flash writes. Table 15: Flash + SRAM Bus Operations Device Mode F-RST# F[2:1]-CE# F[2:1]-OE# F-WE# ADV# F-VPP WAIT S-CS1# S-CS2 R-OE# R-WE# R-UB#, R-LB# D[15:0] Notes Flash Die(#1 or #2) Sync Array Read HLLHL X A c t i v e SRAM must be in High-Z Flash DOUT 1, 2, 3, 5 All Async/ Sync Non- array Read H L L H X X Asserted Flash D OUT 1, 2, 3, 5, Write H L H L L V PPL or VPPH Asserted Flash DIN 3, 7 Output Disable HLHHX X A c t i v e Any SRAM mode allowed Flash High-Z 5 S t a n d b y HHXXX XH i g h - Z Flash High-Z 5 R e s e t LXXXX XH i g h - Z Flash High-Z 5 Table 14: Flash-Only Bus Operations Device Mode F-RST# F1-CE# F1-OE# F-WE# ADV# F-VPP WAIT F2-CE# F2-OE# D[15:0] Notes

Order Number: 251407-13 31 32WQ and 64WQ Family with Asynchronous RAM SRAM Read Flash must be in High-Z LHLHL SRAM DOUT 1, 4, 8, 2 Write LHXL L SRAM D IN 4, 5, 8, 2 Output Disable Any flash mode allowed LHHHX SRAM High-Z 5, 2 Standby HX XXX SRAM High-Z 5, 8, 2XL Data Retention Same as SRAM standby SRAM High-Z 9, 2 Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. For flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so, F[2:1]-OE# will override F-WE#. 4. For SRAM, R-OE# and R-WE# should never be asserted simultaneously. 5. X can be V IL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 6. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 7. Refer to W18 and W30 datasheet for valid D IN during flash writes. 8. The SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2. 9. The SRAM can be placed into data retention mode by lowering S-VCC to the V DR limit when in standby mode. Table 16: Flash + PSRAM Bus Operations Device Mode F-RST# F[2:1]-CE# F[2:1]-OE# F-WE# ADV# F-VPP WAIT P-CS# P-Mode R-OE# R-WE# R-UB#, R-LB# D[15:0] Notes Flash Die(#1 or #2) Sync Array Read HLLHL X A c t i v e PSRAM must be in High-Z Flash DOUT 1, 2, 3, 4, 6 All Async/ Sync Non- array Read H L L H X X Asserted Flash D OUT 1, 2, 3, 4, 6, 7 Write H L H L X VPPL or VPPH Asserted Flash DIN 3, 4, 6, 8 Output Disable HLHHX X A c t i v e Any PSRAM mode allowed Flash High-Z 6 Standby H H X X X X High-Z Flash High-Z 6 R e s e t LXXXX X H i g h - Z Flash High-Z 6 Table 15: Flash + SRAM Bus Operations Device Mode F-RST# F[2:1]-CE# F[2:1]-OE# F-WE# ADV# F-VPP WAIT S-CS1# S-CS2 R-OE# R-WE# R-UB#, R-LB# D[15:0] Notes

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM PSRAM Read Flash#1 and #2 must be in High-Z LHLHL PSRAM DOUT 1, 5, 2 Write LHHLL PSRAM DIN 5, 2 Output Disable Any flash mode allowed LHHHX PSRAM High-Z 6, 2 Standby H H X X X PSRAM High-Z 6, 2 Deep Power- Down HLXXX PSRAM High-Z 6, 9, 2 Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously selected. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. F1-CE# for Flash Die#1, F2-CE# for Flash Die#2. F1-OE# is for Flash Die#1, F2-OE# for Flash Die#2. 4. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-OE# will override F-WE#. 5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously. 6. X can be V IL or VIH for inputs, VPPL,VPPH or VPPLK for F-VPP. 7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 8. Refer to W30/W18 datasheet for Valid D IN during flash writes. 9. Deep power-down is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0. Table 16: Flash + PSRAM Bus Operations Device Mode F-RST# F[2:1]-CE# F[2:1]-OE# F-WE# ADV# F-VPP WAIT P-CS# P-Mode R-OE# R-WE# R-UB#, R-LB# D[15:0] Notes

Order Number: 251407-13 33 32WQ and 64WQ Family with Asynchronous RAM

10.0 Flash Command Definitions

Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for detailed information regarding the following:

11.0 Flash Read Operations

12.0 Flash Program Operations

13.0 Flash Erase Operations

14.0 Flash Security Modes

15.0 Flash Read Configuration Register

32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007

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32WQ and 64WQ Family with Asynchronous RAM

16.0 SRAM Operations

16.1 Power-up Sequence and Initialization

The SRAM functionality and reliability are independent of the power-up sequence and power-up slew rate of the core S-VCC. Any power-up sequence and power-up slew rate is possible under use conditions. SRAM reliability is also independent of the power- down sequence and power-down slew rate of the core S-VCC.

16.2 Data Retention Mode

Table 17: SRAM Data Retention Operation Symbol Parameter Min Max Unit Notes tSDR Data Retention Set-up Time 0 – ns tRDR Data Retention Recovery Time t RC –n s 1 Note: 1. t RC is defined in Table 9, “SRAM AC Characteristics” on page 20. Figure 12: SRAM Data Retention Operation Waveform—S-CS1# Controlled S-VCC S-VCCmin S-VIHmin VDR VSS tSDR Data Retention Mode tRDR S-CS1#

Order Number: 251407-13 35 32WQ and 64WQ Family with Asynchronous RAM Figure 13: SRAM Data Retention Operation Waveform—S-CS2 Controlled S-VCC S-VCCMIN VDR VILMAX VSS S-CS2 tSDR Data Retention Mode tRDR

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32WQ and 64WQ Family with Asynchronous RAM

17.0 PSRAM Operations

17.1 Power-Up Sequence and Initialization

The PSRAM functionality and reliability are independent of the power-up sequence and slew rate of the core P-VCC. Any power-up sequence and slew rate is possible under use conditions. PSRAM reliability are also independent of the power-down sequence and slew rate of the core P-VCC. The following power-up sequence and register setting should be used before starting normal operation. The PSRAM power-up sequence is represented in Figure 14. Following power application, make P-Mode high after fixing P-Mode to a low level for a period of tI1. Make P-CS# high before making P-Mode high. P-CS# and P-Mode are fixed to a high level for period of tI3. 17.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode) For the non-page mode PSRAM (part’s RD38F1030W0YQF, PF38F1030W0YQF, RD38F2030W0YQF, PF38F2030W0YQF) the PSRAM functionality and reliability must be independent of the power-up sequence and power-up slew rate of the core Vcc and the I/O Vcc (Vccq.) Any power-up sequence and power-up slew rate is possible under use conditions. PSRAM reliability must also be independent of the power-down sequence and power-down slew rate of the core Vcc and the I/O Vcc (Vccq.) Once power supply voltages have reached the minimum spec value of 1.7V (or higher), CE# must be maintained high for minimum 200us prior to commencing valid PSRAM operation. Figure 14: Timing Waveform for Power-Up Sequence Table 18: Power-Up Sequence Specifications Parameter Description Min Max Unit Notes tI1 Power application with P-Mode held low 50 — μs1 , 2 , 3 tI2 P-CS# high to P-Mode high 10 — ns tI3 P-Mode high to P-CS# low 500 — μs Notes: 1. Toggle P-Mode to low when starting the power-up sequence. 2. t I1 is specified from when the power supply voltage reaches V CCMIN. 3. Does not apply to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, and 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0 line items. Valid PSRAM operations for these line items can begin 200 μs after P-Vcc has reached P-Vcc min. Register Setting tI3tI1 tI2 Power Up P-VCC P-CS# P-MODE

Order Number: 251407-13 37 32WQ and 64WQ Family with Asynchronous RAM

17.2 Standby Mode/ Deep Power-Down Mode

Caution: All line items that do not have the P-Mode pine will not have the deep power- down feature (38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0). Data is lost during deep power-down mode as shown in the Table below. Wake-up from deep power-down mode involves the same initialization sequence as discussed in Section 17.1, “Power-Up Sequence and Initialization” on page 36.

17.3 PSRAM Special Read and Write Constraints

Caution: This section will not apply to line items that do not have the P-Mode pine will not have the deep power-down feature (38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0). Mode Memory Cell Data Delay time to go Active Standby Valid 0 ns Deep Power-Down Invalid Start-Up Sequence Figure 15: Timing Waveform for Entering Deep Power-Down Mode Table 19: PSRAM Special Read Constraints Description Min Max Unit Notes Cannot have sub tRC address toggle for more than 4 μs in active mode. Need either a read operation or P-CS# high for t RC in that time frame N/A N/A – P-CS# high level pulse width 10 – ns 1 R-UB#/R-LB# high level pulse width 10 – ns 1 R-OE# high level pulse width in active mode (P-CS# low) 10 10,000 ns P-CS# low to R-OE# low – 10,000 ns Address Skew time (unstable address with P-CS# low) – 10 ns 2 Notes: 1. Toggling of these control signals is not necessary during address controlled read operations. 2. Address skew time (t SKEW) indicates the following three types of time depending on the condition. a. When switching P-CS# from high to low, t SKEW is the time from the P-CS# low i nput point until the next address is determined. b. When switching P-CS# from low to high, t SKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, t SKEW is the time from the address start point until the next address is determined. Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high. Deep Power Down ModeDeep Power Down ModeSuspend Mode 1 us P-MODE P-CS# Device Mode

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32WQ and 64WQ Family with Asynchronous RAM Appendix A Write State Machine Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for the WSM details. Appendix B Common Flash Interface Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx™ Wireless Flash Memory (W30) Datasheet (order number 290702) for the CFI details. Appendix C Flash Flowcharts Refer to the Numonyx™ Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx™ Wireless Flash Memory (W30) Datasheet (order number 290702) for the flash flowchart details. Appendix D Additional Information Table 20: PSRAM Special Write Constraints Description Min Max Unit Notes Need either R-WE# high or P-CS# high for at least t WC time, for every 4us window during write operations. N/A N/A – R-OE# high to R-WE# low in active mode (P-CS# low) 0 10,000 ns R-WE# high to R-OE# low in active mode (P-CS# low) 10 10,000 ns Address Skew time (unstable address with P-CS# low) – 10 ns 1 Note: 1. Address skew time (t SKEW) indicates the following three types of time depending on the condition. a. When switching P-CS# from high to low, t SKEW is the time from the P-CS# low input point until the next address is determined. b. When switching P-CS# from low to high, t SKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, t SKEW is the time from the address start point until the next address is determined. Since specs are defined for t SKEW only when P-CS# is active, t SKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high. Order Number Document

290701 Numonyx™ Wireless Flash Memory (W18) Datasheet

290702 Numonyx™ Wireless Flash Memory (W30) Datasheet

251216 64-Mbit 1.8 Volt Numonyx™ Wireless Flash Memory SCSP Family Application Note Note: Contact your local Numonyx or distribution sales office or visit the Numonyx website at http://www.numonyx.com for the most current information on Numonyx Flash memory products, software, and tools.

Order Number: 251407-13 39 32WQ and 64WQ Family with Asynchronous RAM Appendix E Ordering Information (Active Line Items) Figure 16: Decoder for Flash + RAM SCSP Family Devices F 2 0 W 0 Z B Q8D 3R Package Pinout Indicator Product Line Designator Flash Density Voltage Product Family RD = SCSP PF = Pb-free SCSP 38F = Flash & RAM Stack Device 2 = 64-Mbit 1 = 32-Mbit 0 = No die W = Intel® Wireless Flash Memory 0 = No Die Y = 1.8 Volt I/O Z = 3 Volt I/O Q= QUAD+ ballout 3 0 RAM Density 4 = 32-Mbit 3 = 16-Mbit 2 = 8-Mbit 1 = 4-Mbit 0 = No Die Parameter Location B = Bottom Parameter T = Top Parameter D = Dual Parameter Device Details 0-9, A-D = 1 st Generation, 130 nm E-R = 2 nd Generation, 90 nm (note: 90 nm is only 1.8 V I/O) S-Z = 3 rd Generation, TBD Flash #1 Flash #2 RAM #2 RAM #1 Flash #1 Family Flash #2 Family

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32WQ and 64WQ Family with Asynchronous RAM Appendix F Ordering Information (Retired Line Items) Shown here are the decoder for products in the SCSP family with both flash and RAM and the decoder for products in the SCSP family with flash die only (no RAM). The decoders are following by available product combinations. Table 21: Ordering Information on Active Line Items Flash Component RAM Package Product Number PSRAMSize in Mbit and Family Size in Mbit and Type Size (mm) Ballout Type 32M Flash + 16M PSRAM

32 W18

16 PSRAM

8 x 10 x 1.2 Quad+ Lead-free PF38F1030W0YTQ2 PF38F1030W0YBQ2 70 ns, No PMODE pin & Non-Page Mode Support16 PSRAM PF38F1030W0YTQF PF38F1030W0YBQF 32 W30 16 PSRAM 8 x 10 x 1.2 Quad+ Lead-free PF38F1030W0ZTQ0 PF38F1030W0ZBQ0 70 ns, No PMODE pin 64M Flash + 16M PSRAM

64 W18

8 x 10 x 1.2 Quad+ Lead-free PF38F2030W0YTQ1 PF38F2030W0YBQ1 70 ns, No PMODE pin 70 ns, No PMODE pin & Non-Page Mode Support PF38F2030W0YTQF PF38F2030W0YBQF 64 W30 16 PSRAM 8 x 10 x 1.2 Quad+ Lead-free PF38F2030W0ZTQ2 PF38F2030W0ZBQ2 70 ns, No PMODE pin 64M Flash + 32M PSRAM 64 W18 32 PSRAM 8 x 10 x 1.2 QUAD+ Lead-free PF38F2040W0YTQ0 PF38F2040W0YBQ0 88 ns, with PMODE pin 64 W30 32 PSRAM 8 x 10 x 1.2 QUAD+ Lead-free PF38F2040W0ZTQ1 PF38F2040W0ZBQ1 85 ns, No PMODE pin

Order Number: 251407-13 41 32WQ and 64WQ Family with Asynchronous RAM Figure 17: Decoder for Flash + RAM SCSP Family Devices F 2 0 W 0 Z B Q8D 3R Package Pinout Indicator Product Line Designator Flash Density Voltage Product Family RD = SCSP PF = Pb-free SCSP 38F = Flash & RAM Stack Device 2 = 64-Mbit 1 = 32-Mbit 0 = No die W = Intel® Wireless Flash Memory 0 = No Die Y = 1.8 Volt I/O Z = 3 Volt I/O Q= QUAD+ ballout 3 0 RAM Density 4 = 32-Mbit 3 = 16-Mbit 2 = 8-Mbit 1 = 4-Mbit 0 = No Die Parameter Location B = Bottom Parameter T = Top Parameter D = Dual Parameter Device Details 0-9, A-D = 1 st Generation, 130 nm E-R = 2 nd Generation, 90 nm (note: 90 nm is only 1.8 V I/O) S-Z = 3 rd Generation, TBD Flash #1 Flash #2 RAM #2 RAM #1 Flash #1 Family Flash #2 Family

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32WQ and 64WQ Family with Asynchronous RAM Figure 18: Decoder for Flash-Only SCSP Family Devices F 2 2 W 0 Z D Q8D 4R Package Pinout IndicatorProduct Line Designator Flash Density Voltage Product Family RD = SCSP PF = Pb-free SCSP 48F = Flash-only Stack Device 2 = 64-Mbit 1 = 32-Mbit 0 = No Die W = Intel® Wireless Flash Memory 0 = No Die Y = 1.8 Volt I/O Z = 3 Volt I/O Q = QUAD+ Ballout 0 0 0 Parameter Location D = Dual Parameter Flash #1 Flash #2 Flash 1/2 Family Flash #4 Flash #3 Flash 3/4 Family Device Details 0-9, A-D = 1st Generation, 130 nm E-R = 2nd Generation, 90 nm (note: 90 nm is only 1.8 V I/O) S-Z = 3rd Generation, TBD B = Bottom Parameter T = Top Parameter

Order Number: 251407-13 43 32WQ and 64WQ Family with Asynchronous RAM Table 22: 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only) Flash Component Package Product Number (1,2,3,4,5) Size (mm) Type Ballout 32 W30 8 x 10 x 1.2 Lead-free Quad + PF48F1000W0ZTQ0 PF48F1000W0ZBQ0 64 W30 8 x 10 x 1.2 Lead-free Quad + PF48F2000W0ZTQ0 PF48F2000W0ZBQ0 64 W18 + 64W18 8 x 10 x 1.2 Leaded Quad + RD48F2200W0YDQ0

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32WQ and 64WQ Family with Asynchronous RAM Notes: 1. W18 = Numonyx™ Wireless Flash Memory (W18); W30 = Numonyx™ Wireless Flash Memory (W30). 2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. 4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. Notes: 1. W18 = Numonyx™ Wireless Flash Memory (W18); W30 = Numonyx™ Wireless Flash Memory (W30). 2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. 4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. Table 23: 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + SRAM) Flash Component RAM Package Product Number(1,2,3,4) Size in Mbit and Family Size in Mbit and Type Size (mm) Type Ballout 4 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2010W0YTQ0 RD38F2010W0YBQ0 8 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2020W0YTQ0 RD38F2020W0YBQ0 16 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2030W0YTQ0 RD38F2030W0YBQ0

64 W30

8 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2020W0ZTQ0 RD38F2020W0ZBQ0 16 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2030W0ZTQ0 RD38F2030W0ZBQ0 64 W18 + 64 W18 16 SRAM 8 x 10 x 1.4 Leaded Quad+ RD38F2230WWYDQ0 64 W30 + 64 W30 16 SRAM 8 x 10 x 1.4 Leaded Quad+ RD38F2230WWZDQ0 Table 24: 32WQ & 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 1 of 2) Flash Component RAM Package Product Number (1,2,3,4,5) PSRAM usedSize in Mbit and Family Size in Mbit and Type Size (mm) Ballout Type 32 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded RD38F1030W0YTQ2 RD38F1030W0YBQ2 70 ns, No PMODE pin & Non-Page Mode Support 32 W30 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded RD38F1030W0ZTQ0 RD38F1030W0ZBQ0 70 ns, No PMODE pin 64 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded RD38F2030W0YTQ1 RD38F2030W0YBQ1 70 ns, No PMODE pin 64 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded RD38F2030W0YTQ2 RD38F2030W0YBQ2 70 ns, No PMODE pin & Non-Page Mode Support 64 W30 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded RD38F2030W0ZTQ1 RD38F2030W0ZBQ1 85 ns, with PMODE pin 64 W30 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded RD38F2030W0ZTQ2 RD38F2030W0ZBQ2 70 ns, No PMODE pin

Order Number: 251407-13 45 32WQ and 64WQ Family with Asynchronous RAM Notes: 1. W18 = Numonyx™ Wireless Flash Memory (W18); W30 = Numonyx™ Wireless Flash Memory (W30). 2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. 4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 5. RD38F2240WWYDQ0 = Engineering Samples; RD38F2240WWYDQ1 = Production 64 W18 32 PSRAM 8 x 10 x 1.2 QUAD+ Leaded RD38F2040W0YTQ0 RD38F2040W0YBQ0 88 ns, with PMODE pin 64 W30 32 PSRAM 8 x 10 x 1.2 QUAD+ Leaded RD38F2040W0ZTQ0 RD38F2040W0ZBQ0 85 ns, No PMODE pin 64 W30 32 PSRAM 8 x 10 x 1.2 QUAD+ Leaded RD38F2040W0ZTQ1 RD38F2040W0ZBQ1 85 ns, No PMODE pin 64 W18 + 64 W18 32 PSRAM 8 x 10 x 1.4 QUAD+ Leaded RD38F2240WWYDQ0(6) RD38F2240WWYDQ1 88 ns, with PMODE pin 64 W30 + 64 W30 32 PSRAM 8 x 10 x 1.4 QUAD+ Leaded RD38F2240WWZDQ0 RD38F2240WWZDQ1 85 ns, No PMODE pin Table 24: 32WQ & 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 2 of 2) Flash Component RAM Package Product Number (1,2,3,4,5) PSRAM usedSize in Mbit and Family Size in Mbit and Type Size (mm) Ballout Type

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32WQ and 64WQ Family with Asynchronous RAM