RD151TS3312ARP RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 9
Technical content
Features
- Supports 10 MHz to 20 MHz operations. Multiple rate (XIN: SSCOUT) = 1: 1 Input frequency 10 MHz to 20 MHz
- Spread spectrum modulation ; RD151TS3312ARP : ±1.5%, ±0.5% (Central spread modulation) RD151TS3322ARP : –3.0%, –1.0% (Down spread modulation) Key Specifications
- Supply voltages: VDD = 3.3 V ±0.3 V
- Cycle to cycle jitter = ±100 ps typ.
- Clock output duty cycle = 50 ±5%
- Output slew rate = 0.7 V/ns typ.
- Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) RD151TS3312ARPH0 RD151TS3322ARPH0 SOP-8 pin (JEDEC) PRSP0008DD-C (FP-8DCV) RP H (2,500 pcs / Reel) Block Diagram Synthesizer Mode Control 1/N OSC SSC Modulator VDD SSCOUT NC GND SEL XIN XOUT SSN 1/M R = 350 kΩ R = 350 kΩ R = 1 MΩ
RD151TS3312ARP, RD151TS3322ARP Rev.1.00 May 11, 2006 page 2 of 8 Pin Arrangement (Top view)
8 VDD1
7 SEL
6 SSCOUT
5 GND
Pin name No. Type Description GND 5 Ground GND pin VDD 8 Power Power supply pin. NC 3 NC Don’t connect any VDD or GND. SSCOUT 6 Output Spread spectrum modulated clock output. XIN 1 Input Oscillator input. XOUT 2 Output Oscillator output. SEL 7 Input SSC% mode select pin. LVCMOS level input. Pull-down by internal resistor (350 kΩ ). SSN 4 Input SSC ON/OFF select pin. LVCMOS level input. Pull–down by internal resistor (350 kΩ ). SSC Function Table STB SEL RD151TS3312ARP(Central spread) RD151TS3322ARP(Down spread) 0 1 ±0.5% –1.0% 1 0 1 1 OFF OFF Note: 1. ±1.5%(TS3312ARP) / -3.0%(TS3322ARP) SSC is selected for default by internal pull-down resistors. Clock Frequency Table PRODUCT XIN(MHz) SSCOUT(MHz) Multiply rate (XIN: SSCOUT) RD151TS3312ARP 10 to 20 10 to 20 1:1 RD151TS3322ARP 10 to 20 10 to 20 1:1
RD151TS3312ARP, RD151TS3322ARP Rev.1.00 May 11, 2006 page 3 of 8 Absolute Maximum Ratings Item Symbol Ratings Unit Conditions Supply voltage V DD –0.5 to 4.6 V Input voltage V I –0.5 to 4.6 V Output voltage *1 V O –0.5 to V DD+0.5 V Input clamp current I IK –50 mA V I < 0 Output clamp current I OK –50 mA V O < 0 Continuous output current I O ±50 mA V O = 0 to VDD Maximum power dissipation 0.7 W Ta = 55°C (in still air) Storage temperature T stg –65 to +150 °C Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. 1. The input and output negative volt age ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage V DD 3.0 3.3 3.6 V DC input signal voltage –0.3 — V DD+0.3 V High level input voltage V IH 0.7 ×VDD — V DD+0.3 V Low level input voltage V IL –0.3 — 0.3 ×VDD V Input clock duty cycle 45 50 55 % Operating temperature T a –20 — 85 °C Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V Item Symbol Min Typ Max Unit Test Conditions — — ±20 V I = 0 V or 3.6 V, VDD = 3.6 V, XIN pin Input current I I — — ±100 µA VI = 0 V or 3.6 V, VDD = 3.6 V, SEL, SSN pins Input capacitance C I — 3 — pF SEL, SSN pins Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V Item Symbol Min Typ Max Unit Test Conditions VOH V DD–0.2 — — V I OH = –1 mA Output voltage VOL — — 200 mV I OL = 1 mA IOH — –13 — V OH = 1.5 V, VDD = 3.3 V Output current IOL — 13 — mA VOL = 1.5 V, VDD = 3.3 V Output impedance — 40 — Ω Note: Parameters are target of desi gn. Not 100% tested in production.
RD151TS3312ARP, RD151TS3322ARP Rev.1.00 May 11, 2006 page 5 of 8
Application Information
- Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Figure 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. SSCOUT6 SEL SSN 5 XIN XOUT C1 C2 GND GND GND VDD (Crystal or Reference input) (Crystal or Not connection) NC Notes: C1 = High frequency supply decoupling capacitor. (0.1 µF recommended) C2 = Low frequency supply decoupling capacitor. (22 µF recommended) R1 = Match value to line impedance. Figure 2 Recommended circuit configuration
RD151TS3312ARP, RD151TS3322ARP Rev.1.00 May 11, 2006 page 6 of 8 2. Example Board Layout Configuration Crystal connection or Reference input Crystal connection or No connection SSCOUT P G G G 0.1 µF 22 µF FB VDD (+3.3V Supply) GNote: Via to GND plane R1 = Match value to line impedance. FB = Ferrite bead. Figure 3 Example Board Layout
RD151TS3312ARP, RD151TS3322ARP Rev.1.00 May 11, 2006 page 8 of 8 Package Dimensions F*1 p Mx y E Index mark A D Z H E b p Terminal cross section ( Ni/Pd/Au plating ) c b Detail F A L L θ 0.75 0.10 1.27 5.80 6.20 0.400.34 5.30 MaxNomMin Dimension in Millimeters Symbol Reference 1.75 1.270.600.40 3.95 0.250.140.10 0.46 0.250.200.15 6.10 8°0° 0.25 1.08 4.90 Z HE y x θ c bp E D e e L A NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. MASS[Typ.] FP-8DCVPRSP0008DD-C RENESAS CodeJEITA Package Code Previous Code
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