RCLAMP052XP UMW | Alldatasheet

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High Definition Multi-Media Interface (HDMI) Digital Visual Interface (DVI) DisplayPortTM Interface MDDI Ports PCI Express eSATA Interfaces ESD protection for high-speed data lines to IEC 61000-4-2 (ESD) ±17kV (air), ±12kV (contact) IEC 61000-4-5 (Lightning) 5A (8/20μs) IEC 61000-4-4 (EFT) 40A (5/50ns) Package design optimized for high speed lines Flow-Through design Protects two or four I/O lines Low capacitance: 0.3pF typical (I/O to I/O) Low clamping voltage Low operating voltage: 5V Solid-state silicon-avalanche technology Mechanical Characteristics SLP1610P4 6-pin package (1.6 x 1.0 x 0.58mm) SLP2510P8 10-pin package (2.5 x 1.0 x 0.58mm) Pb-Free, Halogen Free,RoHS/WEEE Compliant Lead Pitch: 0.5mm Lead finish: NiPdAu Pin 1 Pin 2 3, 4 Pin 1 Pin 2 Pin 4 Pin 5 3, 8 Absolute Maximum Rating gnitaRl obmySe ulaVs tinU )sμ02/8=pt(rewoPesluPkaePP kp 051 W )sμ02/8=pt(tnerruCesluPkaePI PP 5A )riA(2-4-00016CEIrepDSE )tcatnoC(2-4-00016CEIrepDSE V DSE 71-/+ 21-/+ Vk erutarepmeTgnitarepOT J 521+ot55-C ° erutarepmeTegarotST GTS 051+ot55-C °w ww.umw-ic.com 1 友台半导体有限公司R Clamp arrays are ultra low capacitance ESD protection devices designed to protect high speed data interfaces. This series has been specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage caused by ESD (electrostatic discharge), CDE (Cable Discharge Events), and EFT (electrical fast transients). The RClamp0522P and RClamp0524P have a typical capacitance of only 0.30pF between I/O pins. This allows it to be used on circuits operating in excess of 3GHz without signal attenuation. They may be used to meet the ESD immunity requirements of IEC 61000- 4-2. The RClamp0522P is designed to protect two lines, while the RClamp0524P will protect four lines. The RClamp0522P is in a 6-pin SLP1610P4 package. It measures 1.6 x 1.0 with a nominal height of 0.58mm. The RClamp0524PA is in a 10-pin SLP2510P8 package. It measures 2.5 x 1.0 with a nominal height of 0.58mm. The leads are spaced at a pitch of 0.5mm and are finished with lead-free NiPdAu. They are designed for easy PCB layout by allowing the traces to run straight through the device. The combination of small size, low capacitance, and high level of ESD protection makes them a flexible solution for applications such as HDMI, DisplayPortTM, MDDI, and eSATA interfaces. UMW R

Electrical Characteristics (T=25oC) retemaraPl obmySs noitidnoCm uminiMl acipyTm umixa tinU egatloVffO-dnatSesreveRV MWR dnuorgotnipO/IynA5 V egatloVnwodkaerBesreveRV RB It Am1= dnuorgotnipO/IynA tnerruCegakaeLesreveRI R V MWR C°52=T,V5= dnuorgotnipO/IynA 1A μ egatloVgnipmalCV C I PP sμ02/8=pt,A1= dnuorgotnipO/IynA 51V ecnaticapaCnoitcnuJC j VR zHM1=f,V0= snipO/IneewteB 03.04 .0F p ecnaticapaCnoitcnuJC j VR zHM1=f,V0= dnuorgotnipO/IynA 8.0F p Ms Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 100 110 0 25 50 75 100 125 150 Ambient Temperature - TA (oC) % of Rated Power or IPP 0.01 0.1 0.1 1 10 100 1000 Pulse Duration - tp (us) Peak Pulse Power - PPP (kW)www.umw-ic.com 2 友台半导体有限公司 RCLAMP052xP UMW R

Clamping Voltage vs. Peak Pulse Current (Between any I/O and Ground) Pulse Waveform 100 110 0 5 10 15 20 25 30 Time (祍) Percent of I PP e-t td = IPP/2 Waveform Parameters: tr = 8祍 td = 20祍 Normalized Capacitance vs. Reverse Voltage 0123456 Peak Pulse Current - IPP (A) Clamping Voltage -VC (V) Waveform Parameters: tr = 8 s td = 20 s Line to Gnd Line to Line 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 012345 Reverse Voltage - VR (V) CJ(VR) / CJ(VR=0) f = 1 MHz Insertion Loss S21 - I/O to GND 1 2 START . 030 MHz 3 STOP 000 . 000 000 MHz CH1 S21 LOG 6 dB / REF 0 dB 1: -0.086 dB

900 MHz

2: -0.0336 dB

1.8 GHz

3: -0.126 dB

2.5 GHz

-6 dB -12 dB -18 dB -24 dB -30 dB -36 dB GHz 100 MHz GHz MHz MHz -42 dB -48 dB Insertion Loss S21 - I/O to I/O 1 2 START . 030 MHz 3 STOP 000 . 000 000 MHz CH1 S21 LOG 6 dB / REF 0 dB 1: -0.076 dB 2: -0.062 dB 3: -0.1087 dB -6 dB -12 dB -18 dB -24 dB -30 dB -36 dB GHz 100 MHz GHz MHz MHz -42 dB -48 dB www.umw-ic.com 3 友台半导体有限公司 RCLAMP052xP UMW R

Outline Drawing - SO-8Outline Drawing - SLP1610P4/SLP2510P8 LxNE/2 2X R0.075

3 PLACES

R0.125 e1 .039 BSC 1.00 BSC INCHES .020 BSC b .006 bbb aaa N L e D .012 DIM A MIN 0.00 .020 0.430.30 .004 .003 .015 .063 .017 0.08 0.10 0.38 1.60

0.50 BSC

0.05 0.65 DIMENSIONS MIN 0.00 NOM (.005) .023 .001 MAX .002 .026 NOM 0.50 0.03 (0.13) 0.58 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). NOTES: 1.00.039E 1.701.50.067.059 0.90 1.10.043.035 E DA aaa C PIN 1 INDICATOR (LASER MARK) B C SEATING PLANE e N A bbb C A B INCHES .020 BSC b .006 bbb aaa N L e D .012 DIM A MIN 0.00 .020 0.4250.30 .004 .003 .015 .098 .017 0.08 0.10 0.38 2.50 0.05 0.65 DIMENSIONS MIN 0.00 NOM (.005) .023 .001 MAX .002 .026 NOM 0.50 0.03 (0.13) 0.58 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). NOTES: A2 A1 A bbb C A B bxN bbb C A B D/2 b1xN LxNE/2 R0.125 2X R0.075

7 PLACES

1.00.039E 2.602.40.102.094 0.90 1.10.043.035 E DA aaa C PIN 1 INDICATOR (LASER MARK) B C SEATING PLANE e N SLP1610P4 SLP2510P8 www.umw-ic.com 4 友台半导体有限公司 RCLAMP052xP UMW R

SLP1610P4 Pin Configuration (Top View) niPn oitacifitnedI 2-1s eniLtupnI 6-5 seniLtuptuO )noitcennoClanretnIoN( 4-3d nuorG SLP2510P8 Pin Configuration (Top View) 12 453 8 67910 niPn oitacifitnedI 5,4,2,1s eniLtupnI 01,9,7,6 seniLtuptuO )noitcennoClanretnIoN( 8,3d nuorG Pin 1 Pin 2 Pin 4 Pin 5 3, 8 65 4 Pin 1 Pin 2 3, 4 Circuit Diagram Circuit Diagram Marking 0522P 0524P Pin Identification and Configuration Orderinginformation Ordercode Package Baseqty Deliverymode UMW RCLAMP0522P.TCT SLP1610P4 3000 Tape and reel UMW RCLAMP0524P SLP2510P8 3000 Tape and reel www.umw-ic.com 5 友台半导体有限公司 RCLAMP052xP UMW R