RC7106 | DigiCamel IC Datasheet

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RC7106 FAIRCHILD | Alldatasheet

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SEMICONDUCTOR m www fairchildsemi.com 133MHz Spread Spectrum Clock for Motherboards Features Description + Employs Fairchild’s proprietary Spread Spectrum The RC7106 is a clock synthesizer for motherboard applica- Technology tions. It meets the requirements for 133MHz Camino + Reduces measured EMI by as much as 10dB chipset. The clock frequencies can be set with the 4 select * Supports up to 1SOMHz pins or be set via the I°C interface. + PC programmable + Three skew-controlled copies of the CPU clock + One copy CPU/2 @ 3.3V + Three copies of 3V66 clock + One copy 24MHyz or 48MHz clock * One copy 48MHz, clock + Three copies IOAPIC + Two copies REF 14.318MHz clock (3.3V) + Eleven copies PCI clock + Power down capability Block Diagram xt x > REFO | yo SEL24 48H/REFI IOAPICO:2 = Pk Spread > cpu2 Spectrum | | max cPuo3 3V66_0:2 $ [Kk Pousto yn LY T A | >+- FsoPrcl_F on nn ae SDATA L | >-4- Fstsircii:s solr Za a 48MHz/SEL_3V66 pwROWNE t—-P 7 24_4BMHz/FREQ_APIC

RC7106 PRODUCT SPECIFICATION Pin Assignments qi VY 48 2 47[.0 o3 460 c4 45D cys 4410 c6 43 [1 7 420 os 4p os 40 Cj 10 39 FD i 38 f Cj 12 37D C13 36 C14 35 Cj 15 34F0 Cj 16 3D C17 32D C18 310 Cj 19 30 Cj 20 29 C21 28 Cj 22 27p Cj 23 26 fF Cj 24 25

48 SSOP

PRODUCT SPECIFICATION RC7106 PWRDWN# mona] enw | som | ane | oe | a || oe | ma | 24MHz, PWRDWN# IOAPIC 3V66 48MHz osc. PLL Lot fon Ton Ton Ton Ton Ton Ton On Frequency Selection [ves qui) | __TOAPIC wr) ||| | PRP I EE MHz =0 =1 =0 =1 Le pe[o |i | [srslars| or | 75 | iam | ars _| Lo fo [a | © [ros] sois[ss4| see [eee [ter [ssa | De [efi [+ [esas [oe | ess | es | veer | 4 | Le [a |o | [io[ ss [ass[ or | 733 _| tes_| 356 _| bo fa fe | 1 [is] srs ses |e [76 | isie | 385 | Dept pio pir[ses[s [er [| is [| bop pa [a [ro oo [ao [oe [wo [1 pepe |e [rs [estas] or | ass | ms | a6 | [ape pet pa fesfes| er [as [aie | 2s | [1 pe [+ | © [sss] 665 [ass | ses | eee [168 | a5 | sO tpt fe [© 137 [ees [se25| ees [ees [aries [3025 | Pepa pe [1 pel fas | | [vs [5 | [a [eas [res [seas | eer [res eras [262 | Oc *Note: These output frequencies are not synchronous to the CPU Clock and do not have Spread Spectrum modulation.

RC7106 PRODUCT SPECIFICATION Pin Descriptions |_PinName | PinNumber | Type | Pin Function Description CPUO:2 40,38,37 OUT CPU Clock Outputs: The frequency of these three CPU clocks are determined by the 4 select pins FS0:3 or via the [°C interface. cPUu/2 42 OUT CPU/2 Clock Output: The frequency of this clock is determined by the 4 select pins FS0:3 or via the IC interface. PCI4:10 14,15,17,18, OUT PCI BUS Clock Outputs: These seven PCI clock outputs run 20,21,22 synchronously to the CPU. FSO/PCI_F IN/OUT | I/O Dual Function FSO and PCI_F pin: See table for frequency selection. After power-on, this pin becomes a free-running PCI clock. FS1:3/ 911,12 IN/OUT V/O Dual Function FS1:3 and PCI1:3 pin: See table for frequency PCI1:3 selection. After power-on, these pins become normal PCI clock. 3V66 Clock Outputs: See table for frequency selection REF Clock Output: This output provides a 14.318MHz high drive clock . SEL24_48#/ IN/OUT. VO Dual Function SEL24_48# and REF1 Pin: During power-up, if REF1 the input is “0”, 48MHz would be selected on pin 26. If the input is latched “1”, 24MHz would be selected. After power-on, this pin becomes a REF1 output. There is an internal pull-up resistor on this pin. IOAPICO:2 47,46,44 IOAPIC Clock Outputs: See table for frequency selection. 24_48MHz/ OUTI/IN VO Dual Function 24_48MHz and Freq_APIC pin: See table for FREQ_APIC. frequency selection. After power-on the pin becomes a normal 24MHz or 48MHz clock depending on pin 3 during power-up. 48MHz/ 27 OUT/IN | I/O Dual Function 48MHz and FS3 pin: See table for frequency SEL_3V66 selection. After power-on the pin becomes a normal 48MHz clock. x1 Crystal Connection: An input connection for an external14.318MHz crystal. Connect to either a 14.318MHz crystal or other reference signal. x2 OUT Crystal Connection: If using an external reference, this pin must be left unconnected. PWRDWN# 24 Power-down Input pin: This pin shuts down the clock PLL bring all clocks to a low state. SCLK I°C Clock Pin: The IPC clock should be applied to this input as described in the IC section of this datasheet. SDATA IN/OUT | [°C Data Pin: Data should be presented to this input as described by the I7C section of this datasheet. There is an internal pull-up resistor on this pin. VDD 4,10,16,23, POWER | 3.3V Power Pins: 28,35 VDDL 39,43,48 POWER | 2.5V Power Pins: VSS 1,7,13,19,25, POWER | Ground Pins: 31,36,41,45

cies as shown in the table. A short time after power up, the of ane ten back on again. " minimally affected by the 10kohm strap to ground or VDD. Upon power up, the first 2mS of operation is used for input ‘Put logic sampling. Figure 1. Input Logic Selection through Resistor Load Option

this serial data interface is optional. The serial interface is the control functions of the serial data interface. Table 2. Serial Data Interface Control Functions Summary held low. outputs to unused PCI slots. controlled fashion. under normal system operation. Output Tristate Puts all clock outputs into a high Production PCB testing. Test Mode All clock outputs toggle in relation to X1 Production PCB testing. revision or production device testing. written as 0. tiated, valid data can then be sent. Data is considered to be valid SCLOCK is held high. See Figure below. The COMMAND CODE and BYTE COUNT is not used by the Butfer Chip.

of eight bits each. See Table 3 for byte order. Table 3. Byte Writing Sequence

1 Slave 11010010 | Commands the RC7106 to accept the bits in Data Bytes 3-6 for internal

not correct (or is for an alternate slave receiver). 2 Command | Don’t Care | Unused by the RC7106, therefore bit values are ignored (don't care). addressed slave receiver on the serial data bus. Byte Count | Don’tCare | Unused by the RC7106, therefore bit values are ignored (don't care). addressed slave receiver on the serial data bus. [6 | Data Byte 2 control functions, refer to Table 4, Data Byte Serial Configuration Map.

. . . grammable via the serial data interface. See Table 4 for bit descriptions of Data Bytes 1-4. Table 4. Data Bytes 1-4 Serial Configuration Map

Table 5. Byte 0: Functionality and frequency select register (Default = 0) Note 1: Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are defaulted to 0000. “These output frequencies are not synchronous to the CPU Clock and do not have Spread Spectrum modulation. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. not implied. Maximum conditions for extended periods may affect reliability.

RC7106 PRODUCT SPECIFICATION Ta = 0°C to +70°C; VDD = 3.3V+5%; VDDL = 2.5V+5% TestConaition | Win | Typ Wax] Unis | Combined 3.3V Supply Current CPU = 133MHz Outputs TBD mA Loaded Combined 2.5V Supply Current CPU = 133MHz Outputs TBD mA Loaded Logic Inputs [tis | Input High Curren ee [lin [lat High Curent a Clock Outputs? Vou Output High Voltage loy=-1MA 2.0 v CPU, CPU/2 and IOAPIC PCI, 3V66, 24 24MHz,48MHz,REF lot Output Low Current Vo_=1.2V 27 mA CPU, CPU/2 Por av66 Tout Las [| | REF, 24H eM es [|_| Output High Current VoH=1.4V -101 -26 mA CPU and CPU/2 REF, 2aNe BN ee Crystal Oscillator XT input Treshol Vaage | VOD=3.3V ee Xt input Capactance™ | X@ unconnected | | 18 | | oF Pin Capacitance/Inductance input Pn Capactance Bepixianae [|_| 8 | F | OuipuiPinCapacianss [| ———SS~d Sid Sid input Pin Inductance a Notes: 4. The RC7106 contains an internal crystal load capacitor be- 1. RC7106 logic inputs have internal pull-up resistors. tween X1 and VSS and another between X2 and VSS. 2. Allclock outputs loaded with maximum lump capacitance The total load placed on the crystal is 18pF; this includes test load specified in AC Electrical Characteristics section. ypleal stray careers of eno ce aces towne csi ical) | input capacitance is applicable when X1 is driven wit 3. X1 input threshold voltage (typical) is VDD/2 an external clock source (X2 is left unconnected).

PRODUCT SPECIFICATION RC7106 Ta=0°C to 70°C; VDD=3.3V25%; VDDL=2.5V+5%:; fyt_=14.31818MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU0:1 (C, oqp=20pF) |_CPU=133MHz | nmi im ||| etconstonconmns | [te [Peres [75 |_| 8 | nS | Weas atrcngedgeatt25v. i [ie _[towtime |__| 18 |__| n8 | Duration ofclockoyele below 0AV | [ie [ouputnisetine [4 | [16 [rs [oave2v Sid [ie [Ouputrantime [4 [| 18 | nS [2oveow SSS [to [Duyowe | | | 58 | % |Weasuredatiaev id [us| siter Cysieto yale |_| | 250. | pS _| Measured on sing edge at 1 25V___—_—| [isc [Ouputskew | [| 175 | pS | Measured on rsing edge at 26V. | P* Tesretereer| | | |” [aerate from Power-up (cold from power-up. Short cycles exist prior to start) frequency stabilization. Lia a a for determining series termination value.

RC7106 PRODUCT SPECIFICATION PCI Clock Outputs, PCI0:7 (Lump Capacitance Test Load = 30pF) |_Pel=s3amHz | fmt [||| Tecan [te [Poros | 30 | |__| 8 | Weas.aliisngedgeati5v = [a [Her Time | 120 | |__| 8 _| Duration of cock ole above 2V—_—| [x [towTine | 120. [| |r| Duration af cock cycle below 0aV [te [Oupunisotime [os[[@ [rs lovee [te [Ouputrattime [os [ [2 [8 [aaviooaySS—~S [to [Ouyeyle | as | os [| Measured [uc [ater eto Gye |_| | 500 | pS | Measured on ising age atT5V—— [isc [Output Stew | | | 500 | pS [ Measured on rising edge at 15V.———_—| fe [overetsonomel LL [erraceatiy! tien ce _| rising edge at 1.5V. CPU leads PCI output. 3V66 Clock Outputs (Lump Capacitance Test Load = 30pF) Jennie in| ||| Teeanatanconmet [te [OupunisoTime [05 [ [2 [rs fowwew SCS—~* [ie [OuputFattine [os [| @ [8 [eo SSSC—~d [to [Ouyeyle |S | as [Measuedatey C= [ie [ter yetocyse |_| | 800 | pS | Measured on rising edge at7 BV | [ise [Ouputstew |__| | 250 [ pS [Measuedattsv i fst | Frequency Stabilization 3 Assumes full supply voltage reached within 1mS. [ [remPontn "| |_| ® | ™ [renner oer meetin ne Sic ad for determining series termination value. CPU/2 Clock Output (Lump Capacitance Test Load = 20pF) |_cPu=133MHz | [ier [|| Ttcanatencanment [T [Frewerey [seme Cd [ta [Oupuirisotine [os] [2 | 8 [oWeaw SSS—~*d [te [Oupatrattine [os || @ [v8 [awvnow S—=S [to [ouyeyle | | as | [Measured atv C*d [ie [iter ysetoaycie |__| | 250 | pS [ Measured on rising oogoatT5V———_—| [isc [Oupusiew [|__| 178 [pS [Measuedatizv fst | Frequency Stabilization 3 mS _ | Assumes full supply voltage reached within 1mS. re ecm [= | > eae a for determining series termination value.

PRODUCT SPECIFICATION RC7106 24MHz and 48MHz Clock Outputs (Lump Capacitance Test Load = 20pF) Jems [ || _ttcontonconmet 24,004 [io | Freaveney devaion [+167 | pom | @eoneaeyae—SS—=*d Ee [ia [Oupansotine [os | [2 |S [oweewS—~Sd [| OuputFattime [os | 2 | rs |2avwow SS [to [ouyoyle | a || SB | [Measured tev C= [ia [iter Absoite |_| | 800 | pS | Measured onrsing eds atv. ‘| fgp | Frequency Stabilization 3 mS_ | Assumes full supply voltage reached within 1mS [ retonto "||| ® | [pooner armen nt Si a a for determining series termination value. IOAPIC Clock Output (Lump Capacitance Test Load = 20pF) nmin | ts) retconstoncommet | [t[Freqweney | ____883.__| Wz | Frequency generated by crystal oscllator | [te [Oupunisetme [oe] [te [rs lows [ie [OuputFat tine [04 | [16 [ rs [aoveoav SSSC—~S [io [Duyowe [as [| 88 | [Measured VS [ia | siterAbsoite |__| | 500. | pS_[ Measured on rising edge at 126V.—_| [isc [Oupuseew [|_| 178 [ pS [Measuedatizv [ [remtonts "||| | [ferponerup 77 eevee nS from Power-up from power-up. [fe [evenness FTL | [erst es rraten rae | for determining series termination value. REF Clock Output (Lump Capacitance Test Load = 20pF) [rumen pu | et consenconmen | [T[Frewoney | _14stei8 | wz | Frequency generated by oystal osclaton [a [Oupatrisetine [oS] [2 [nS lowwew —*d [te [Ouputrartine [os| | 2 [nS [2avoow SSS [to [OuyGyeie [as | | a8 | [Measued tiv S—S [ie [iter Oyseto-ate [| |_1 | nS | Measured onisng edge atte. | [isc [Ouputsiew [| [1 [nS [Measuedatisv fst Frequency Stabilization 3 mS | Assumes full supply voltage reached within 1mS [Tremont "||| | [reponse ene nS pe [eewemnme| [= | [aaa for determining series termination value.

RC7106 PRODUCT SPECIFICATION Group Skews (CPU and IOAPIC load = 20pF; PCI, 3V66 load = 30pF) CPU (66.6MHz) to ro] fp CPU @ 1.25V and 3V66 @ 1.5V 3V66 3V66 to PCI | 1.5 | 21 | 4 | nS | 3V66 and PCI @ 1.5V, 3V66 Leads CPU to IOAPIC CPU and IOAPIC @ 1.25V, CPU Leads

PRODUCT SPECIFICATION RC7106 Mechanical Dimensions 48 pin SSOP Symbol ee ee Notes +. Dimensioning and tolerancing per ANSI Y14.5M - 1982. A [095 | iio [241 | 279 | 2. "D" and "E1” do not include mold flash. Mold flash or At | oog | oie | 020 [ 041 | protrusions shall not exceed .010 inch (0.25mm) D 0135 5 c [00s] —o10 | 0.13 [025 | 5 3. "Lis the length of terminal for soldering to a substrate. D [620 [630 [1575 | 1600 [24 7 a 4. Terminal numbers are shown for reference only. er | 201 | 200 [739 | 759 [2 5. "b’ & "c" dimensions include solder finish thickness. e 025 BSC 0.64 BSC L [020 [ o40 | 051 [ 102 [| 3. 6. Symbol "N" is the maximum number of terminals. N ee a | o Te | oe Te | Cc ee AARARERBAAARRBREBAARARRR E eI eDifafa) edad afifalalifala)itale}ijilalitalajii q a MUTTON TOUT f “semnorwe «= i a T| eT cam NR EE LEAD COPLANARITY [2Iccc[C]

RC7106 PRODUCT SPECIFICATION

Ordering Information

ProductNumber | Temperature | Screening | Package | Package Marking RO7I06 Pe ss0P RC7i06 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES. OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Acritical component is any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling, can be reasonably expected to result in significant injury to the user. www. fairchildsemi.com 5720789 0.0 008 ‘Stock#DS30005057. © 1998 Fairchild Semiconductor Corporation

Product Information

RC7106 specifications and overview.

Summary

133MHz Spread Spectrum Clock for Motherboards

Description

133MHz Spread Spectrum Clock for Motherboards

Source title RC7106 Datasheet(PDF) - Fairchild Semiconductor

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