RC5061 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
- Programmable output for Vcore from 1.3V to 3.5V using an integrated 5-bit DAC
- Controls adjustable linears for Vtt (1.5V), and Vclock (2.5V)
- Meets VRM specification with as few as 5 capacitors
- Meets 1.550V +40/-70mV over initial tolerance, temperature and transients
- Remote sense
- Active Droop (V oltage Positioning)
- Drives N-Channel MOSFETs
- Overcurrent protection using MOSFET sensing
- 85% efficiency typical at full load
- Integrated Power Good and Enable/Soft Start functions
- 20 pin SOIC package
Applications
- Power supply for Pentium III Camino Platform
- Power supply for Pentium III Whitney Platform
- VRM for Pentium III processor
- Programmable multi-output power supply
Description
The RC5061 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable set of output voltages for multi-voltage platforms such as the Intel Camino, and provides a complete solution for the Intel Whitney and other high-performance processors. The RC5061 features remote voltage sensing, independently adjustable current limit, and Active Droop for optimal converter transient response. The RC5061 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V . The RC5061 uses a high level of integration to deliver load currents in excess of 16A from a 5V Block Diagram VID3 VID2 VID1 VID0 GNDP OSC 1.24V Reference Digital Control Power Good 5-Bit DAC VID4 87654 +5V +12V PWRGD ENABLE/SS VCC GNDA LODRV HIDRV VCCP 17VCCA +5V REF REF PWRGD, OCL PWRGD, OCL +3.3V +1.5V +2.5V OCL VCCP R S RC5061 High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms
RC5061 PRODUCT SPECIFICATION REV. 1.0.0 7/6/00 source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components, while Active Droop permits exact tailor- ing of voltage for the most demanding load transients. The RC5061 includes linear regulator controllers for Vtt termina- tion (1.5V), and Vclock (2.5V), each adjustable with an exter- nal divider. The RC5061 also offers integrated functions including Power Good, Output Enable/Soft Start and current limiting, and is available in a 20 pin SOIC package. Pin Assignments RC5061 HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VTTGATE VTTFB VCCP LODRV GNDP VCCA VFB IFB PWRGD SS/ENABLE VCKFB VCKGATE Pin Definitions Pin Number Pin Name Pin Function Description
1 HIDRV
High Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". 2S W High side Driver Source and Low side Driver Drain Switching Node. Together with IFB pin allows FET sensing for Vcc current.
3 GNDA
Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. 4-8 VID0-4 Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller.
9 VTTGATE
Gate Driver for VTT Transistor. For 1.5V output.
10 VTTFB
Voltage Feedback for VTT.
11 VCKGATE
Gate Driver for VCK Transistor. For 2.5V output.
12 VCKFB
Voltage Feedback for VCK.
13 ENABLE/SS
Output Enable. A logic LOW on this pin will disable all outputs. An internal current source allows for open collector control. This pin also doubles as soft start for all outputs.
14 PWRGD
Power Good Flag. An open collector output that will be logic LOW if any output voltage is not within ±12% of the nominal output voltage setpoint.
15 IFB
Vcc Current Feedback. Pin 15 is used in conjunction with pin 2 as the input for the Vcc current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details.
16 VFB
Vcc Voltage Feedback. Pin 16 is used as the input for the Vcc voltage feedback control loop. See Application Information for details regarding correct layout.
17 VCCA
Analog VCC. Connect to system 5V supply and decouple with a 0.1µF ceramic capacitor.
18 GNDP
Power Ground. Return pin for high currents flowing in pin 20 (VCCP).
19 LODRV
Vcc Low Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5".
20 VCCP
Power VCC. For all FET drivers. Connect to system 12V supply through a 33 Ω , and decouple with a 1µF ceramic capacitor.
PRODUCT SPECIFICATION RC5061 REV. 1.0.0 7/6/00 Absolute Maximum Ratings Note: 1. Component mounted on demo board in free air. Recommended Operating Conditions Supply Voltage VCCA to GND 13.5V Supply Voltage VCCP to GND 15V Voltage Identification Code Inputs, VID0-VID4 VCCA All Other Pins 13.5V Junction Temperature, T J 150°C Storage Temperature -65 to 150°C Lead Soldering Temperature, 10 seconds 300°C Thermal Resistance Junction-to-ambient, Θ JA 75°C/W Parameter Conditions Min. Typ. Max. Units Supply Voltage VCCA 4.5 5 5.25 V Input Logic HIGH 2.0 V Input Logic LOW 0.8 V Ambient Operating Temperature 0 70 °C Output Driver Supply, VCCP 10.8 12 13.2 V Electrical Specifications CCA = 5V, V CCP = 12V, V OUT = 2.0V, and T A = +25°C using circuit in Figure 1 unless otherwise noted.) The • denotes specifications which apply over the full operating temperature range. Parameter Conditions Min. Typ. Max. Units VCC Regulator Output Voltage See Table 1 • 1.3 3.5 V Output Current 18 A Initial Voltage Setpoint I LOAD = 0.8A, V OUT = 2.400V V OUT = 2.000V V OUT = 1.550V 2.397 2.000 1.550 2.424 2.020 1.565 2.454 2.040 1.580 V V V Output Temperature Drift T A = 0 to 70°C, V OUT = 2.000V V OUT = 1.550V mV mV Line Regulation V IN = 4.75V to 5.25V • -4 mV/V Internal Droop Impedance I LOAD Ω Maximum Droop 60 mV Output Ripple 20MHz BW, I LOAD = 18A 11 mVpk Total Output Variation, Steady State V OUT = 2.000V V OUT = 1.550V 1.940 1.480 2.070 1.590 V Total Output Variation, Transient I LOAD = 0.8A to 18A, V OUT = 2.000V V OUT = 1.550V 1.900 1.480 2.100 1.590 V Short Circuit Detect Current • 45 50 60 µA Efficiency I LOAD = 18A, V OUT = 2.0V 85 % Output Driver Rise & Fall Time See Figure 3 50 nsec Output Driver Deadtime See Figure 3 50 nsec
RC5061 PRODUCT SPECIFICATION REV. 1.0.0 7/6/00 Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter’s VFB sense point. 2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m Ω trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s VRM 8.4 specification of +50, –80mV. If Intel specifications on maximum plane resistance from the converter’s output capacitors to the CPU are met, the specification of +40, –70mV at the capacitors will also be met. Duty Cycle 0 100 % 5V UVLO • 3.74 4 4.26 V 12V UVLO • 7.65 8.5 9.35 V Soft Start Current • 5 10 17 µA VTT Linear Regulator Output Voltage I LOAD 2A • 1.455 1.5 1.545 V Under Voltage Trip Level Over Current 80 %V O VCLK Linear Regulator Output Voltage I LOAD 2A • 2.375 2.5 2.625 V Under Voltage Trip Level Over Current 80 %V O Common Functions Oscillator Frequency • 255 310 345 kHz PWRGD Threshold Logic HIGH, All Outputs Logic LOW, Any Output 108 112 OUT Linear Regulator Under Voltage Delay Time Over Current 30 µsec Electrical Specifications (Continued) CCA = 5V, V CCP = 12V, V OUT = 2.0V, and T A = +25°C using circuit in Figure 1 unless otherwise noted.) The • denotes specifications which apply over the full operating temperature range. Parameter Conditions Min. Typ. Max. Units
- 0 = processor pin is tied to GND.
Table 1. Output Voltage Programming Codes
RC5061 PRODUCT SPECIFICATION REV. 1.0.0 7/6/00 Typical Operating Characteristics CCA = 5V, V CCP = 12V, and T A = +25°C using circuits in Figure 1, unless otherwise noted.) Droop, VCPU = 2.0V, RD = 8K Ω VOUT (V) VOUT (V) VCPU (V) VCPU (V) 2.04 2.03 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 1.94 0 3 6 9 12 15 18 Output Current (A) Output Programming, VID4 = 1 3.5 3.0 2.5 2.0 1.5 1.0 DAC Setpoint VCPU Efficiency vs. Output Current Output Current (A) 0 3 6 9 12 15 18 VOUT = 1.550V VOUT = 2.000V Efficiency (%) Output Programming, VID4 = 0 2.1 1.9 1.7 1.5 1.3 1.1 DAC Setpoint 0 5 10 15 20 25 3.5 3.0 2.5 2.0 1.5 1.0 0.5 CPU Output Voltage vs. Output Current Output Current (A)
PRODUCT SPECIFICATION RC5061 REV. 1.0.0 7/6/00 Typical Operating Characteristics (continued) Output Ripple, 2.0V @ 18A Time (1µs/div) Time (1µs/div) VCPU (20mV/div) VCPU (50mV/div) VCPU (50mV/div) VCPU (1V/div) VIN (2V/div) HIDRV pin LODRV pin 5V/div 5V/div Output Startup, System Power-up Transient Response, 12.5A to 0.5A 1.590V 1.550V 1.480V 1.590V 1.550V 1.480V Time (100µs/div) Time (100µs/div) Time (10ms/div) Switching Waveforms, 18A Load Output Startup from Enable VCPU (1V/div) ENABLE (2V/div) Time (10ms/div) Transient Response, 0.5A to 12.5A
Figure 1. Typical Application Circuit
Table 2. RC5061 Application Bill of Materials
- Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply
with Intel dI/dt requirements. L1 may be omitted if desired.
- For 17.4A designs using the TO-220 MOSFETs, heatsinks with thermal resistance
refer to Applications Bulletins AB-8 and AB-15. *Refer to Appendix for values.
1 N-Channel MOSFET R DS(ON) = 20mΩ @
1 N-Channel MOSFET R DS(ON) = 10mΩ @
2 N-Channel MOSFET
1 DC/DC Controller
Figure 2. Application Circuit for Coppermine/Camino Motherboards
Table 3. RC5061 Application Bill of Materials for Intel Coppermine/Camino Motherboards
- Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply
with Intel dI/dt requirements. L1 may be omitted if desired.
- For 12.5A designs using the TO-220 MOSFETs, heatsinks with thermal resistance Θ SA < 20°C/W should be used. For
selections, refer to Applications Bulletins AB-8 and AB-15.
RC5061 PRODUCT SPECIFICATION 12 REV. 1.0.0 7/6/00 Test Parameters Figure 3. Ouput Drive Timing Diagram
Application Information
The RC5061 is a programmable synchronous DC-DC con- troller IC. When designed around the appropriate external components, the RC5061 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The RC5061 functions as a fixed frequency PWM step down regulator. Main Control Loop Refer to the RC5061 Block Diagram on page 1. The RC5061 implements “summing mode control”, which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the DROOP (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the DROOP and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the RC5061 current limit comparator disables the output drive signals to the external power MOSFETs. High Current Output Drivers The RC5061 contains two identical high current output drivers that utilize high speed bipolar transistors in a push-pull config- uration. The drivers’ power and ground are separated from the chip’s power and ground for switching noise immunity. The power supply pin, VCCP, is supplied from an external 12V source through a series 33Ω resistor. The resulting volt- age is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low R DS,ON . Internal Voltage Reference The reference included in the RC5061 is a precision band-gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, includ- ing those below 1.80V . Power Good (PWRGD) The RC5061 Power Good function is designed in accordance with the Pentium III DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than ±12% of its nominal setpoint. The Power Good flag provides no other control function to the RC5061. Output Enable/Soft Start (ENABLE/SS) The RC5061 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching. A larger value may occasionally be required if the converter has a very large capacitor at its output. Over-Voltage Protection The RC5061 constantly monitors the output voltage for protec- tion against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-voltage condition is assumed and the RC5061 disables the output drive signal to the external high-side MOSFET. The DC-DC converter returns to normal operation after the output voltage returns to normal levels. Oscillator The RC5061 oscillator section uses a fixed frequency of operation of 300KHz. tR tDT tDT tF HIDRV to SW LODRV2V 2V
may be found in Fairchild’s Application Note 57.
- Low Static Drain-Source On-Resistance, R DS,ON < 20mΩ (lower is better)
- Low gate drive voltage, VGS = 4.5V rated
- Power package with low Thermal Resistance
- Drain-Source voltage rating > 15V. The on-resistance (R DS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applica- tions Bulletin AB-8. Inductor Selection Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is: where: V in = Input Power Supply Vout = Output V oltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel V ripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is: where: C o = The total output capacitance Ipp = Maximum to minimum load transient current V tb = The output voltage tolerance budget allocated to load transient D m = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax . Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for C O , which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The RC5061 pro- vides significant cost savings for the newer CPU systems that typically run at high supply current. RC5061 Short Circuit Current Characteristics The RC5061 protects against output short circuit on the core supply by turning off both the high-side and low-side MOSFETs and resetting softstart. The short circuit limit is set with the R S resistor, as given by the formula with IDetect ≈ 50µA, ISC is the desired current limit, and R DS,on the high-side MOSFET’s on resistance. Remember to make the RS large enough to include the effects of initial tol- erance and temperature variation on the MOSFET’s RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET eliminates this source of inaccuracy in the current limit. The value of R S should be less than 8.3KΩ . If a greater value is necessary, a lower RDS,on MOSFET should be used instead. As an example, Figure 4 shows the typical characteristic of the DC-DC converter circuit with an FDB6030L high-side MOSFET (R DS = 20mΩ maximum at 25°C * 1.25 at 75°C = 25m Ω ) and a 8.2KΩ RS.
Figure 4. RC5061 Short Circuit Characteristic DS,on rather than maximum, and is at 25°C).
Figure 6. Adjusting the Output Voltage of the Linear
- Placement of the MOSFETs relative to the RC5061 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5061 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress.
- In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5061. That is, traces that connect to pins 1, 2, 19, and 20 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 16 and 17.
- Place the 0.1µF decoupling capacitors as close to the RC5061 pins as possible. Extra lead length on these reduces their ability to suppress noise.
- Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins.
- Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter.
- Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5.
- A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. Additional Information For additional information contact Fairchild Semiconductor at http://www.fairchildsemi.com/cf/tsg.htm or contact an autho- rized representative in your area. VFB VGATE VOUT 10KΩ R R 10K Ω * –1 Vout Vnom
RC5061 PRODUCT SPECIFICATION 16 REV. 1.0.0 7/6/00 Appendix Worst-Case Formulae for the Calculation of Cout, R7, and Cin (Circuit of Figure 1 only) The following formulae design the RC5061 for worst-case operation, including initial tolerance and temperature depen- dence of all of the IC parameters (initial setpoint, reference tolerance and tempco, active droop tolerance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: V T+ , the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit; IO , the maximum output current; V nom , the nominal output voltage; V in, the input voltage (typically 5V); ESR, the ESR of the ouput caps, per cap (44mΩ for the Sanyo parts shown in this datsheet); R D , the on-resistance of the MOSFET (10mΩ for the FDB7030); ∆R D , the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature). Irms, the rms current rating of the input caps (2A for the sanyo parts shown in this datasheet.) The value of R7 must be ≤ 8.3KΩ . If a greater value is calcu- lated, RD must be reduced. Number of capacitors needed fo Cout = the greater of: Example: Suppose that the transient limits are ±134mV , cur- rent I is 14.2A, and the nominal voltage is 2.000V , using MOSFET current sensing and the usual caps. We have V T+ = calculate: Since X > Y , we choose X, and round up to find we need 5 capacitors for COUT . Irms Vin Vnom Vin Vnom *IO C in 50 * 10-6 VT- ESR * IO ESR * IO 18 * R5 * 1.1 14400 * IO * RD Y or VT+ –0.004 * Vnom + 2.000 2.000 *14.2 C in 3.47 ⇒ 4 caps= == 5.2KΩ 50 * 10-6 4.28 18 * 10400 * 1.1 0.044 * 14.2 Y = 4.66 0.134 0.044 * 14.2 X ==
PRODUCT SPECIFICATION RC5061 REV. 1.0.0 7/6/00 17 Mechanical Dimension 20-Lead SOIC A .093 .104 2.35 2.65 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .004 .012 0.10 0.30 .020 0.51B .013 0.33 C .009 .013 0.23 0.32 E .291 .299 7.40 7.60 e .394 .419 10.00 10.65 .010 .029 0.25 0.75 H .050 BSC 1.27 BSC h L .016 .050 0.40 1.27 0° 8° 0° 8° N2 0 2 0 α ccc .004 0.10—— D .496 .512 12.60 13.00 Notes: Dimensioning and tolerancing per ANSI Y14.5M-1982. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). "L" is the length of terminal for soldering to a substrate. Terminal numbers are shown for reference only. "C" dimension does not include solder finish thickness. Symbol "N" is the maximum number of terminals. D A A1 – C – ccc C LEAD COPLANARITY SEATING PLANEe B L h x 45° C α EH
RC5061 PRODUCT SPECIFICATION 7/6/00 0.0m 003 Stock#DS30005061 2000 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com