RC5051 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
- Programmable output from 1.3V to 3.5V using an integrated 5-bit DAC
- 85% efficiency typical
- Adjustable operation from 80KHz to 1MHz
- Integrated Power Good and Enable functions
- Overvoltage protection
- Overcurrent protection
- Drives N-channel MOSFETs
- 20 pin SOIC package
- Meets Intel Pentium II specifications using minimum number of external components
Applications
- Power supply for Pentium II
- VRM for Pentium II processor
- Programmable step-down power supply
Description
The RC5051 is a synchronous mode DC-DC controller IC which provides an accurate, programmable output voltage for all Pentium II CPU applications. The RC5051 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V . The RC5051 uses a high level of integration to deliver load currents in excess of 19A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range, and the internal oscillator can be programmed from 80KHz to 1MHz for additional flexibility in choosing external components. An on-board precision low TC refer- ence achieves tight tolerance voltage regulation without expensive external components. The RC5051 also offers integrated functions including Power Good, Output Enable, over-voltage protection and current limiting. Block Diagram DIGITAL CONTROL +5V 20 19 18 17 8 2 1.24V REFERENCE 5-BIT DAC 65-5051-01 POWER GOOD OSC PWRGD VREF VID0 VID1 VID2 VID4 VID3 ENABLE +5V VO RC5051 +12V RC5051 Programmable Synchronous DC-DC Controller for Low Voltage Microprocessors Pentium is a registered trademark of Intel Corporation.
RC5051 PRODUCT SPECIFICATION REV. 1.0.4 4/2/01 Pin Assignments Pin Definitions Pin Number Pin Name Pin Function Description
1 CEXT
Oscillator Capacitor Connection . Connecting an external capacitor to this pin sets the internal oscillator frequency. Layout of this pin is critical to system performance. See Application Information for details.
2 ENABLE
. A logic LOW on this pin will disable the output. An internal pull-up resistor allows for either open collector or TTL compatibility.
3 PWRGD
. An open collector output that will be at logic LOW if the output voltage is not within 12% of the nominal output voltage setpoint.
4 IFB
High Side Current Feedback . Pins 4 and 5 are used as the inputs for the current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details.
5 VFB
. Pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. See Application Information for details regarding correct layout.
6 VCCA
. Connect to system 5V supply and decouple with a 0.1 µ F ceramic capacitor.
7 VCCP
Power VCC for low side FET driver . Connect to system 5V supply and place a 1 µ F ceramic capacitor for decoupling and local charge storage.
8 VID4
. A logic 1 on this open collector/TTL input will enable the VID3–VID0 inputs to set the output from 2.1V to 3.5V, and a logic 0 will set the output from 1.3V to 2.05V, as shown in Table 1. Pullup resistors are internal to the controller.
9 LODRV
. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be < 0.5". 10, 11 GNDP Power Ground . Return pin for high currents flowing in pins 7 and 13 (VCCP and VCCQP). Connect to a low impedance ground.
12 HIDRV
. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be < 0.5".
13 VCCQP
. For high side FET driver. VCCQP must be connected to a voltage of at least VCCA + V GS,ON (MOSFET), and place a 1 µ F ceramic capacitor for decoupling and local charge storage. See Application Information for details
14 GNDD
. Return path for digital logic. Connect to a low impedance system ground plane to minimize ground loops.
15 GNDA
. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops.
16 VREF
Reference Voltage Test point . This pin provides access to the DAC output and should be decoupled to ground using 0.1 µ F capacitor. No load should be connected. 17-20 VID0-VID3 Voltage Identification Code Inputs . These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. Pull-up resistors are internal to the controller. VID0 VID1 VID2 VID3 VREF GNDA VCCQP GNDD 91 2 10 11 65-5051-02 CEXT ENABLE PWRGD IFB RC5051VFB VCCA VID4 VCCP GNDP HIDRV GNDP LODRV
PRODUCT SPECIFICATION RC5051 REV. 1.0.4 4/2/01 Absolute Maximum Ratings Operating Conditions Electrical Specifications CCA = 5V, V OUT = 2.8V, f osc = 300 KHz, and T A = +25 C using circuit in Figure 1, unless otherwise noted) The denotes specifications which apply over the full operating temperature range. Notes: 1. Steady Date Voltage Regulation includes Initial Voltage Setpoint, Load Regulation, Output Ripple and Output Temperature Drift and is measured at the converter’s output capacitors. 2. As measured at the converter ’s output capacitors. For motherboard applications, the PCB layout should exhibit no more than 0.5m Ω trace resistance between the converter’s output capacitors and the CPU. Supply Voltages, VCCA, VCCP, VCCQP to GND 13V Supply Voltage VCCQP, Charge Pump (V IN +VCCA) 18V Voltage Identification Code Inputs, VID4-VID0 13V Junction Temperature, T J 150 C Storage Temperature -65 to 150 C Lead Soldering Temperature, 10 seconds 300 C Parameter Conditions Min. Typ. Max. Units Supply Voltage, VCCA, VCCP 4.75 5 5.25 V Input Logic HIGH 2.0 V Input Logic LOW 0.8 V Ambient Operating Temp 0 70 C Output Driver Supply, VCCQP 8.5 12 V PWRGD threshold Logic High Logic Low 107 112 OUT OUT Parameter Conditions Min. Typ. Max. Units Output Voltage See Table 1 1.3 3.5 V Output Current 15 A Initial Voltage Setpoint I LOAD = 0.8A, V OUT = 2.8V V OUT = 2.0V 2.797 2.000 2.825 2.020 2.853 2.040 V V Output Temperature Drift T A = 0 to 70 CV OUT = 2.8V V OUT = 2.0V +16 +11 mV mV Load Regulation I LOAD = 0.8A to 14.2A -20 mV Line Regulation V IN = 4.75V to 5.25V 2m V Output Ripple 20MHz BW, I LOAD = 14.2A 13 mVpk Total Output Variation Steady State V OUT = 2.8V V OUT = 2.0V 2.740 1.940 2.900 2.060 V V Total Output Variation Transient I LOAD = 0.8 to 14.2A, V OUT = 2.8V V OUT = 2.0V 2.670 1.900 2.930 2.100 V V Short Circuit Detect Threshold 100 120 140 mV Efficiency I LOAD = 14.2A, V OUT = 2.8V 82 % Output Driver Rise and Fall Time See Figure 2 80 nsec Output Driver Deadtime 1 See Figure 2 5 %/f OSC Output Driver Deadtime 2 See Figure 2 80 nsec Turn-on Response Time I LOAD = 0A to 14.2A 10 msec Oscillator Range 80 1000 KHz Oscillator Frequency C EXT = 100 pF 270 300 330 KHz Max Duty Cycle 90 95 %
Table 1. Output Voltage Programming Codes
- 0 = processor pin is tied to GND.
11111 N o C P U
PRODUCT SPECIFICATION RC5051 REV. 1.0.4 4/2/01 Typical Operating Characteristics (VCCA, VCCD = 5V, f OSC = 280 KHz, and T A = +25 C using circuit in Figure 1, unless otherwise noted) Efficiency vs. Output Current 65-5050-03 80.0 78.0 76.0 74.0 72.0 70.0 82.0 84.0 86.0 88.0 13579 1 1 1 3 V OUT = 2.8V VOUT = 2.0V 14.5 Output Current (A) Efficiency (%) Load Regulation, VOUT = 2.8 V 2.77 2.76 2.75 2.74 2.73 2.78 2.79 2.80 2.81 2.82 2.83 1 3 5 7 9 11 13 14.5 Output Current (A) VOUT (V) Output Voltage vs. Output Current, RSENSE = 6mΩ 1.0 0.5 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 Output Current (A) Output Programming, VID4 = 0 1.0 1.5 2.0 2.5 3.0 3.5 1.0 1.5 2.0 2.5 3.0 3.5 DAC Set Point VOUT (V)VOUT (V) Output Programming, VID4 = 1 DAC Set Point VOUT (V) 18 39 75 150 300 560 CEXT (pf) Oscillator Frequency vs. CEXT 250 450 650 850 1050 1250Frequency (KHz)
RC5051 PRODUCT SPECIFICATION REV. 1.0.4 4/2/01 Typical Operating Characteristics (continued) Output Ripple, 2.8V @ 14.2A Time (1µs/division) VOUT (20mV/div) Time (1µs/division) VOUT (50mV/div) Transient Response, 14.2A to 0.8A Time (1µs/division) VOUT (50mV/div) Transient Response, 0.8A to 14.2A 2V/div 5V/div Time (1µs/division) Switching Waveforms, 9A Load Output Startup, System Power-up HIDRV pin LODRV pin Time (2ms/division) VIN (1V/div ) VOUT (1V/div) 65-5051-12 2.10V 2.00V 1.90V 2.10V 2.00V 1.90V
Figure 1. 15A Application Circuit for Pentium II Processors
Table 2. RC5051 Application Bill of Materials for Intel Pentium II Processors
- Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply
with Intel dl/dt requirements. L1 may be omitted if desired.
- For 14.2A designs using the FDP6030L MOSFETs, heatsinks with thermal resistance Θ
details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
2 N-Channel MOSFET
1 CuNi Alloy Wire Resistor
1 DC/DC Controller
Table 3. Recommended Values for CPU-based Applications Figure 2. Output Drive Test Circuit and Timing Diagram
300 MHz Intel Pentium
RC5051 PRODUCT SPECIFICATION 10 REV. 1.0.4 4/2/01
Application Information
The RC5051 is a programmable synchronous DC-DC con- troller IC. When designed around the appropriate external components, the RC5051 can be configured to deliver more than 19A of output current, as appropriate for the Klamath and Deschutes and other processors. The RC5051 functions as a fixed frequency PWM step down regulator. Main Control Loop Refer to the RC5051 Block Diagram on page 1. The RC5051 implements “summing mode control”, which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a set of comparators which provide the inputs to the digital control block. The signal conditioning section accepts inputs from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the differ- ence between the VFB signal the reference voltage from the DAC and presents the output to one of the summing ampli- fier inputs. The second, current control path, takes the differ- ence between the IFB and VFB pins and presents the resulting signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator. This output is then presented to a comparator, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator inputs and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. The digital block utilizes high speed Schottky transistor logic, allowing the RC5051 to operate at clock speeds as high as 1MHz. There are additional comparators in the analog control sec- tion whose function is to set the point at which the RC5051 enters its pulse skipping mode during light loads, as well as the point at which the current limit comparator disables the output drive signals to the external power MOSFETs. High Current Output Drivers The RC5051 contains two identical high current output drivers that utilize high speed bipolar transistors in a push- pull configuration. The drivers’ power and ground are sepa- rated from the chip’s power and ground for switching noise immunity. The HIDRV driver has a power supply pin, VCCQP, which is supplied from an external 12V source through a series resistor or from a charge-pump circuit powered from 5V if 12V is not available. The LODRV driver has a power supply pin, VCCP, which can be supplied from either the 12V or 5V source. The resulting voltages are suffi- cient to provide the gate to source drive to the external MOSFETs required in order to achieve a low R DS,ON. Internal Voltage Reference The reference included in the RC5051 is a precision band- gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0–VID4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V . For guar- anteed stable operation under all loading conditions, 0.1µF of decoupling capacitance should be connected to the VREF pin. No load should be connected to VREF. Power Good (PWRGD) The RC5051 Power Good function is designed in accordance with the Pentium II DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than ±12% of its nominal setpoint. The Power Good flag provides no other control function to the RC5051. Output Enable (ENABLE) The RC5051 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the out- put voltage. When disabled, the PWRGD output is in the low state. If an enable is not required in the circuit, this pin may be left open. Over-Voltage Protection The RC5051 constantly monitors the output voltage for pro- tection against over voltage conditions. If the voltage at the VFB pin exceeds 20% of the selected program voltage, an over-voltage condition is assumed and the RC5051 disables the output drive signal to the external MOSFETs. The DC- DC converter returns to normal operation after the fault has been removed. Over-Current Protection Current sense is implemented in the RC5051 to reduce the duty cycle of the output drive signal to the MOSFETs when an over-current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to an internal comparator. When the voltage
RC5051 PRODUCT SPECIFICATION 14 REV. 1.0.4 4/2/01
- The traces that run from the RC5051 IFB (pin 4) and VFB (pin 5) pins should be run together next to each other and Kelvin connected to the sense resistor. Running these lines together rejects some of the common mode noise that is presented to the RC5051 feedback input. Try, as much as possible, to run the noisy switching signals (HIDRV , LODRV & VCCQP) on one layer, but use the inner layers for power and ground only. If the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing sign VFB and IFB.
- A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. PC Motherboard Sample Layout and Gerber File A reference design for motherboard implementation of the RC5051 along with the PCAD layout Gerber file and silk screen can be obtained from our marketing department at 650-968-9211 x 7833. RC5051 Evaluation Board Fairchild Semiconductor provides an evaluation board to verify the system level performance of the RC5051. It serves as a guide to performance expectations when using the sup- plied external components and PCB layout. Please call the marketing department at 650-968-9211 x 7833 for an evalua- tion board. Additional Information For additional information contact the Fairchild Semiconductor’s Analog & Mixed Signal Products Group Marketing Department at 650-968-9211 x 7833.
PRODUCT SPECIFICATION RC5051 REV. 1.0.4 4/2/01 15 Mechanical Dimensions – 20 Lead SOIC A .093 .104 2.35 2.65 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .004 .012 0.10 0.30 .020 0.51B .013 0.33 C .009 .013 0.23 0.32 E .291 .299 7.40 7.60 e .394 .419 10.00 10.65 .010 .029 0.25 0.75 H .050 BSC 1.27 BSC h L .016 .050 0.40 1.27 0° 8° 0° 8° N2 0 2 0 α ccc .004 0.10—— D .496 .512 12.60 13.00 Notes: Dimensioning and tolerancing per ANSI Y14.5M-1982. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). "L" is the length of terminal for soldering to a substrate. Terminal numbers are shown for reference only. "C" dimension does not include solder finish thickness. Symbol "N" is the maximum number of terminals. D A A1 – C – ccc C LEAD COPLANARITY SEATING PLANEe B L h x 45° C α EH
RC5051 PRODUCT SPECIFICATION 4/2/01 0.0m 003 Stock#DS30005051 2001 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com