RC4558 TI1 | Alldatasheet

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Sample & Buy T echnical Documents Tools & Software Support & Community RC4558 SLOS073G –MARCH 1976–REVISED OCTOBER 2014 RC4558DualGeneral-PurposeOperationalAmplifier

1 Features 3 Description

The RC4558 device is a dual general-purpose 1• Continuous Short-Circuit Protection operational amplifier, with each half electrically similar• Wide Common-Mode and Differential Voltage to the μA741, except that offset null capability is notRanges provided.

  • No Frequency Compensation Required The high common-mode input voltage range and the• Low Power Consumption absence of latch-up make this amplifier ideal for
  • No Latch-Up voltage-follower applications. The device is short- circuit protected, and the internal frequency• Unity-Gain Bandwidth: 3 MHz Typ compensation ensures stability without external• Gain and Phase Match Between Amplifiers components.
  • Low Noise: 8 nV/√Hz Typ at 1 kHz Device Information(1)

2 Applications PART NUMBER PACKAGE (PIN) BODY SIZE

SOIC (8) 4.90 mm × 3.91 mm• DVD Recorders and Players SOIC (8) 3.00 mm × 3.00 mm• Pro Audio Mixers RC4558 PDIP (8) 9.81 mm × 6.35 mm TSSOP (8) 3.00 mm × 4.40 mm SOP (8) 6.20 mm × 5.30 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Noninverting Amplifier Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLOS073G –MARCH 1976–REVISED OCTOBER 2014 www.ti.com Table of Contents

4 Revision History

Changes from Revision F (September 2010) to Revision G Page

  • Added Applications, Device Information table, Handling Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout

2 Submit Documentation Feedback Copyright © 1976–2014, Texas Instruments Incorporated

Product Folder Links: RC4558

1IN− 1IN+ VCC− VCC+ 2OUT 2IN− 2IN+ D, DGK, P, PS, OR PW PACKAGE (TOP VIEW) RC4558 www.ti.com SLOS073G –MARCH 1976–REVISED OCTOBER 2014

5 Pin Configuration and Functions

NAME NO. 1IN+ 3 I Noninverting input 1IN- 2 I Inverting Input 1OUT 1 O Output 2IN+ 5 I Noninverting input 2IN- 6 I Inverting Input 2OUT 7 O Output VCC+ 8 — Positive Supply VCC- 4 — Negative Supply Copyright © 1976–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: RC4558

SLOS073G –MARCH 1976–REVISED OCTOBER 2014 www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC+ 18 Supply voltage(2) V VCC– –18 VID Differential input voltage(3) ±30 V VI Input voltage (any input)(2)(4) ±15 V Duration of output short circuit to ground, one amplifier at a time(5) Unlimited TJ Operating virtual junction temperature 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–. (3) Differential voltages are at IN+ with respect to IN–. (4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. (5) Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.

6.2 Handling Ratings

Tstg Storage temperature range -65 150 °C Human body model (HBM), per AEC Q100-002(1) 0 500 V(ESD) Electrostatic discharge V Charged device model (CDM), per AEC Q100-011 (2) 0 1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

VCC– –5 –15 RC4558 0 70 TA Operating free-air temperature °C RC4558I –40 85

6.4 Thermal Information

THERMAL METRIC(1) D DGK P PS PW UNIT

8 PINS

RθJA Junction-to-ambient thermal resistance 97 172 85 95 149 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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Product Folder Links: RC4558

www.ti.com SLOS073G –MARCH 1976–REVISED OCTOBER 2014

6.5 Electrical Characteristics

at specified free-air temperature, VCC+ = 15 V, VCC– = –15 V TESTPARAMETER TA (2) MIN TYP MAX UNITCONDITIONS(1) 25°C 0.5 6 VIO Input offset voltage VO = 0 mV Full range 7.5 25°C 5 200 IIO Input offset current VO = 0 nA Full range 300 25°C 150 500 IIB Input bias current VO = 0 nA Full range 800 VICR Common-mode input voltage range 25°C ±12 ±14 V RL = 10 kΩ 25°C ±12 ±14 VOM Maximum output voltage swing 25°C ±10 ±13 V RL = 2 kΩ Full range ±10 25°C 20 300RL ≥ 2 kΩ,AVD Large-signal differential voltage amplification V/mVVO = ±10 V Full range 15 B1 Unity-gain bandwidth 25°C 3 MHz ri Input resistance 25°C 0.3 5 MΩ CMRR Common-mode rejection ratio 25°C 70 90 dB VCC = ±15 VkSVS Supply-voltage sensitivity (ΔVIO/ΔVCC) 25°C 30 150 μV/Vto ±9 V AVD = 100, RS = 100 Ω,Vn Equivalent input noise voltage (closed loop) 25°C 8 nV/√Hzf = 1 kHz, BW = 1 Hz 25°C 2.5 5.6 VO = 0,ICC Supply current (both amplifiers) TA min 3 6.6 mANo load TA max 2.3 5 25°C 75 170 VO = 0,PD Total power dissipation (both amplifiers) TA min 90 200 mWNo load TA max 70 150 Open loop 85RS = 1 kΩ,VO1/VO2 Crosstalk attenuation 25°C dBf = 10 kHzAVD = 100 105 (1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. (2) Full range is 0°C to 70°C for RC4558 and –40°C to 85°C for RC4558I.

6.6 Operating Characteristics

VCC+ = 15 V, VCC– = –15 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Rise time VI = 20 mV, RL = 2 kΩ, CL = 100 pF 0.13 ns Overshoot VI = 20 mV, RL = 2 kΩ, CL = 100 pF 5% SR Slew rate at unity gain VI = 10 V, RL = 2 kΩ, CL = 100 pF 1.1 1.7 V/μs Copyright © 1976–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: RC4558

6.7 Typical Characteristics

Figure 1. Supply Current vs Supply Voltage Figure 2. Supply Current vs Temperature Figure 3. Gain and Phase vs Frequency Figure 4. Gain and Phase vs Frequency Figure 5. Output Voltage Swing vs Supply Voltage Figure 6. Output Voltage Swing vs Frequency

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Figure 13. Input Noise Voltage vs Frequency

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IN− VCC− VCC+ RC4558 www.ti.com SLOS073G –MARCH 1976–REVISED OCTOBER 2014

7 Detailed Description

7.1 Overview

The RC4558 device is a dual general-purpose operational amplifier, with each half electrically similar to the μA741, except that offset null capability is not provided. The high common-mode input voltage range and the absence of latch-up make this amplifier ideal for voltage- follower applications. The device is short-circuit protected, and the internal frequency compensation ensures stability without external components.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Unity-Gain Bandwidth

The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without greatly distorting the signal. The RC4558 device has a 3-MHz unity-gain bandwidth.

7.3.2 Common-Mode Rejection Ratio

The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to the change in the input voltage, then converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers are designed to have it as high as possible. The CMRR of the RC4558 device is 90 dB.

7.3.3 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. The RC4558 device has a 1.7 V/μs slew rate.

7.4 Device Functional Modes

The RC4558 device is powered on when the supply is connected. Each of these devices can be operated as a single supply operational amplifier or dual supply amplifier depending on the application. Copyright © 1976–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: RC4558

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Typical Application

VOUT+ and VOUT– range from 2 V to 10 V. The difference, VDIFF, is the difference between VOUT+ and VOUT–. Figure 14. Schematic for Single-Ended Input to Differential Output Conversion

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/c43 /c45 /c43/c230 /c246/c61 /c61 /c231 /c247 /c232 /c248 2 4 2 D IF F O U T O U T IN R E F 1 3 4 1 R R RV V V V 1 V 1 R R R R/c43 /c45 /c230 /c246/c230 /c246 /c230 /c246/c61 /c45 /c61 /c180 /c43 /c45 /c180 /c43 /c231 /c247/c231 /c247 /c231 /c247 /c43/c232 /c248 /c232 /c248 /c232 /c248 4 2 2 out ref in 3 4 1 1 R R RV V 1 V R R R R /c45 /c230 /c246 /c230 /c246/c61 /c180 /c180 /c43 /c45 /c180 /c231 /c247 /c231 /c247/c43 /c232 /c248/c232 /c248 OUT REF 3 4 1 1 IN RC4558 www.ti.com SLOS073G –MARCH 1976–REVISED OCTOBER 2014 Typical Application (continued)

8.1.1 Design Requirements

The design requirements are as follows:

  • Supply voltage: 15 V
  • Reference voltage: 12V
  • Input: 2 V to 10 V
  • Output differential: ±8 V

8.1.2 Detailed Design Procedure

The circuit in Figure 14 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and VOUT– using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a buffered version of the input signal, VIN (see Equation 1). VOUT– is the output of the second amplifier which uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for VOUT– is Equation 2. VOUT+ = VIN (1) (2) The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and VOUT–. Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the reference voltage and the maximum output of each amplifier is equal to the VREF. The differential output range is 2×VREF. Furthermore, the common mode voltage will be one half of VREF (see Equation 7). (3) VOUT+ = VIN (4) VOUT– = VREF – VIN (5) VDIFF = 2×VIN – VREF (6) (7)

8.1.2.1 Amplifier Selection

Linearity over the input range is key for good dc accuracy. The common mode input range and the output swing limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required. Bandwidth is a key concern for this design. Because RC4558 has a bandwidth of 3 MHz, this circuit will only be able to process signals with frequencies of less than 3 MHz.

8.1.2.2 Passive Component Selection

Because the transfer function of VOUT– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low tolerances to maximize performance and minimize error. This design used resistors with resistance values of 36 kΩ with tolerances measured to be within 2%. But, if the noise of the system is a key parameter, the user can select smaller resistance values (6 kΩ or lower) to keep the overall system noise low. This ensures that the noise from the resistors is lower than the amplifier noise. Copyright © 1976–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: RC4558

8.1.3 Application Curves

voltage from 0 V to 12 V. However, this design should only be used between 2 V and 10 V for optimum linearity. Figure 15. Differential Output Voltage Node vs Input Figure 16. Positive Output Voltage Node vs Input Voltage Figure 17. Positive Output Voltage Node vs Input Voltage

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www.ti.com SLOS073G –MARCH 1976–REVISED OCTOBER 2014

9 Power Supply Recommendations

The RC4558 device is specified for operation from ±5 V to ±15 V; many specifications apply from –0°C to 70°C. The Typical Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages outside of the ±18-V range can permanently damage the device (see the Absolute Maximum Ratings ). Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines. Copyright © 1976–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: RC4558

10 Layout

10.1 Layout Guidelines

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, (SLOA089).
  • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Example.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

Figure 18. Operational Amplifier Schematic for Noninverting Configuration Figure 19. Operational Amplifier Board Layout for Noninverting Configuration

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11 Device and Documentation Support

11.1 Trademarks

All trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.3 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Copyright © 1976–2014, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: RC4558

www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples RC4558-W ACTIVE WAFERSALE YS 0 TBD Call TI Call TI RC4558D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 RC4558 RC4558DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 RC4558 RC4558DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 RC4558 RC4558DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 (YRP ~ YRS ~ YRU) RC4558DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 (YRP ~ YRS ~ YRU) RC4558DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 RC4558 RC4558DRG3 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 RC4558 RC4558DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 RC4558 RC4558ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I RC4558IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 (YSP ~ YSS ~ YSU) RC4558IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (YSP ~ YSS ~ YSU) RC4558IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I RC4558IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I RC4558IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 RC4558IP RC4558IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 RC4558IP RC4558IPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I

www.ti.com 24-Apr-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples RC4558IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 R4558I RC4558IPWRE4 ACTIVE TSSOP PW 8 TBD Call TI Call TI -40 to 85 RC4558IPWRG4 OBSOLETE TSSOP PW 8 TBD Call TI Call TI -40 to 85 RC4558P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 RC4558P RC4558PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 RC4558P RC4558PSLE OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70 RC4558PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 R4558 RC4558PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 R4558 RC4558PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 R4558 RC4558PWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI 0 to 70 RC4558PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 R4558 RC4558PWRE4 ACTIVE TSSOP PW 8 TBD Call TI Call TI 0 to 70 RC4558PWRG4 OBSOLETE TSSOP PW 8 TBD Call TI Call TI 0 to 70 RC4558Y OBSOLETE DIESALE Y 0 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

www.ti.com 24-Apr-2015 Addendum-Page 3 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) RC4558DGKR VSSOP DGK 8 2500 364.0 364.0 27.0 RC4558DR SOIC D 8 2500 340.5 338.1 20.6 RC4558DR SOIC D 8 2500 364.0 364.0 27.0 RC4558DR SOIC D 8 2500 367.0 367.0 35.0 RC4558DRG3 SOIC D 8 2500 364.0 364.0 27.0 RC4558DRG4 SOIC D 8 2500 340.5 338.1 20.6 RC4558DRG4 SOIC D 8 2500 367.0 367.0 35.0 RC4558IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 RC4558IDR SOIC D 8 2500 340.5 338.1 20.6 RC4558IPWR TSSOP PW 8 2000 364.0 364.0 27.0 RC4558IPWR TSSOP PW 8 2000 367.0 367.0 35.0 RC4558PSR SO PS 8 2000 367.0 367.0 38.0 RC4558PWR TSSOP PW 8 2000 367.0 367.0 35.0 RC4558PWR TSSOP PW 8 2000 364.0 364.0 27.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2015 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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