RC4200

RC4200 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

• High accuracy
• Nonlinearity – 0.1% Temperature coefficient – 0.005%/°C
• Multiple functions
• Multiply, divide, square, square root, RMS-to-DC conversion, AGC and modulate/demodulate
• Wide bandwidth – 4 MHz
• Signal-to-noise ratio – 94 dB

Applications

• Low distortion audio modulation circuits
• V oltage-controlled active filters
• Precision oscillators

Description

The RC4200 analog multiplier has complete compensation for nonlinearity, the primary source of error and distortion. This multiplier also has three onboard operational amplifiers designed specifically for use in multiplier logging circuits. These amplifiers are frequency compensated for optimum AC response in a logging circuit, the heart of a multiplier, and can therefore provide superior AC response. The RC4200 can be used in a wide variety of applications without sacrificing accuracy. Four-quadrant multiplication, two-quadrant division, square rooting, squaring and RMS conversion can all be easily implemented with predictable accuracy. The nonlinearity compensation is not just trimmed at a single temperature, it is designed to provide compensa- tion over the full temperature range. This nonlinearity compensation combined with the low gain and offset drift inherent in a well-designed monolithic chip provides a very high accuracy and a low temperature coefficient. Block Diagram 65-4200-01 RC4200 VOS2 VOS1 Q3 Q4 I1Q1Q2 RC4200 Analog Multiplier

RC4200 PRODUCT SPECIFICATION 2 REV. 1.2.1 6/14/01 Functional Description The RC4200 multiplier is designed to multiply two input currents (I1 and I2) and to divide by a third input current (I4). The output is also in the form of a current (I3). A simplified circuit diagram is shown in the Block Diagram. The nominal relationship between the three inputs and the output is: The three input currents must be positive and restricted to a range of 1 µA to 1 mA. These currents go into the multiplier chip at op amp summing junctions which are nominally at zero volts. Therefore, an input voltage can be easily converted to an input current by a series resistor. Any number of currents may be summed at the inputs. Depending on the application, the output current can be converted to a voltage by an external op amp or used directly. This capa- bilty of combining input currents and voltages in various combinations provides great versatility in application. Inside the multiplier chip, the three op amps make the collector currents of transistors Q1, Q2 and Q4 equal to their respective input currents (I 1, I2, and I4). These op amps are designed with current source outputs and are phase-compen- sated for optimum frequency response as a multiplier. Power drain of the op amps was minimized to prevent the introduc- tion of undesired thermal gradients on the chip. The three op amps operate on a single supply voltage (nominally -15V) and total quiescent current drain is less than 4 mA. These special op amps provide significantly improved performance in comparison to 741-type op amps. The actual multiplication is done within the log-antilog configuration of the Q1-Q4 transistor array. These four transistors, with associated proprietary circuitry, were specially designed to precisely implement the relationship. I I1I2 VBEN kT ICN ISN Previous multiplier designs have suffered from an additional undesired linear term in the above equation; the collector current times the emitter resistance. The I CrE term intro- duces a parabolic nonlinearity even with matched transistors. Fairchild Semiconductor has developed a unique and propri- etary means of inherently compensating for this undesired I CrE term. Furthermore, this Fairchild Semiconductor devel- oped circuit technique compensates linearity error over tem- perature changes. The nonlinearity versus temperature is significantly improved over earlier designs. From equation (2) and by assuming equal transistor junction temperatures, summing base-to-emitter voltage drops around the transistor array yields: This equation reduces to: The rate of reverse saturation current I S1IS2/IS3IS4, depends on the transistor matching. In a monolithic multiplier this matching is easily achieved and the rate is very close to unity, typically 1.0±1%. The final result is the desired relationship: The inherent linearity and gain stability combined with low cost and versatility makes this new circuit ideal for a wide range of nonlinear functions. KT I IS1 IS2 IS3 IS4 I1I2 I3I4 IS1 IS2 IS3 IS4 I1I2 Pin Assignments VOS2 –VS I3 (Output) VOS1 GND 65-4200-07

PRODUCT SPECIFICATION RC4200 REV. 1.2.1 6/14/01 3 Absolute Maximum Ratings Notes: 1. For a supply voltage greater than -22V, the absolute maximum input voltage is equal to the supply voltage. 2. Observe package thermal characteristics. Thermal Characteristics (Still air, soldered into PC board) Parameter Min. Max. Unit Supply Voltage1 -22 V Input Current -5 mA Storage Temperature Range RC4200/4200A -55 +125 °C Operating Temperature Range RC4200/4200A 0 +70 °C 8-Lead Plastic DIP 8-Lead SOIC Maximum Junction Temperature +125 °C +125 ˚C Maximum PD TA < 50°C 468mW 300mW Thermal Resistance θJC —— Thermal Resistance θJA 160°C/W 240 ˚C/W For TA > 50°C Derate at 6.25mW/ °C 4.17mW/ ˚C

Electrical Characteristics

(Over operating temperature range, VS = -15V unless otherwise noted) Parameters Test Conditlons 4200A 4200 Total Error as Multiplier TA = +25 °C Untrimmed1 ±2.0 ±3.0 % With External Trim ±0.2 ±0.2 % Versus Temperature ±0.005 ±0.005 %/ °C Versus Supply (-9 to -18V) ±0.1 ±0.1 %/V Nonlinearity2 50µA ≤ I1,2,4 ≤ 250 µA, TA = +25°C ±0.1 ±0.3 % Input Current Range (I1, I2 and I4) 1.0 1000 1.0 1000 µA Input Offset Voltage I 1 = I2 = I4 = 150 µA TA = +25°C ±5.0 ±10 mV Input Bias Current I 1 = I2 = I4 = 150 µA TA = +25°C 300 500 nA Average Input Offset Voltage Drift I1 = I2 = I4 = 150 µA ±50 ±100 µV/ °C Output Current Range (I3)3 1.0 1000 1.0 1000 µA

Figure 5. Multiplying Circuit Offset Adjust

1. Set all trimmer pots to 0V on the wiper.
2. Connect V X input to ground. Put in a full scale square

on V0 output (adjust for 0 feedthrough).

1. Connect V Y input to ground. Put in a full scale square

on V0 output (adjust for 0 feedthrough).

1. Connect V X and VY to ground. Adjust VOS(R16) for 0V

Figure 6. Extended Range Divider

Figure 7. Divider Circuit with Offset Adjustment

PRODUCT SPECIFICATION RC4200 REV. 1.2.1 6/14/01 9 Divider Circuit Offset Adjustment Procedure 1. Set each trimmer pot to 0V on the wiper. 2. Connect V X (input) to ground. Put a DC voltage of approximatey 1/2 VZ (max.) DC on the VZ (input) with an AC (squarewave is easiest) voltage of 1/2 VZ (max.) peak-to-peak superimposed on it. Adjust XOS (R5) for zero feedthrough. (No AC at V0) 3. Connect V X (input) to VZ (input) and put in the 1/2 VZ(max.) DC with an AC of approximately 20 mV less than VZ(max.). Adjust ZOS (R13) for zero feedthrough. 4. Return V X (Input) to ground and connect VZ(max.) DC on VZ(input). Adjust output VOS(R17) for VO = 0VO 5. Connect V X (input) to VZ (input) and and in VZ (max.) DC. (The output will equal K.) Decrease the input slowly until the output (V 0 - K) deviates beyond the desired accuracy. Adjust ZOS to bring it back into toler- ance and return to Step 4. Continue steps 4 and 5 until V Z reduces to the lowest value desired. Notice that as the input to VX and VZ gets closer to zero (an illegal state) the system noise will predominate so much that an integrating voltmeter will be very helpful. Square Root Circuit V0 = N√VX Figure 8. 1/2 V (Max.)z V (Max.) 1/2 V (Max.) z z 10 mV~~ V (Max.) 1/2 V (Max.) z z 65-1868 65-1877 RC4200 Multiplier V (Input) S X O O S ao Ra Rb R R V (Output) S-V 3 6 Rc Rd I1 I4 REF+V VXVREF R1Rb VREF RaRb V0VREF Rao Rb R0R4 V0VREF RcR4 V0VREF R0Rd VREF RcRd If RaRb RcRd and Rao RbR0Rd + Rao RbRcR4 RcRdR0R4== Then R0R4 VXVREF R1Rb

2 VXK where K =

and V0 NV X where N = K= 0V X VX max.() and V0 max.()≤≤ NV X max.()= N VX V0 max.() 2 Ra Rd VREF Rb Rc VREF V0 max.() Rao V0 max.() V0 max.()

1. Set both trimmer pots to 0V on the wiper.
2. Put in a full scale (0 to V X(max.) squarewave on VX
3. Connect V X input to ground. Adjust VOS(R13) for 0V

Figure 9. Square Root Circuit Offset Adjust

Figure 10. Squaring Circuit

2 RcRd and R1Ra 2RCX RD==

Figure 11. Squaring Circuit Offset Adjust

1. Set both trimmer pots to 0V on the wiper.
2. Put in a full scale (±V X) squarewave on VX input.

Adjust ZOS(R10) for uniform output.

1. Connect V X input to ground. Adjust VOS(R11) for 0V

• Nonimearity—Incremental deviation from absolute accuracy. See Note 1.
• Scaling Error—Linear deviation from absolute accuracy.
• Output Offset—Constant deviation from absolute accuracy.
• Feedthrough.—Cross-product errors caused by input offsets and external circuit limitations. See Note 2. This nonlinearity error in the transfer function of the RC4200 is ±0.1% maximum (±0.03 maximum for the RC4200A). That is, The other system errors are caused by voltage offsets on the inputs of the RC4200 and can be as high as ±3.0% (±2.0% for RC4200A). Figure 12. Notes: 1. The input circuits tend to become unstable at I1, I2, I4 < 50 µA and linearity decreases when I 1, I2, I4 > 250 µA (e.g., @ I1 = I2 = 500µA nonlinearity error ≈ 0.5%). 2. This section will not deal with feedthrough which is proportional to frequency of operation and caused by stray capacitance and/or bandwidth limitations. (refer to Figure 12.) 3. Not including resistor tolerance or output offset on the operational amplifier. 4. For 50 µA ≤ I 1, I2, I4 ≤ 250 µA. I1I2 VXVY VZ R0R4 R1R2 65-1871 RC4200 Multiplier V V S X Y OS O S R V +V3 6 I1 I4 V Z Ideal Op-Amp V = 0 O Errors Caused by Input Offsets System errors can be greatly reduced by externally trimming the input offset voltages of the RC4200. (±3.0% F.S. for RC4200 and ±0.1% for RC4200A.) If X OS = XOSX, YOS = YOSY, ZOS = -VOSZ,

Figure 13. RC4200 with Input Offset Adjustment equivalent feedthrough or output offset error. See Figure 6. output op amp offset adjust, VOS (R16).

100 R4 ZOSX OS

RC4200 PRODUCT SPECIFICATION 14 REV. 1.2.1 6/14/01 Reducing Mismatch Errors You need not use 0.01% resistors to reduce resistor product mismatch errors. Here are a couple of ways to obtain maximum accuracy out of the extended range multiplier (see Figure 4) using 1% resistors. Method 1 VX feedthrough, for example, occurs when VY = 0 and VOSY ≠ 0. This VX feedthrough will equal ±VXVOSY. Also, if VOSZ ≠ 0, there is a VX feedthrough equal to VXVOSZ. A resistor-product error of α will cause a VX feedthrough of ±αVX. Likewise, VY feedthrough errors are: ±VYVOSX, ±VYVOSZ and ±βVY Total feedthrough: ±VXVOSY ±VYVOSX ±αVX ±βVY ±(VX + VY) VOSZ By carefully abusing XOS(R5), YOS(R9) and ZOS(R20) this equation can be made to very nearly equal zero and the feedthrough error will practically disappear. A residual of set will probably remain which can be trimmed outwith V OS(R16) at the output of amp. Method 2 Notice that the ratios of R1Rb:RCXRd and R2Ra:RCYRd are both dependent of Rd also that R1, R2, Ra and Rb are all functions of the maximum input requirements. By designing a multiplier for the same input ranges on both V X and VY then R1 = R2, RCX = RCY and Ra = Rb. (Note: it is accept- able to design a four quadrant multiplier and use only two quadrants of it.) Select R d to be 1% or 2% below (or above) the calculated value. This will cause α and β to both be positive (or nega- tive) by nearly the same amount. Now the effective value of R d can be trimmed with an offset adjustment ZOS(R20) on pin 5. This technique causes: a slight gain error which can be com- pensated with the R0 value, and an output of offset error that can be trimmed with VOS(R16) on the output op amp. Extended Range Divider The only cross-product error of interest is the VZ feedthrough (VX = 0 and VOSX ≠ 0) which is easily adjusted with XOS(R5). See Figure 6. Resistor product mismatch will cause scaling errors (gain) that could be a problem for very low values of VZ. Adjust- ments to YOS(R18) can be made to improve the high gain accuracy. Square Root and Squaring These circuits are functions of single variables so feedthrough, as such, is not a consideration. Cross product errors will effect incremental accuracy that can be corrected Y OS(R14) or ZOS(R10). See Figure 9 and Figure 11.

PRODUCT SPECIFICATION RC4200 REV. 1.2.1 6/14/01 15 Appendix 2— Applications Design Considerations for RMS-to-DC Circuits Average Value Consider Vin = Asinωτ. By definition, Where T = Period ω = 2πf RMS Value Again, consider VIN = Asinωt Therefore, the rms value of Asinωt becomes: RMS Value for Rectified Sine Waves Consider Vin = |A sin ωt|, a rectified wave. To solve, integrate of each half cycle. Practical Consideration: |Asinωt| has high-order harmonics; Asinωt does not. Therefore, non-ideal integrators may cause different errors for two approaches. Figure 14. VAG VIN td T 2--- AVIN T t 65-1873 VAG T--- A ωtsin t d T 2--- ω---- ωt cos– T 2--- Average Value of Asinωt is 2 π---A Vrms VAVG T--- VIN[] 2 td T ∫== Vrms for Asinωtdt: Vrms T--- A2sin2ωt dt T Vrms 2--- 1 2---cos 2 cos 2 ωt–d t T Vrms 2--- 1 T Vrms 2---= Vrms Vrms A i.e. 1 T--- TVin 2 dt = T--- A2sin2ωt dt+ Asin ωt–() 2dtT 2--- T T 2--- This is the same as 1 1--- TA2sin2ωttd so, |Asinωt|rms Asinωtrms= Low Pass Filter b Absolute Value Low Pass Filter VIN V = A V O VG IN2 V = VO IN rms 65-4200-09 (a) VIN VIN (b) OV VIN Avg VIN implies V0 Avg V IN 2()= V0 Avg V IN

Amplitude Modulator with A.G.C. factor even though the carrier varies in amplitude. the carrier variation and modulating input. range circuits, in terms of the input voltages. Figure 15. RMS to DC Converter VOUT=√VIN2 *Determines sacle factor (K) for X function. **Determines sacle factor (K) for X function.

Figure 16. Amplitude Modulator with A.G.C.

RC4200 PRODUCT SPECIFICATION 18 REV. 1.2.1 6/14/01 Limited Range, First Quadrant Applications The following circuit has the advantage that cross-product errors are due only to input offsets and nonlinearity error is sightly error is slightly less for lower input currents. The circuit also has no standby current to add to the noise content, although the signal-to-noise ratio worsens at very low input currents (1-5 µA) due to the noise current of the input stages. The R SCS filter circuits are added to each input to improve the stability for input currents below 50 µA. Caution! The bandpass drops off significantly for lower currents (<50 µA) and non-symmetrical rise and fall times can cause second harmonic distortion. Thermal Symmetry The scale factor is sensitive to temperature gradients across the chip in the lateral direction. Where possible, the package should be oriented such that forces generating temperature gradients are located physically on the line of thermal sym- metry. This will minimize scale-factor error due to thermal gradients. VOS2 –VS Output I3 VOS1 GND Thermal Symmetry Line 65-0070 65-1867 RC4200 Multiplier S X SR1 100 S-V 3 6 V 4156 R 100 V 50 mV S-V S+V 100 µ

0.1 FS-V

µ0.1 F O S+V S-V µ ZV YV Inputs Cs Rs V OS1 0.1 F Rs Cs V OS2 50 mV 50 mV V ADJOS4 100 R4 Gain Adj. R Output VOVOS3 µ O R = 10K, C = 0.005 F V = KV V V XY zs Where K = R R4 R1 R2 O S S µ

Figure 18. Outputs

150 A dc

200 A ac*µ

250 A dc

250 A dcµ

200 A ac*

167 A dcµ

PRODUCT SPECIFICATION RC4200 REV. 1.2.1 6/14/01 21 Mechanical Dimensions 8-Lead SOIC Package D A – C – ccc C LEAD COPLANARITY SEATING PLANEe B L h x 45° C α EH A .053 .069 1.35 1.75 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .004 .010 0.10 0.25 .020 0.51B .013 0.33 C .008 .010 0.20 0.25 E .150 .158 3.81 4.01 e .228 .244 5.79 6.20 .010 .020 0.25 0.50 H .050 BSC 1.27 BSC h L .016 .050 0.40 1.27 0° 8° 0° 8° N8 8 α ccc .004 0.10—— D .189 .197 4.80 5.00 Notes: Dimensioning and tolerancing per ANSI Y14.5M-1982. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). "L" is the length of terminal for soldering to a substrate. Terminal numbers are shown for reference only. "C" dimension does not include solder finish thickness. Symbol "N" is the maximum number of terminals.

RC4200 PRODUCT SPECIFICATION 22 REV. 1.2.1 6/14/01 Mechanical Dimensions (continued) 8-Lead Plastic DIP Package A — .210 — 5.33 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .015 — .38 — .022 .56B .014 .36 B1 .045 .070 1.14 1.78 D .348 .430 8.84 10.92 .300 .325 7.62 8.26 .240 .280 6.10 7.11 E e — .430 — 10.92 .005 — .13 — A2 .115 .195 2.93 4.95 .100 BSC 2.54 BSC eB .115 .160 2.92 4.06L 8° 8° 5N C .008 .015 .20 .38 Notes: Dimensioning and tolerancing per ANSI Y14.5M-1982. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). Terminal numbers are for reference only. "C" dimension does not include solder finish thickness. Symbol "N" is the maximum number of terminals. D e B A L 5 8 E eB C

RC4200 PRODUCT SPECIFICATION 6/14/01 0.0m 003 Stock#DS30004841 © 2001 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

Ordering Information

Part Number Package Operating Temperature Range RC4200N 8-Lead Plastic DIP 0 °C to +70°C RC4200AN 8-Lead Plastic DIP 0 °C to +70°C RC4200M 8-Lead SOIC 0 °C to +70°C RC4200AM 8-Lead SOIC 0 °C to +70°C