RC38612ADDDGN2HB0

RC38612 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Renesas Electronics Corporation
• PDF pages: 99

Technical content

Datasheet sections

Features

▪ Six independent timing channels

• Each can act as a frequency synthesizer, jitter attenuator, Digitally Controlled Oscillator (DCO), or Digital Phase Lock Loop (DPLL)
• Generates output frequencies that are independent of input frequencies via a Fractional Output Divider (FOD)
• Each FOD supports output phase tuning with 1ps ▪ 12 differential / 24 LVCMOS outputs
• Any frequency from 0.5Hz to 1GHz (250MHz for LVCMOS)
• Jitter below 150fs RMS (10kHz to 20MHz)
• Supports LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL output modes
• Differential output swing is selectable: 400mV / 650mV / 800mV / 910mV
• Independent output voltages of 3.3V, 2.5V, or 1.8V ▪ LVCMOS additionally supports 1.5V or 1.2V swings
• The clock phase of each output is individually programmable in 1ns to 2ns steps with a total range of ±180° ▪ 5 differential / 10 single-ended clock inputs
• Supports any frequency from 0.5Hz to 1GHz
• Any input can be mapped to any or all of the timing channels
• Redundant inputs frequency independent of each other
• Any input can be designated as external frame/sync pulse of EPPS (even pulse per second), 1PPS (Pulse per Second), 5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz associated with a selectable reference clock input
• Per-input programmable phase offset of up to ±1.638 s in 1ps steps ▪ Three GPIOs can be configured as single-ended clock inputs supporting frequencies from 0.5Hz to 150MHz ▪ Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring, and/or LOS input pins
• Loss of Signal (LOS) input pins (via GPIOs) can be assigned to any input clock reference ▪ Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive, and other programmable settings ▪ System APLL operates from fundamental-mode crystal: 25MHz to 54MHz or from a crystal oscillator ▪ System DPLL accepts an XO, TCXO, or OCXO operating at virtually any frequency from 1MHz to 150MHz ▪ DPLLs can be configured as DCOs to synthesize Precision Time Protocol (PTP) / IEEE 1588 clocks
• DCOs generate PTP based clocks with frequency resolution less than 1.11 × 10-16 ▪ DPLL Phase detectors can be used as Time-to-Digital Converters (TDC) with precision below 1ps
• TDCs are readable at periods from 1ms to 100s ▪ DPLL Digital Loop Filters (DLFs) are programmable with cut off frequencies from 0.09mHz to 12kHz
• DPLL architecture supports the use of external DLFs implemented in software ▪ DPLL/DCO channels share frequency information using the Combo Bus to simplify compliance with ITU-T G.8273.2 ▪ Switching between DPLL and DCO modes is hitless and dynamic ▪ Supports 1MHz I 2C or 50MHz SPI serial processor ports ▪ Can configure itself automatically after reset via:
• Internal customer- definable One-Time Programmable (OTP) memory with up to 16 different configurations
• Standard external I 2C EEPROM is serial port in I2C mode ▪ 1149.1 JTAG Boundary Scan ▪ 10 × 10 × 0.9 mm 72-QFN package RC38612 Datasheet Radio Access Network Equipment Synchronizer

2©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Block Diagram Figure 1. Block Diagram

Description

The RC38612 Radio Access Network Equipment Synchronizer provides tools to manage timing references, clock sources and timing paths for IEEE 1588 / Precision Time Protocol (PTP), Synchronous Ethernet (SyncE), and CPRI based clocks. The device supports up to six independent timing paths that can be used to control PTP clock synthesis and SyncE/CPRI clock generation. The device supports physical layer timing with DPLLs and packet based timing with DCOs. Input-to- input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces; as well as IEEE 1588 Time Stamp Units (TSUs). Reference Monitors Reference Switching State Machines Q5Out Out Combo Bus System DPLL FOD To FODs OSCI OSCOXO_DPLL SPI/I2C GPIO / JTAG St atus and Configuration Registers OTPI2C Master Q0Out Q1Out Q3Out GPIO[0] GPIO[3] Sy stem APLL Osc DPLL / DCO_0 FOD Out Q11 Out Out Q10Out Q9Out Q7Out DPLL / DCO_1 FOD Q4Out Q2Out DPLL / DCO_2 FOD DPLL / DCO_3 FOD CLK0 CLK1 DPLL / DCO_5 FOD DPLL / DCO_7 FOD CLK2 CLK3 CLK4 Div Div Div Div Div Div Div Div Div Div Div Div 012357

3©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet The RC38612 accepts up to five differential reference inputs and up to ten single-ended reference inputs that can operate at common GNSS, Ethernet, SONET/SDH, PDH frequencies, and any input frequency from 0.5Hz to 1GHz (250MHz in single-ended mode). The references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to all the DPLLs. The active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities, locking allowances, reference monitors, revertive and non-revertive settings, and LOS inputs. The RC38612 can accept a clock reference and an associated frame pulse or sync signal as a pair. The DPLLs can lock to the clock reference and align the sync and clock outputs with the paired sync/frame input. The device allows any of the reference inputs to be configured as sync inputs that can be associated with any of the other reference inputs. The input sync signals can have a frequency of 1PPS (Pulse per Second), EPPS (even pulse per second), 5PPS, 10PPS, 50Hz, 100Hz, 1kHz, 2kHz, 4kHz, and 8 kHz. This feature enables any DPLL to phase align its frame sync and clock outputs with a sync input without the need to use a low bandwidth setting to lock directly to the sync input. The DPLLs support four primary operating modes: Free-Run, Locked, Holdover, and DCO. In Free-Run mode, the DPLLs synthesize clocks based on the system clock alone. In Locked mode, the DPLLs filter reference clock jitter with the selected bandwidth. Also in Locked mode, the long-term output frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data acquired while in Locked mode to generate accurate frequencies when input references are not available. In DCO mode, the DPLL control loop is opened and the DCO can be controlled by a PTP clock recovery servo running on an external processor to synthesize PTP clocks. The DPLLs can be configured with a range of selectable filtering bandwidths. Bandwidths lower than 20mHz can be used to lock the 0.1Hz to 10Hz can be used for G.8262/G.813 applications. Bandwidths above 10Hz can be used in jitter attenuation and rate conversion applications. In Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per ITU-T G.8273.2, two DPLLs can be used; one DPLL is configured as a DCO to synthesize PTP clocks and the other DPLL is configured as an EEC/SEC to generate physical layer clocks. Combo mode provides physical layer frequency support from the EEC/SEC to the PTP clock. For applications per ITU-T G.8263, any DPLL can be configured as a DCO to synthesize packet-based clocks. In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, any of the DPLLs can be configured as an EEC/SEC to output clocks for the T0 reference point and can be used to output clocks for the T4 reference point. The RC38612 generates up to 12 differential output clocks at any frequency from 0.5Hz to 1GHz. The differential outputs can support LVPECL, LVDS, HCSL, and CML. It generates up to 24 single-ended clocks with frequencies from 0.5Hz to 250MHz. LVCMOS output Clocks generated by the DPLLs have jitter below 150fs RMS (12kHz to 20MHz) and therefore are suitable for serial 100GBASE-R, 40GBASE-R, and lower rate interfaces. All control and status registers are accessed through an I 2C / SPI slave microprocessor interface. The SPI interface supports a high data rate up to 50MHz). For configuring the DPLLs, the I 2C master interface can automatically load a configuration from an external EEPROM after reset. It also has internal customer-definable One-Time Programmable memory with up to 16 different configurations.

5©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet

6©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet

Figure 2. Pin Assignments for 10 × 10 mm 72-QFN Package[1] software compatibility with other members of the family of devices. Table 1. Pin Descriptions[a] connected to the OSCI pin, this pin should be left unconnected. mode parallel-resonant crystal (see Table 36 and Table 37).

3 VDDA_PDCP_XTAL Power

5 nMR Input Pull-up Master Reset input (see Device Initial Configuration ).

7 XO_DPLL Input Single-ended crystal oscillator input for System Digital PLL (see Crystal

Oscillator Input (XO_DPLL) ).

8 CLK0 Input Pull-down Positive input for differential input Clock 0 or single-ended input for Clock 0

10 CLK1 Input Pull-down Positive input for differential input Clock 1 or single-ended input for Clock 1

12 CLK2 Input Pull-down Positive input for differential input Clock 2 or single-ended input for Clock 2

14 CLK3 Input Pull-down Positive input for differential input Clock 3 or single-ended input for Clock 3

16 VDD_DIG Power Power Supply for digital logic. 1.2V or 1.8V supported. 17 CLK4 Input Pull-down Positive input for differential input Clock 4 or single-ended input for Clock 4. 18 nCLK4 Input Pull-up Negative input for differential input Clock 4 or single-ended input for Clock 12.

19 SCLK I/O Pull-up

Serial port clock input. Used in both SPI and I 2C modes as the clock. Operation (see I2C Master ). External pull-up recommended in I 2C mode.

20 SDIO I/O Pull-up

3-wire SPI modes. Used as Serial Data Output pin in 4-wire SPI mode. Operation (see I2C Master ). External pull-up recommended in I 2C mode. an Address Bit 1 select input in I 2C mode. Unused in 3-wire SPI mode. Address Bit 0 select input in I 2C mode.

24 VDDA_LC_BG Power Analog power supply voltage for System Analog PLL’s LC Resonator and

Table 1. Pin Descriptions[a] (Cont.)

26 GPIO[3] I/O Pull-up[c] General Purpose Input / Output 3 (see General Purpose Input/Outputs

28 Q11 Output Q11 clock positive output (see FOD Multiplexing and Output Stages ). Multiplexing and Output Stages . powers FOD_2, FOD_3, and FOD_7. 1.8V supply required. Multiplexing and Output Stages . 32 Q7 Output Q7 clock positive output (see FOD Multiplexing and Output Stages ). 33 nQ7 Output Q7 clock negative output (see FOD Multiplexing and Output Stages ).

34 GPIO[9] I/O Pull-up[c] General Purpose Input / Output 9 (see General Purpose Input/Outputs

35 nQ6 Output Q6 clock negative output (see FOD Multiplexing and Output Stages ). 36 Q6 Output Q6 clock positive output (see FOD Multiplexing and Output Stages ). Multiplexing and Output Stages . Multiplexing and Output Stages . 39 Q5 Output Q5 clock positive output (see FOD Multiplexing and Output Stages ). 40 nQ5 Output Q5 clock negative output (see FOD Multiplexing and Output Stages ). Multiplexing and Output Stages . 42 Q4 Output Q4 clock positive output (see FOD Multiplexing and Output Stages ). 43 nQ4 Output Q4 clock negative output (see FOD Multiplexing and Output Stages ). Multiplexing and Output Stages . 45 Q10 Output Q10 clock positive output (see FOD Multiplexing and Output Stages ). 46 nQ10 Output Q10 clock negative output (see FOD Multiplexing and Output Stages ).

47 GPIO[2] I/O Pull-up[c] General Purpose Input / Output 2 (see General Purpose Input/Outputs

48 VDD_GPIO_FOD Power Combined Power Supply input for all the digital pins, including GPIO pins and

serial ports pins as well as FOD_5 and FOD_6. Only 1.8V supported.

49 GPIO[1] I/O Pull-up[c] General Purpose Input / Output 1 (see General Purpose Input/Outputs

50 nQ9 Output Q9 clock negative output (see FOD Multiplexing and Output Stages ). 51 Q9 Output Q9 clock positive output (see FOD Multiplexing and Output Stages ). Multiplexing and Output Stages .

53 nQ3 Output Q3 clock negative output (see FOD Multiplexing and Output Stages ). 54 Q3 Output Q3 clock positive output (see FOD Multiplexing and Output Stages ). Multiplexing and Output Stages .

56 GPIO[5] I/O Pull-up[c] General Purpose Input / Output 5 (see General Purpose Input/Outputs

57 nQ2 Output Q2 clock negative output (see FOD Multiplexing and Output Stages ). 58 Q2 Output Q2 clock positive output (see FOD Multiplexing and Output Stages ). Multiplexing and Output Stages . Multiplexing and Output Stages . 61 Q1 Output Q1 clock positive output (see FOD Multiplexing and Output Stages ). 62 nQ1 Output Q1 clock negative output (see FOD Multiplexing and Output Stages ).

63 GPIO[4] I/O Pull-up[c] General Purpose Input / Output 4 (see General Purpose Input/Outputs

64 nQ0 Output Q0 clock negative output (see FOD Multiplexing and Output Stages ).

65 Q0 Output Q0 clock positive output (see FOD Multiplexing and Output Stages )

Multiplexing and Output Stages . powers FOD_0 and FOD_1. 1.8V supply required. Multiplexing and Output Stages . 69 Q8 Output Q8 clock positive output (see FOD Multiplexing and Output Stages ). 70 nQ8 Output Q8 clock negative output (see FOD Multiplexing and Output Stages ).

71 GPIO[0] I/O Pull-up[c] General Purpose Input / Output 0 (see General Purpose Input/Outputs

72 CREG_XTAL Power Filter capacitor for voltage regulator for oscillator circuit associated with OSCI /

OSCO pins. Requires a 10 F filter capacitor to ground. ePAD VSS Power Device ePAD must be connected to Ground. [a] Pull-up and Pull-down refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. is required to configure the device for either 2.5V or 3.3V operation. For more information, see the 8A3xxxx Family Programming Guide . [c] GPIO pins may be configured via EEPROM and/or OTP with a pull-up or a pull-down. Pull-up is the default configuration.

Table 2. Pin Characteristics [b] Output impedance values for the Qx / nQx outputs are provided in Table 35.

locations are kept consistent to enhance software compatibility and portability between members of the family. functions that are available in the RC38612 only. Figure 3. Single PLL Channel of the document that describe specific functions or details that would overly burden this document. Table 3 shows related documents. Table 3. Related Documentation to power filtering and terminations. family of devices. Please ensure to use the version indicated here for this product. determine differences between update revisions, see Release Note documents. to be loaded from an external EEPROM or over the serial port at each device reset.

which in turn is the source for all internal clocks. For more information, see Table 36 and Crystal Recommendation . Alternatively, the crystal input can be overdriven by a crystal oscillator. For more information, see Overdriving the XTAL Interface . logic results in excellent phase noise performance and a substantial amount of flexibility in frequency and phase for the RC38612. tuning range and also does not result in FOD divider ratios where the divide-ratio fraction is very close to 1, 0, or 1/2. Figure 4. System Analog PLL Channel can be re-configured manually over the serial port at any time. and/or used to drive a GPIO status signal as described in GPIO Modes .

input types to the RC38612, see Table 4 and Applications Information . NMOS so the input buffer will work best with the incoming signal’s voltage swing. 150MHz, the internal divider can be bypassed. The RC38612 has the option to lock to the rising or falling edge of the input clock signal by selecting the inverted input path to the divider. Table 4. Input Stage Setting [a] Single-ended inputs with a voltage swing of 100mV to 1000mV. needed between the AC-coupling capacitor and the device. AC-coupling capacitor must be placed close to the device.

mode can only be used with the GPIOs and input stages shown in Table 5. NMOS mode does not have any effect for GPIO inputs. The RC38612 has the option to lock to the rising or falling edge of the input clock signal for either path individually. Figure 7. Input Stage Configured as Differential Plus Single Single-Ended In addition to the above, there are a number of other configuration bits that can be used for the input stage. ▪ Unused inputs can be disabled. This allows a small amount of power saving and eliminates a source of on-die noise. Operation and Sync Pulse Operation ). Table 5. Input Stages Using GPIOs as Reference Clock Inputs

configured to allow it to be considered qualified in spite of the alarm. For information on how these internal alarms can be signaled and monitored by outside resources, see Alarm Output Operation . operation. In normal operation, the user can specify whether the alarm condition should be tight to the expected clock period or loose. 500kHz, both loose and tight specifications check for the clock edge being outside ±20nsec of the expected position to declare an alarm. For clocks less than or equal to 500kHz, loose threshold is set at ±25% of the nominal edge position and tight is set to ±1%. equivalent to a normal clock monitor. alarm) output via GPIO if so configured. Table 6. Gapped Clock LOS Settings

00 Gapped Clock Monitoring

available much more quickly. a GPIO and/or be used as one input to an Alert (aggregated alarm) output via GPIO if so configured. There is a timer associated with the activity qualification and disqualification of each input reference. allowed to affect the disqualification decision or not. The disqualification timer can be selected according to Table 8. the full duration selected, then the input is qualified for use again. Qualification timer settings are shown in Table 9. Table 7. Activity Limit Table 8. Disqualification Timer Table 9. Qualification Timer

ranges are also listed in Table 10. In addition to the Input Clock Selection and Qualification functions mentioned earlier, the following modes are also available. implemented as a pulse rather than a square wave clock. frame input signal can be used with an associated input clock to align a frame output signal and align associated output and frame clock. The frame pulse does not require any specific duty cycle but should have a pulse width of at least 10nsec. Table 10. Frequency Offset Limits

input frame pulse used by the same DPLL. The RC38612 allows several different pulse widths to be selected (see Table 15). An example of the frame pulse operation is provided in Figure 8. Figure 8. Frame Pulse Operation is locked to CLKx, and Qy is the output frame pulse output of DPLLn. alignment edge rather than an edge of the associated clock. require any specific duty cycle but should have a pulse width of at least 10nsec. of the sync input frequencies. the same DPLL. The falling edge of the sync input signal can be used by setting the frame pulse configuration register.

Figure 11. DPLL Automatic State Machine

1. Reset, the device enters Free-Run State.
2. Once an input clock is qualified and it is selected: enter the LockAcq State.
3. If the DPLL selected input clock is disqualified AND no qualified input clock is available: go back to Free-Run State.
4. DPLL switches to another qualified clock: remain in LockAcq State.
5. The DPLL locks to the selected input clock: enter Locked State.
6. The DPLL selected input clock is disqualified AND No qualified input clock is available: enter Holdover State.
7. A qualified input clock is now available: enter LockRec State.
8. If the DPLL selected input clock is disqualified AND no qualified input clock is available: go back to Holdover State.
9. The DPLL switches to another qualified clock: enter LockRec State.
10. The DPLL locks to the selected input clock: go to Locked State.
11. The DPLL switches to another qualified clock: remain in LockRec State

26©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Combo mode can be used with Free-Run mode. In this case, the input clock of the combo master affects the combo slave’s free-Run frequency. For more information, see Combo Mode . Locked Mode In Locked mode, the DPLL is synchronized to an input clock. The frequency and phase of the output clock track the DPLL selected input clock. The bandwidth (BW) and damping factor are programmable and are used by the DPLL when locked to an input reference. Table 11 includes some common BW settings and their associated applications. Table 11. DPLL Bandwidth 0.09 m 0.271 m 0.905 m stratum 3E, BW < 1mHz 2.90 m G.812 Type I, BW < 3mHz 4.34 m 8.69 m 17.4 m 34.7 m 92.6 m GR-253 stratum 3, SMC, and G.8262 EEC-option 2 278 m 556 m 1.11 G.8262 EEC-option 1 1 ≤ BW ≤ 10, GR-1244 stratum 3 BW < 3Hz 2.22 G.8262 EEC-option 1 1 ≤ BW ≤ 10, GR-1244 stratum 3 BW < 3Hz 4.45 G.8262 EEC-option 1 1 ≤ BW ≤ 10 8.89 G.8262 EEC-option 1 1 ≤ BW ≤ 10 17.8 35.6 71.2 94.4 142 285 G.8251 (OTN) 333 571 11.4 k 12.1 k Jitter attenuators and Clock generators

If all the input clocks for a particular DPLL become invalid, then the DPLL will enter holdover state. (simple holdover), or a previously stored post-filtered frequency offset (advanced holdover). inside the DPLL. The rate at which the holdover registers are updated is programmable between 0s and 63s in steps of 1s. there are valid references available for the DPLL to lock to. holdover value register bits under user control. selection process for each DPLL. input clock, and the input clock configuration. inputs as having the same priority, then an additional table allows several outputs to be placed in a group of equal priority. Table 12. DPLL Reference Mode

0000 Automatic input clock selection

0001 Manual input clock selection

0010 GPIO

0011 Slave

0100 GPIO_Slave

28©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Manual Input Clock Selection via Register or GPIO If manual input clock selection is chosen then the DPLL will lock to the input clock indicated by register bits or by selected GPIO pins. The results of input reference monitoring do not affect the clock selection in manual selection mode. If the DPLL is locked to an input clock that becomes invalid, then the DPLL will go into holdover mode even in the case where there are other input clocks that are valid. Slave or GPIO Slave Selection This mode of clock selection is used when the RC38612 is acting as an inactive, redundant clock source to another timing device. The other device is the master and this device is the slave. When Slave mode is selected via registers, a specific input (from the master timing device) is also indicated. That input and only that input is used in this mode. GPIO Slave mode involves the same configuration settings as if the part were a master, but a GPIO input is used to tell this device that it is now the slave and to switch to and monitor the designated input only. DPLL Switchover Management Revertive and Non-Revertive Switching All DPLLs support revertive and non-revertive switching, with the default being non-revertive. During the reference selection process, a DPLL selects the valid reference with the highest priority then the DPLL locks to that input clock. In the case of non-revertive switching, the DPLL only switches to another, higher priority reference if the current reference becomes invalid. Non-revertive switching minimizes the amount of reference switches and therefore is the recommended mode. If revertive switching is enabled and a higher priority clock becomes valid, then the DPLL will switch to that higher priority input clock unless that clock is designated as part of the same group (i.e., should be considered of equal priority). Hitless Reference Switching All RC38612 DPLLs support Hitless Reference Switching (HS). HS is intended to minimize the phase changes on DPLL output clocks when switching between input references that are not phase aligned, and when exiting the holdover state and locking to an input reference. HS is enabled or disabled through register settings. If enabled for a DPLL, HS is triggered if either of the following conditions occurs: ▪ DPLL is locked to an input reference and switches to a different input reference ▪ DPLL exits the Holdover state and locks to an input reference When a DPLL executes a hitless reference switch, it enters a temporary Holdover state (without asserting a holdover alarm), it then measures the initial phase offset between the selected input reference and the DPLL feedback clock. The DPLL uses the measured initial phase offset as the zero point for its phase detector so that it does not align its output with the selected input reference, thereby minimizing the resulting phase transient. The DPLL will track its selected input reference and will maintain the initial phase offset. Similarly, when a DPLL exits the Holdover state and locks to an input reference it first measures the initial phase offset between the selected input reference and the DPLL feedback clock. The DPLL uses the initial phase offset as the zero point for its phase detector so that it does not align its output with the selected input reference, thereby minimizing the resulting phase transient. The DPLL will track its selected input reference and will maintain the initial phase offset. There are other cases where hitless reference switching can be used in synchronization applications with physical and/or packet clocks. For information on such applications, please contact Renesas. Two types of hitless reference switching are supported: ▪ HS Type 1 - Compliant with ITU-T reference switching requirements. The output phase change due to reference switching is influenced by the nominal frequency of the newly selected reference, see Table 38. ▪ HS Type 2 - Compliant with ITU-T reference switching requirements. The output phase change due to reference switching is not influenced by the nominal frequency of the newly selected reference, see Table 38.

hitless reference switching event. output clocks will experience a transient as the DPLL pulls-in to the input reference. 1ns/s, including the values needed to meet Telecom standards as displayed in Table 13. frequency range of the input when locking. to the frequency/phase snaps. Table 13. Some Key DPLL Phase-Slope Limits Supported

versus the speed of locking. Figure 12. Steerable Fractional Divider Block 13.9GHz and the FOD output (f FOD) is between 500MHz and 1GHz, there is a limited range of valid FOD divide ratios (from 13.4 to 27.8). The Fractional Divider involves two unsigned integer values, representing the integer (INT) and fraction (FRAC) portion of the divide ratio. The fraction portion is an integer representing the 43-bit numerator of a fraction, where the denominator of that fraction is fixed at 2 43. not, the magnitude of the inaccuracy. For more information, please contact Renesas. The equation for the FOD output frequency is given below. recommended that APLL frequency and FOD divider settings be coordinated to avoid such fractions.

larger frequency change for a shorter period of time, whereas a Slow setting will apply a smaller frequency change for a longer period. adjustment be performed via the Digital Phase Locked Loop (DPLL) logic. The RC38612 has multiple output stages that are associated with the FODs and output pins as shown in the following table. The single output stages are shown in Figure 13 and the dual output stages are shown in Figure 14. Table 14. FOD to Output Stage to Output Pin Mappings

pulses or sync pulses, duty cycle adjustment options remain accessible in all modes of operation. integer output divider value. Several examples are shown in Table 15. ▪ Coarse phase adjust lengthens or shortens the high and/or low pulses of the output clock in units of T FOD. ▪ The coarse phase adjust will not shorten the output clock period to anything less than 2xT FOD high + 2xT FOD low.

• This means coarse adjust cannot be used if the integer divider ratio is 1, 2, 3, or 4. ▪ Coarse phase adjust can lengthen or shorten (subject to the above rule) the output clock period by up to 2 32xTFOD high + 232xTFODlow.
• Such a large change in a single clock period may have serious effects on devices receiving the output clock, so the user is cautioned to consider that before applying a large adjust at one time. Multiple smaller adjustments can be performed by the user over a period of time to avoid this.

Table 15. Output Duty Cycle Examples

500 MHz

[b] For precision of duty cycle achieved, see Table 38. [c] This represents the high period of a pulse.

655.36 MHz

clock, so UI = Unit Interval of the clock output associated with the frame pulse. In this example, the associated clock is the 8.192MHz clock.

user and apply it in a single clock period to the limits listed in the preceding rules.

• For clock signals that are using 50% / 50% duty cycle, adjustments will be applied approximately equally to the high and low portions of the clock.
• For clock signals using other duty cycle selections, adjustments will only be applied to the low portion of the clock. ▪ The user can apply as many of these updates as desired, so the range of adjustment is unlimited. Output Buffer The output buffer structure will generate either one differential or two single-ended output signals as programmed by the user. A single output stage will have one output buffer structure and a dual stage one will have two output buffers. Each output buffer has a separate VDDO_Qx pin that will affect its output voltage swing as indicated below and in Table 32. Output Buffer in Differential Mode When used as a differential output buffer, the user can control the output voltage swing (V OVS) and common mode voltage (V CMR) of the buffer. Which V OVS and VSWING settings may be used with a particular V DDO_Qx voltage are described in the following table. Note that VDDO_Qx options of 1.5V or 1.2V cannot be used in differential mode. The nominal voltage swing options are 410mV, 600mV, 750mV, and different conditions, see Table 32. The user can use this programmability to drive LVDS, 2.5V LVPECL, and 3.3V LVPECL receivers without AC-coupling. Most other desired receivers can be addressed with this programmable output, but many will require AC-coupling or additional terminations. For termination recommendations for some common receiver types, see the appropriate section of the Applications Information or contact Renesas using the contact information on the last page of this datasheet.

Table 16. Configurable Output Mode Options [a] Voltage swing values are approximate values. For actual swing values, see Table 32, Table 33, and Table 34.

35©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Output Buffer in Single-Ended Mode When used as a single-ended output buffer, two copies of the same output clock are created with LVCMOS output levels. Each clock will have the same frequency, phase, voltage, and current characteristics. The only exception to this is that the user can program the clock from the nQx output pad to be inverted in phase relative to the one coming from the Qx output pin. The non-inverted setting may result in greater noise on these outputs and increased coupling to other output clocks in the device, so it should be used with caution. from the V DDO_Qx voltage of 1.8V. For each output voltage, there are four impedance options that can be selected from. For actual voltage and impedance values under different conditions, see Table 35. General Purpose Input/Outputs (GPIOs) The GPIO signals are intended to provide a user with a flexible method to manage the control and status of the part via pins without providing dedicated pins for each possible function that may be wasted in a lot of applications. The GPIOs are fully configurable so that any GPIO can perform any function on any target logic block. GPIO Modes Each GPIO pin can be individually configured to operate in one of the following modes. Note that these modes are effective only once the RC38612 has completed its reset sequence. During the reset sequence one or more of these pins can have different functions as outlined in Use of GPIO Pins at Reset : ▪ General Purpose Input – In this mode of operation, the GPIO pin will act as an input whose logic level will be monitored and reflected in an internal register that may be read over the serial port. This is the default mode if no other option is programmed in OTP or EEPROM. ▪ General Purpose Output – In this mode of operation, the GPIO pin will act as an output that is driven to the logic level specified in an internal register. That register can be written over the serial port. ▪ Alarm output – In this mode of operation, the GPIO pin will act as a single-purpose alarm or Alert (aggregated alarm) output. For information on when an alarm output will be asserted or released and alarm sources, see Alarm Output Operation . Note that each GPIO can be independently configured. If multiple GPIOs are configured the same way, they will all have the same output values.

• Loss-of-Signal status – In this mode of operation, the GPIO pin will act as an active-high Loss-of-Signal output. There is an option to invert this output polarity via register programming. When the GPIO output is asserted, that indicates the selected input reference monitor is indicating an alarm condition. The related reference monitor and the associated GPIO pin are configured via registers. Configuration of the reference monitor will determine what constitutes an alarm. For more information on reference monitor configuration, see Reference Monitoring . Note that the GPIO output reflects the actual state of the alarm signal from the selected reference monitor. This is not a latched or “sticky” signal. This is different than the other alarm sources below.
• Loss-of-Lock status – In this mode of operation, the GPIO pin will act as a Loss-of-Lock output. The related PLL channel and associated GPIO pin are configured via registers. For more information on alarm conditions, see Digital Phase Locked Loop (DPLL) and System Analog PLL (APLL) . The GPIO can be programmed to show the active Loss-of-Lock status, in which case a high state on the pin will indicate that the associated DPLL or APLL is not currently locked. Alternatively, the GPIO can be programmed to flag any changes in the lock status in a “sticky” bit mode. In this mode of operation, a high state will indicate that the lock status of the associated DPLL or APLL has changed. Either the PLL has entered or left the locked state. The GPIO can be programmed to invert this polarity so that a low state indicates a status change. In either case, since this is a “sticky” status, it must be cleared by register access to the “stick” clear register to remove the alarm signal.
• Holdover status – In this mode of operation, the GPIO pin will act as a Holdover status. The related PLL channel and associated GPIO pin are configured via registers. For more information on alarm conditions, see Digital Phase Locked Loop (DPLL) . The GPIO can be programmed to show the active Holdover status, in which case a high state on the pin will indicate that the associated DPLL is currently in holdover state. Alternatively, the GPIO can be programmed to flag any changes in the holdover status in a “sticky” bit mode. In this mode of operation, a high state will indicate that the holdover status of the associated DPLL has changed. Either the PLL has entered or left the holdover state. The GPIO can be programmed to invert this polarity so that a low state indicates a status change. In either case, since this is a “sticky” status, it must be cleared by register access to the “stick” clear register to remove the alarm signal.

36©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet

• Alert (aggregated alarm) status – In this mode of operation, the GPIO will act as the logical OR of all alarm indicators that are enabled to drive this output. Only “sticky” bits are available to drive the GPIO in this mode. This output will be asserted if any of the “sticky” bits are asserted and enabled to cause the Alert (aggregated alarm). To clear this output, all contributing “sticky” bits must be individually cleared. This output will be active-high to indicate one or more alarms are asserted. There is an option to invert this output polarity via register programming. ▪ Output Disable control – In this mode of operation, the GPIO pin will act as a control input. When the GPIO input is high, the selected output clock(s) will be disabled, then placed in high-impedance state. When the GPIO pin is low, the selected output clock(s) will be enabled and drive their outputs as configured. For information on output frequency and output levels, see System Analog PLL (APLL) and FOD Multiplexing and Output Stages . Selection of which output(s) are controlled by which GPIO(s) is configured via registers over the serial port or by OTP or EEPROM at reset. Each GPIO can be configured to control any or all outputs (or none). So all combinations can be set up from a single GPIO controlling all outputs, to all outputs responding to individual GPIO signals and any grouping in between. ▪ Single-ended Input Clock – In this mode of operation a single-ended input clock can be applied to certain GPIOs that map to specific input stages (see Input Stage for details, including which GPIOs map to which input references). This can be used if extra single-ended inputs are needed due to all input reference clock pins being taken-up by differential input references. This mode cannot be used if an input stage already has two single-ended input references from the CLKx/nCLKx input pins. ▪ Manual Clock Selection control – In this mode of operation, the GPIO pin acts as an input that will manually select between one of two inputs for a specific DPLL channel. The specific input references and the PLL channel must be pre-configured via registers. Assertion of the GPIO will select the higher priority input and de-assertion will select the lower priority input. For information on how to configure the input references for a PLL channel, see DPLL Input Clock Qualification and Selection . ▪ DCO Increment – In this mode of operation, the GPIO pin will act as an increment command input pin for a specific channel configured as a DCO. The rising edge of the GPIO pin will cause an increment function on the indicated DCO. The amount of the increment and the related DCO to increment must be previously configured via registers. For more information, see Increment / Decrement Registers and Pins . ▪ DCO Decrement – In this mode of operation, the GPIO pin will act as an decrement command input pin for a specific channel configured as a DCO. The rising edge of the GPIO pin will cause an decrement function on the indicated DCO. The amount of the decrement and the related DCO to decrement must be previously configured via registers. For more information, see Increment / Decrement Registers and Pins . ▪ Clock Disqualification Input – In this mode of operation, the GPIO pin will act as an active-high disqualification input for a preconfigured input and DPLL. This is intended to be connected to the LOS output of a PHY or other device. For more information, see DPLL Input Clock Qualification and Selection . GPIO Pin Configuration The GPIO pins are all powered off a single voltage supply that only supports 1.8V operation. An internal register must be set to indicate 1.8V. This setting is a global one for all GPIOs. In addition, each GPIO can be enabled or disabled under register control. If enabled and configured in an operating mode that makes it an output, the user can choose if the GPIO output will function as an open-drain output or a CMOS output. The open-drain output drives low but is pulled high by a pull-up resistor. There is a very weak pull-up internal to the RC38612, but an external pull-up is strongly recommended. In CMOS mode, the output voltage will be driven actively both high and low as needed. Register control can also enable a pull-up (default) or pull-down. Alarm Output Operation There are many internal status and alarm conditions within the RC38612 that can be monitored over the serial port by polling registers. Several of these can be directed to GPIO pins as indicated in General Purpose Input/Outputs (GPIOs) . In addition, one of the GPIOs can be designated as an Alert (aggregated alarm) output signal called an Alert output.

indicates the alarm is present. For more information, see GPIO Modes . The GPIO can be programmed to invert the alarm if desired. RC38612 there will be an indication of what caused the alarm in the first place. Note that there can be multiple sticky bits asserted. blocks can generate the indicated alarms. the bits that contributed to the alarm output being asserted. both the individual alarm “sticky” status and the logic block “sticky” status must be cleared to fully remove the source of the alarm output. will be able to drive it. The GPIO can be programmed to invert the Alert (aggregated alarm) if desired. Table 17. Alarm Indications of the appropriate live alarm indication. [b] Only the “live” status will negate by itself. The “sticky” needs to be explicitly cleared by the user. PLL is currently in a specific state. The user can read the current state of the Digital PLL state machine from status registers over the serial port. [d] This includes the System DPLL, as well as all Digital PLLs.

it may also bring-up Digital PLLs, lock to input references including any OCXO/TCXOs, and generate output clocks. Each of these is discussed individually in the following sections and then integrated into the reset sequence. the reset functions outlined below. Table 18. GPIO Pin Usage at Start-Up

8 Must be high during reset active period Pull-up

See details just below this table. Disables EEPROM accesses during start-up sequence. check for additional start-up information by default. See details just below this table. address bit A2. Has no effect on serial port selected as SPI. See details just below this table.

39©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Any of the available GPIOs can be used as the following: ▪ I2C base address bit A2 – This is for the serial port when selected as I 2C during the start-up sequence using GPIO[9]. If no GPIOs are configured in this mode, bit A2 of the slave serial port base address will be zero. The value of the I 2C base address and the serial port configuration can be overwritten by SCSR configuration data or serial port accesses later in the start-up sequence. If more than one GPIO is programmed with this functionality, only the one with the highest index will be used (e.g., if both GPIO[5] and GPIO[7] are programmed to do this, only GPIO[7] would be used). ▪ EEPROM Access Disable control – A high input value on a GPIO programmed with this function prevents a device from attempting to read device update information or SCSR configuration data from an external I 2C EEPROM. This will speed up device reset time but prevent access to updated information that may be stored in EEPROM. If no GPIOs are configured in this mode then the device will attempt to locate an external EEPROM at the appropriate point in the start-up sequence. If multiple GPIOs are configured to perform this function then any one of them being active will disable EEPROM accesses, so it is recommended that no more than one GPIO be programmed for this function. ▪ Default Configuration Select control – If no GPIOs are selected then GPIO[3:0] will be assumed and the value on those pins at the rising edge of the nMR signal will be used to select which of the SCSR configurations in OTP memory is to be used. Note that since a GPIO is pulled-up by default, unless these pins are pulled or driven low during the reset period, this will select SCSR Configuration 15. If one or more GPIOs are selected for this function, then the value on those pins at the rising edge of nMR will be used to select the SCSR configuration to be loaded. The Device Information block of the OTP can be configured to select any of up to four GPIO pins to be used for this purpose if the default GPIOs are not convenient. The GPIOs chosen do not have to be sequential, but whichever ones are chosen, the one with the lowest index number will be the LSB and so on in order of the index until the GPIO with the highest index is the MSB. No GPIO that appears elsewhere in this table should be used for this purpose. For example, if GPIO[8], GPIO[6], GPIO[5] and GPIO[2] are used, GPIO[8] is the MSB, GPIO[6] is next most significant, GPIO[5] is next and GPIO[2] is the LSB. If less than four GPIO pins are selected, then the selected GPIOs will be used as the least-significant bits of a 4-bit selection value, with the upper bits set to zero. If more than four GPIOs are programmed for this function, then the GPIOs will form a larger bit-length word for selection of internal configuration. Default Values for Registers All registers are defined so that the default state (without any configuration data from OTP or EEPROM being loaded) will cause the device to power-up with none of the outputs enabled and all GPIO signals in General-Purpose Input mode. Users can then program any desired configuration data over the serial port once the reset sequence has completed. One-Time Programmable (OTP) Memory The RC38612 contains a 32kbytes One-Time Programmable (OTP) memory block that is customer definable. The term “one-time programmable” refers to individual blocks within the memory structure. Different blocks can be programmed at different times, but each block can only be programmed once. The data structure within the OTP is designed to facilitate multiple updates and multiple configurations being stored, up to the limit of the physical memory space. After reset of the RC38612, all internal registers are reset to their default values, then OTP contents are loaded into the device’s internal registers. A Device Information block programmed by Renesas at Final Test will always be loaded. This provides information that is specific to the device, including product ID codes and revision information. In addition there are zero or more device configurations stored in the OTP or by Renesas at the factory if a special dash-code part number is requested. Certain GPIO pins are sampled at the rising edge of the external nMR input signal. The state of those pins at that time will be used by the RC38612 to determine which of up to 16 configurations stored in the OTP to load into the device registers. For information on how to select a configuration, see Use of GPIO Pins at Reset . Storage of configuration data in OTP does not require having a value stored for every register in the device. Register default values are defined to ensure that most functions will be disabled or otherwise made as neutral as possible. This allows only features that are being used in any particular configuration (and their associated trigger registers as defined in the 8A3xxxx Family Programming Guide ) to need to be stored in OTP for that configuration. The intent of this is to minimize the size a configuration takes in OTP to allow more configurations to be stored there. For this reason, the exact number of configurations storable in OTP cannot be predetermined. There will be a minimum of two configurations and a maximum of 16 configuration capacity in the OTP.

40©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Part numbers with -000 as the dash code number are considered “unprogrammed” parts, but will come with at least a Device Information block pre-programmed with Renesas-proprietary information, including parameters needed to successfully boot the device to the point where it can read its configuration data. One Device Update block may also be programmed if determined to be appropriate by Renesas. Custom user configurations indicated with non-zero dash code part numbers will in addition have one or more SCSR Configuration sections pre-programmed as indicated in the datasheet addendum for that particular dash code part number. Note that a programmed configuration, Device Information block, or Device Update block may be invalidated via the OTP programming interface, and if sufficient OTP space remains, a new one added to replace it. Note that this does not erase or remove the original data and the space it consumes. It just marks it to be ignored by the device. This allows for a limited ability to update a device in the field either from a device functional update or configuration data perspective. This is a purely software-driven process handled over the serial port. Please contact Renesas for support if this type of in-field upgrade / change is desired. Note that the ability to perform this type of in-field update is highly dependent on the size of the change versus the remaining space in OTP, so it will not be possible in all cases. Configuration Data in OTP Users can program multiple configurations into the internal One-Time Programmable memory. Renesas’ Timing Commander GUI Software can perform this function. Please contact Renesas for sample code if this needs to be performed in another way by the end user. By using the GPIO pins at start-up as outlined in Use of GPIO Pins at Reset , one of those configurations can be chosen for use as the initial values in the device registers after reset. Register values can be changed at any time over the serial port, but any such changes are not stored in OTP and will be lost on reset or power-down. The OTP is organized so that only configuration data that changes from the register default values needs to be stored. This saves OTP space and allows the potential for more configurations to be stored in the OTP. If the indicated configuration in OTP has a checksum error, it will not be loaded and registers will be left at their default values. Use of External I2C EEPROM The RC38612 can search for additional configuration or device updates in an external I 2C EEPROM. As described in the Use of GPIO Pins at Reset , a GPIO can be configured to select whether or not this search will be performed during the reset sequence. T he EEPROM search will not be performed if the serial port is set to SPI mode since the necessary I 2C Master signals are not available in that mode. The remainder of this description assumes the EEPROM search is enabled. The RC38612 will use its I 2C Master Port to attempt to access an external I 2C EEPROM at base address 1010000 (binary) at an I 2C frequency of 1MHz. If there is no response, this will be repeated at base address 1010001 (binary) at 1MHz. This will repeat up to address 1010111 (binary) at 1MHz. If there still are no responses, the search will be repeated at 400kHz and then again at 100kHz. If no response is received after this entire sequence, the device will assume there is no EEPROM available. Any errors in the process will be reported in status registers. Device Updates in External I2C EEPROM As indicated in Reset Sequence , if enabled, the RC38612 will search for Device Update information in an external I 2C EEPROM. It will first identify all valid EEPROMs attached to the I 2C master port as described above. Each valid EEPROM will be checked for a valid Device Update Block header with valid checksum at address offset 0x0000 within the EEPROM. The first such valid block will be used as described in Reset Sequence . Configuration Data in External I2C EEPROM As a final option for device configuration, the initial configuration can be read from an external I 2C EEPROM. Renesas’ Timing Commander GUI Software can generate the necessary EEPROM load information as an Intel HEX file for this purpose. The RC38612 will search each EEPROM identified during the above search sequence for a valid configuration data block (valid header and checksum). The first valid block found will be loaded into internal registers after checksum validation. The search will terminate after the first valid block is found and loaded. This means that only a single valid configuration block can be stored via the EEPROM method. When the device searches for an EEPROM configuration, it will check for a valid block at address offsets 0x0000 and 0xF000 within an EEPROM. If using this configuration method, see the warning in Step 5 – Search for Configuration in External EEPROM .

42©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Based on the serial port protocol selection made via the GPIO pin in Step 1, serial port configuration will be completed as indicated by the GPIO input pin. If SPI mode is selected by the GPIO, the register default values will configure it to use 4-wire SPI mode. Step 3 – Scan for Device Updates in EEPROM If enabled to do so, the RC38612 will check for device functional update information in any available EEPROMs (for information on how EEPROMs are searched for, see Use of External I 2C EEPROM ). If such information is found, it will be loaded, the device functionality updated, and then the part will reinitialize to Step 0. Step 4 – Read Configuration from OTP Using the GPIO values latched in Step 1, the device will search the internal OTP memory for the indicated configuration number. If no such configuration is found or the configuration has an invalid checksum, the device will skip to Step 5. Any errors in this process will be reported. If loading from OTP was successful, which configuration number was loaded will be reported. If the requested configuration is found and is valid, the device will load the registers indicated in the configuration data with the stored data values in the internal register image. Any register not included in the configuration data set will remain at its default value in the register image. Note: Many register modules have explicitly defined trigger registers that when written will cause the other register settings in that module to take effect. Users must ensure that the configuration in OTP will cause a write to all applicable trigger registers, even if that register’s contents would be all zero. Multi-byte register fields also require all bytes of the field to be written to ensuring triggering. For indications of which trigger registers are associated with which other registers, see the 8A3xxxx Family Programming Guide . The contents of several of the registers will be used to guide the remainder of the reset sequence: ▪ If the APLL feedback divider value was programmed in this step, perform APLL calibration in parallel with remaining reset activities. ▪ Re-configure the serial ports to use I 2C or SPI protocols as indicated. For information, see I2C Slave Operation or SPI Operation . Step 5 – Search for Configuration in External EEPROM The RC38612 will check for configuration information in any available EEPROM (for information on how EEPROMs are searched for, see Use of External I 2C EEPROM ). If a valid configuration data block is found, it will be read, its checksum validated and if that passes, loaded into the internal register image similarly to OTP configuration data described in Step 4. If the data found is not of the correct format or the data block fails a checksum comparison, it will be ignored. The search will continue through the EEPROM and on to the next EEPROM address until the complete range has been searched or a valid configuration block has been found and applied to the internal register image. Then the sequence will proceed to Step 6. Note: Since OTP and EEPROM configuration data rarely consists of a full register image, reading of configuration data from OTP and then from one or more configuration blocks stored in EEPROM may result in internal registers being loaded with conflicting settings drawn partially from each of the configuration data sets being loaded. It is strongly recommended that a configuration block placed in EEPROM only be used when no valid configuration is being pointed to in OTP by GPIO signals (or there is no valid configuration in OTP at all). If multiple configurations are to be used then the user must ensure all registers are set to the desired values by the final configuration block to be loaded. Step 6 - Load OTP Hotfix and Execute If the RC38612 OTP memory contains a hotfix, that information will be loaded into RAM and executed at this point. Step 7 – Complete Configuration The RC38612 will complete the reset and initial configuration process at this point and begin normal operations. Completion steps include the following: 1. If configuration information was loaded in Step 4 or Step 5, recalibrate the System APLL and lock it to the reference clock on the OSCI input. 2. Enable serial port operation as configured.

43©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet 3. Apply configuration settings from the internal register image to the actual registers and enable Qx / nQx outputs a nd GPIOs as configured. 4. Begin operation on input reference monitors and PLL state machine alarms/status. 5. Enable alarm operation as configured. Note that there are several scenarios in which the reset sequence will reach this point without retrieving any configuration data and with all registers in the default state. This may be intentional for users who wish to configure only via the serial port or the result of a problem in the loading of a configuration. Users can read appropriate status bits to determine what failures, if any, occurred during the reset sequence. Accessing the Serial Ports After a Reset Sequence After a reset sequence, there is a wait time (t wait) after nMR de-assertion before the device serial ports can be accessed. The required wait time depends on the EEPROM and OTP as follows: ▪ EEPROM load is disabled by OTP programming: t wait = 15ms ▪ EEPROM load is enabled and no EEPROM is present: t wait = 150ms ▪ EEPROM load is enabled and EEPROM is present: t wait is given by the equation below: twait (s) = { { { EEPROM_Payload_Size (bytes) / 256 } * 2342 + 2250 } / I2C_CLK_Rate (Hz) } * 1.15 EEPROM_Payload_Size is the sum of: ▪ Size of configuration in bytes ▪ Size of firmware (if any) in bytes Clock Gating and Logic Power-Down Control The RC38612 can disable the clocks to many logic blocks inside the device. It also can turn off internal power regulators, disabling individual power domains within the part. Because of the potentially complex interactions of the logic blocks within the device, logic within the part will handle the decision-making of what will be powered-off, versus clock-gated, versus fully operational at any time. By default, the device will configure itself with functions in the lowest power-consuming state consistent with powering up the part and reading a user configuration. User configurations, whether stored in internal OTP, external EEPROM, or manually adjusted over the serial port, should make use of register bits to only turn on functions that are needed. Also if a function is no longer needed, register bits should be used to indicate it is no longer required. Internal logic will reduce its power-consumption state in reaction to these indicators to the greatest extent possible. For more information on how to calculate power consumption for a particular configuration, consult Renesas’ Timing Commander software for more precise results for a particular configuration. Serial Port Functions The RC38612 supports one serial port. The signals on the port share the functions of an I 2C Master port used for loading configuration data at reset and a configurable slave I 2C or SPI port that can be used at any time after the reset sequence is complete to monitor and/or configure the device. Note that the I 2C master port can only be used when the slave port is configured in I 2C mode. Since I 2C master operation only occurs immediately after reset, while configuration or other data is being loaded from an external I 2C serial EEPROM, I 2C mode for the serial port can be selected via GPIOs as indicated in Use of GPIO Pins at Reset . The operation of the serial port when in I 2C master operation (during self-configuration only) is described in I2C Master . The SCLK and SDIO pins are used for this purpose. Please refer to the appropriate section below for details on the operation of the master I2C and slave I 2C or SPI ports.

or external EEPROM (for information, see Device Initial Configuration ). function in the selected mode, as shown in Table 19. to be provided during slave serial port accesses. Of that 64KB, only the upper 32KB contains user accessible registers. part of the address offset is provided in each transaction and another part comes from an internal page register in each serial port. Figure 16 shows how page register and offset bytes from each serial transaction interact to address a register within the RC38612. Table 19. Serial Port Pin to Function Mapping

46©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet The Dev Addr shown in the figure represents the base address of the RC38612. This 7-bit value can be set in an internal register that can have a user-defined value loaded at reset from internal OTP memory or an external EEPROM. The default value if those methods are not used is 1011000b. Note that the levels on the A0 and A1 signals can be used to control Bit 0 and Bit 1, respectively, of this address. There is also an option to designate the reset state of a GPIO pin to set the default value of the A2 bit of the I 2C slave port base address (for information, see Use of GPIO Pins at Reset ). In I2C operation these inputs are expected to remain static. They have different functions when the part is in SPI mode. The resulting base address is the I 2C bus address that this device will respond to. When I2C operation is selected for a slave serial port, the selection of 1-byte (1B) or 2-byte (2B) offset addressing must also be configured. These offsets are used in conjunction with the page register for each serial port to access registers internal to the device. Because the I2C protocol already includes a read/write bit with the Dev Addr, all bits of the 1B or 2B offset field can be used to address internal registers. ▪ In 1B mode, the lower 8 bits of the register offset address come from the Offset Addr byte and the upper 8 bits come from the page register. The page register can be accessed at any time using an offset byte value of 0xFC. This 4-byte register must be written in a single-burst write transaction. ▪ In 2B mode, the full 16-bit register address can be obtained from the Offset Addr bytes, so the page register only needs to be set up once after reset via a 4-byte burst access at offset 0xFFFC. Note: I2C burst mode operation is required to ensure data integrity of multi-byte registers. When accessing a multi-byte register, all data bytes must be written or read in a single I 2C burst access. Bursts can be of greater length if desired, but must not extend beyond the end of the register page (Offset Addr 0xFF in 1B mode, no limit in 2B mode). An internal address pointer is incremented automatically as each data byte is written or read. Figure 18 and Table 20 show the detailed timing on the interface. 100kHz, 400kHz, and 1MHz operation are supported. I2C 1-byte (1B) Addressing Examples RC38612 I2C 7-bit I 2C address is 0x5B with LSB = R/W Example write “0x50” to register 0xCBE4: B6* FC 00 CB 10 20 #Set Page Register, *I2C Address is left-shifted one bit. B6 E4 50 #Write data 5B to CB E4 Example read from register 0xC024: B6* FC 00 C0 10 20 #Set Page Register, *I2C Address is left-shifted one bit. B6 24* #Set I2C pointer to 0xC024, *I2C instruction should use “No Stop” B7 <read back data> #Send address with Read bit set. I2C 2-byte (2B) Addressing RC38612 I2C 7-bit I 2C address is 0x5B with LSB = R/W Example write “50” to register 0xCBE4: B6* FF FD 00 10 20 #Set Page Register, *I2C Address is left-shifted one bit. B6 CB E4 50 #Write data to CB E4 Example read from register 0xC024: B6* FF FD 00 10 20 #Set Page Register (*I2C Address is left-shifted one bit.) B6 C0 24* #Set I2C pointer to 0xC024, *I2C instruction should use “No Stop” B7 <read back data> #Send address with Read bit set.

both 3-wire and 4-wire SPI mode. 4-wire SPI mode is the default. The R/W bit is high for Read Cycles and low for Write Cycles. Figure 20. SPI Sequencing

• In 1B operation, the 16-bit register address is formed by using the 7 bits of address supplied in the SPI access and taking the upper 9 bits from the page register. The page register is accessed using an Offset Address of 0x7C with a 4-byte burst access.
• In 2B operation, the 16-bit register address is formed by using the 15 bits of address supplied in the SPI access and taking the upper 1-bit from the page register. Note that this bit will always be 1 for register accesses, so the page register only needs to be set once in 2B operation. The page register can be accessed using a 3-byte burst access Offset Address of 0x7FFD. It should be accessed in a single burst write transaction to set it. ▪ Data sampling on falling or rising edge of SCLK ▪ Output (read) data positioning relative to active SCLK edge ▪ 4-wire (SCLK, CS, SDIO, SDI) or 3-wire (SCLK, CS, SDIO) operation ▪ In 3-wire mode, SDIO is a bi-directional data pin. ▪ Output signal protocol compatibility / drive strength and termination voltage 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 CS SCL K SDI (4-wire) SDI O (4-wire) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14R/ W CS SCL K SDI (4-wire) SDI O (4-wire) D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Hi-Z SPI Read Sequence* SPI Write Sequence* XX (SDI unus ed while data being read) A14-A7 are omitted in 7b SPI Add ressing Mode Data byte from Address provided Data byte from Addres s + 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A14-A7 are omitted in 7b SPI Add ressing Mode Data byte to Address pr ovided Data byte to Address + 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14R/ W SDI O (3-wire) D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13R/ W SDIO (3-wire) D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDI O Driven by Master SDIO Driven by Slave SDI O Driven by Master * See the timing diagrams for exact timing relationships.

49©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Note: SPI burst mode operation is required to ensure data integrity of multi-byte registers. When accessing a multi-byte register, all data bytes must be written or read in a single SPI burst access. Bursts can be of greater length if desired, but must not extend beyond the end of the register page. An internal address pointer is incremented automatically as each data byte is written or read. SPI 1-byte (1B) Addressing Example Example write to “50” to register 0xCBE4 7C 80 CB 10 20 #Set Page register 64* 50 #*MSB is 0 for write transactions Example read from 0xC024: 7C 00 C0 10 20 #Set Page register A4* 00 #*MSB is set, so this is a read command SPI 2-byte (2B) Addressing Example Example write to “50” to register 0xCBE4 7F FD 80 10 20 #Set Page register 4B E4* 50 #*MSB is 0 for write transactions Example read from 0xC024: 7F FD 80 10 20 #Set Page register C0* 24 00 #*MSB is set, so this is a read command SPI timing is shown in Figure 21 and Table 21.

Figure 21. SPI Timing Diagram Table 21. SPI Timing

HIGHZ, and CLAMP instructions. device resumes operational mode in a clean state. [a] Tested as low as 50kHz, but there’s no limit in the design to how low this can go. edge rates and longer delays. This is highly dependent on PCB loading. Table 22. JTAG Signal Mapping Table 21. SPI Timing (Cont.)

and/or frequency updates will be calculated using external methods and written into the RC38612 over the serial port. with devices receiving this clock. The output will remain at this frequency until a new FCW is written. If supported by the device, Combo Mode can be used to add additional offsets to the write frequency offset. Figure 28. External DCO Control via Frequency Control Word of the nominal DCO frequency. A positive value will increase the output frequency and a negative one will decrease the output frequency. be written into the register.

1 FFO

cumulative FCW value. The cumulative FCW value functions as described in the previous section. serial port and cause an increment or decrement frequency offset to be applied to one or more DCOs with a single register access. Subsequent accesses to this register can apply additional frequency offsets to any or all DCOs. DCO. For information on how to configure the GPIOs, see General Purpose Input/Outputs (GPIOs) . In this mode, the DPLL loop bandwidth and the phase slope limiting are programmable and will affect the output phase as it is adjusted. should not cause any issues, if properly configured, with devices receiving this clock. can be adjusted by external software. Figure 29. External DCO Control via Phase Control Word

has a granularity of 1 millisecond and a full range of up to 65.535 seconds. oscilloscope. A negative value will slow the output frequency. input to allow individual offsets to be specified per-input. Frequency Detector to the Digital Loop Filter when the DPLL is operating in closed loop. Figure 30. Phase Control in Closed Loop Operation any missing pulses or glitches in the output clocks from either channel since all frequency changes are limited by at least one loop filter. based on SSM clock quality level.

Figure 32. Satellite Channel and Source Channel For more information about configuring satellite channels, please see the Renesas application note titled Auto-Alignment of Outputs .

8A3xxxx Family Programming Guide. synchronizes the output clocks and a 1PPS sync pulse signal generated from the same DPLL . sub-ns bitfield will remain at zero. In order to avoid truncation errors for the sub-nanoseconds, a flexible modulus accumulator is used, as displayed below. Figure 33. ToD Accumulator preprogrammed value and to latch the ToD accumulator to sample the Time of Day. [1] DPLL 0 and 1 only; DPLL 2 and 3 have maximum of 750MHz.

61©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet ▪ Internal Global Timer, based on System PLL ▪ Read/write access to a pre-configured CSR ▪ Interrupt source, directed to a GPIO The ToD accumulator value can also be updated and distributed by the RC38612 using PWM (see Pulse-Width Modulation Encoders, Decoders, and FIFO ). Read/Write to ToD or ToD-based Registers Unless otherwise specified, any referenced bits or registers throughout this section reside in the TOD_WRITE_X section of the register map, where X ranges from 0 to 3. TOD_WRITE_0 is CC00 (Offset 000h to 00Fh). TOD_READ_PRIMARY_0 base address CC40h (offset 000h to 000Eh). For more information about other TOD registers, see the 8A3xxxx Family Programming Guide. For general 1588 applications, the ToD accumulator must be synchronized to the overall network Time of Day. This can be done by programming the ToD accumulator with the network Time of Day using a simple write to the 11B ToD register. The update of the ToD accumulator with the 11B ToD register value is triggered on the final write to the MSB of the ToD second register. The ToD accumulator will be updated with the ToD value after a maximum of X clock cycles of the ToD accumulator clock . For better precision on programming the ToD accumulator, the Active Edge Sampling and Loading and Other Asynchronous Events mechanisms should be used. Similarly, the ToD accumulator can be read at any time by the microprocessor. The latch of the ToD accumulator value is triggered on an initial read to the previous word before the ToD register. The full 11B ToD value can be subsequently read after this access, or a burst access starting at the previous word can be performed. The ToD register is updated with the ToD accumulator value after a maximum of X clock cycles of the ToD accumulator clock. For better precision on latching the ToD accumulator, the Active Edge Sampling and Loading and Other Asynchronous Events mechanisms should be used. The RC38612 also supports latching of the ToD accumulator on read/write access to specific programmed register. The desired register to trigger or latch the ToD accumulator is programmed via register. The latched ToD value is contained in the Register ToD FIFO. Active Edge Sampling and Loading The RC38612 provides precise triggering and latching of the ToD accumulator using an active edge of an internal synchronous clock The following active-edge sources can latch a Time of Day value from the ToD accumulator on a single edge or on continuous active edges. ▪ External Sync Pulse (1PPS, PPES, etc.)

• 11B ToD value will be latched in the FIFO on next active edge ▪ PWM
• 11B ToD will be latched on internal 1PPS. The 11B ToD value will be sent out on the corresponding PWM_PPS frame (see Pulse-Width Modulation Encoders, Decoders, and FIFO )
• Alternately, 11B ToD may be latched on a PWM_PPS “reply” request and sent out on a PWM_PPS frame (see Ranging Operation ) The following active edge sources can trigger the programming of the ToD accumulator on a single edge or on continuous active edges. ▪ External Sync Pulse (1PPS, PPES, etc.)
• Value in 11B ToD register will be programmed into ToD accumulator on next active edge ▪ PWM
• 11B ToD value from the PWM_PPS frame will be programmed into ToD accumulator on the next PWM_PPS Frame reception (see Pulse-Width Modulation Encoders, Decoders, and FIFO ) When using GPIOs, there will be an inaccuracy due to internal delays. For better precision on latching the ToD accumulator, use an unused reference clock/pulse input.

source directed to a GPIO or the global system timer. mentioned, due to internal delays to the GPIO block, the precision of the interrupt active edge sampling will have an error. clock (2.5ns ± the accuracy of the oscillator). information on ToD registers, see Time-of-Day (ToD) Operation . port. For information on ToD registers, see Time-of-Day (ToD) Operation . about other PWM_ENCODER and PWM_DECODER registers, see the 8A3xxxx Family Programming Guide. (75% modulation). This is displayed below, along with a sample of an encoded stream. Figure 34. PWM Coded Symbols decoded information can then be sent to any DPLL or to the System DPLL.

been phase synchronized with one another. Figure 42. SYSREF Usage Example divider in the lower path will be set to a multiple (128 in this example) of the integer divider ratio in the upper path (8 in this example). Adjustment . For this example, the coarse phase step is 1.02nsec.

be referred to in footnotes for the various other tables. Table 23. Abbreviated Signal Names and Detailed Signal Names Referenced by Them

conditions may affect device reliability. Table 24. Absolute Maximum Ratings [a] For information on the signals referenced by this abbreviation, see Table 23. Table 25. Recommended Operating Conditions[a] [a] It is the user’s responsibility to ensure that device junction temperature remains below the maximum allowed.

Table 26. Power Supply DC Characteristics[a][b]

Table 26. Power Supply DC Characteristics[a][b] (Cont.)

configuration of the device. [c] Supports 1.8V +5%, 2.5V +5% or 3.3V +5% operation, not a continuous range. [e] Supports 2.5V +5% or 3.3V +5% operation, not a continuous range. [f] Supports 1.2V +5% or 1.8V +5% operation, not a continuous range. the total for all V DD_DCO_Qx . of FODs on that supply that are enabled. Note that only the base current is needed if all FODs are disabled. NumFOD is the number of FODs on that supply that are enabled. Note that only the base current is needed if all FODs are disabled. [j] VDDA_DIA_FOD_B consumes higher current than V DDA_DIA_FOD_A because it has some additional circuitry, besides the FODs on it. [k] Please refer to Table 23 for details on the signals referenced by this abbreviation. [l] Currents for the outputs are shown in Table 27 or Table 28 as appropriate for the mode the individual output is operating in.

Table 27. Output Supply Current (Output Configured as Differential)[a][b][c] [a] Output current consumption is not affected by any of the core device power supply voltage levels. [b] Internal dynamic switching current at maximum f OUT is included. [d] Refers to the output voltage (swing) setting programed into device registers for each output. [e] IDDO_Qx denotes the current consumed by each V DDO_Qx supply. [f] Measured with outputs unloaded. [g] For information on the signals referenced by this abbreviation, see Table 23. Table 28. Output Supply Current (Output Configured as LVCMOS)[a][b][c] [a] Output current consumption is not affected by any of the core device power supply voltage levels. [b] Internal dynamic switching current at maximum f OUT is included. [d] Refers to the LVCMOS output drive strength (termination) setting programed into device registers for each output. [e] IDDO_Qx denotes the current consumed by each V DDO_Qx supply. [f] Measured with outputs unloaded. [g] For information on the signals referenced by this abbreviation, see Table 23. [h] Measured with outputs unloaded.

Table 29. LVCMOS/LVTTL DC Characteristics[a][b][c][d][e] [a] VIL should not be less than -0.3V.

[d] When Output Q are configured as LVCMOS, their output characteristics are specified in Table 35. [e] Input pair used as two single-ended clocks rather than as a differential clock. Table 30. Low-swing Mode Single-ended Input DC Characteristics[a][b][c][d][e] [a] VIL should not be less than -0.3V. [b] VIH should not be higher than V DD_CLK. [d] Input pair used as two single-ended clocks rather than a differential clock. [e] Input must be AC coupled.

Table 31. Differential Input DC Characteristics[a] [b] VIL should not be less than -0.3V. [c] VPP is the single-ended amplitude of the output signal. The differential specs is 2*V PP. [d] Common mode voltage is defined as the cross-point. Table 32. Differential Output DC Characteristics (VDDO_Qx = 3.3V+5%, VSS = 0V, TA = -40°C to 85°C)[a][b][c][d] [a] For information on the signals referenced by this abbreviation, see Table 23. [b] Terminated with 100 Ω across Qx and nQx. [c] If LVDS operation is desired, the user should select SWING = 00 and CENTER = 001 or 010. CENTER = 001 or 010 for 2.5V LVPECL operation. [e] VOVS is the single-ended amplitude of the output signal. The differential specs is 2*V OVS. [f] Refers to the differential voltage swing setting programed into device registers for each output. [h] Refers to the differential voltage crossing point (center voltage) setting programed into device registers for each output.

Table 33. Differential Output DC Characteristics (VDDO_Qx = 2.5V+5%, VSS = 0V, TA = -40°C to 85°C)[a][b][c][d] [a] For information on the signals referenced by this abbreviation, see Table 23. [b] Terminated with 100 Ω across Qx and nQx. [c] If LVDS operation is desired, the user should select SWING = 00 and CENTER = 001 or 010. 3.3V LVPECL levels cannot be generated. [e] VOVS is the single-ended amplitude of the output signal. The differential specs is 2*V OVS. [f] Refers to the differential voltage swing setting programed into device registers for each output. [h] Refers to the differential voltage crossing point (center voltage) setting programed into device registers for each output.

Table 34. Differential Output DC Characteristics (VDDO_Qx = 1.8V+5%, VSS = 0V, TA = -40°C to 85°C)[a][b][c] [a] For information on the signals referenced by this abbreviation, see Table 23. [b] Terminated with 100 Ω across Qx and nQx. [c] If LVDS operation is desired, the user should select SWING = 00 and CENTER = 010. [d] VOVS is the single-ended amplitude of the output signal. The differential specs is 2*V OVS. [e] Refers to the differential voltage swing setting programed into device registers for each output. [g] Refers to the differential voltage crossing point (center voltage) setting programed into device registers for each output.

Table 35. LVCMOS Clock Output DC Characteristics[a][b] [c] This refers to the register settings for the LVCMOS output drive strength within the device.

Table 36. Input Frequency Characteristics[a] [b] For crystal characteristics, see Table 37. [c] Refer to Overdriving the XTAL Interface. [d] For information on the signals referenced by this abbreviation, see Table 23. [e] For proper device operation, the input frequency must be divided down to 150MHz or less (DPLL Phase Detector maximum frequency = 150MHz). DPLL instead of using XO_DPLL. Table 37. Crystal Characteristics[a]

Table 38. AC Characteristics[a][b]

when using internal loopback. inputs CLK2/nCLK2 and CLK3/nCLK3. Fine phase measurements enabled. Table 38. AC Characteristics[a][b] (Cont.)

86©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet [b] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. [c] VDDA_X refers to V DDA_PDCP, VDDA_XTAL, VDDA_LC, and VDDA_BG. [d] Long-term frequency error with respect to the DPLL input reference. The typical value shown assumes the DPLL has been phase-locked to a stable input reference for at least 306 minutes (based on a 0.1mHz advanced holdover filter setting) before going into an advanced holdover state on disqualification of the input reference. [e] This parameter will vary with the quality of the reference to the system DPLL. The typical value shown assumes an ideal reference used for the system DPLL. [f] This parameter will vary with the quality of the TDC and system DPLL references. The typical value shown assumes an ideal reference is used as input to the TDC and system DPLL. [g] Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage [h] This parameter is defined in accordance with JEDEC Standard 65. [i] Measured at the differential cross points. [j] Measured at V DDO_Qx / 2. [k] Using LVCMOS with V DDO_Qx = 1.5V or 1.2V will result in much larger skews and is not recommended for skew-sensitive applications. [l] For this device, banks are defined as a list of outputs driven by specific FODs. Results do not apply if the output is driven by a different FOD. [m] This parameter is measured across the full operating temperature range and the difference between the slowest and fastest numbers is the variation. [n] Measured from the differential cross point of the input to the differential cross point of the associated output after device is locked and input is stable. Measured using integer-related input and output frequencies. [o] Measured with the channel in DPLL mode. [p] Characterized using input and output signals with swing = 0.9V, common mode voltage = 0.9V with respect to GND, and matching edge rates. [q] Characterized using input and output signals with swing = 0.410V, common mode voltage = 1.3V with respect to GND (LVDS signals), and matching edge rates. [r] Characterized over offset between REF and FB signals in the range of -20ns to 20ns. [s] Characterized using BGA-144 package devices. [t] The typical specification applies for all combinations of DPLLs and REF and FB differential pairs. [u] Rise and fall times on differential outputs are independent of the power supply voltage on the output. [v] Measured with outputs terminated with 50 Ω to GND. [w] For information on the signals referenced by this abbreviation, see Table 23. [x] Refers to the differential voltage swing setting programed into device registers for each output. [y] Measured with outputs terminated with 50 Ω to VDDO_Qx / 2. [z] Refers to the LVCMOS output drive strength (termination) setting programed into device registers for each output. [aa]This parameter has been characterized with F OUT = 50MHz. [ab]Phase noise measured using an SMA100A as the input source, for T A = -40°C to 85°C. Close-in phase noise performance will depend on the input source. [ac]Measured from the rising edge of nMR after all power supplies have reached > 80% of nominal voltage to the first stable clock edge on the output. A stable clock is defined as one generated from a locked analog or digital PLL (as appropriate for the configuration listed) with no further perturbations in frequency expected. [ad]At power-up, the nMR signal must be asserted for at least this period of time. [ae]Start-up time will depend on the actual configuration used. For more information on estimating start-up time, please contact Renesas technical support. [af] Noise spur amplitude measured relative to 156.25MHz carrier. [ag] Typical PSNR values specified over the modulation frequency range of 10kHz to 1MHz. [ah] Injected as sinusoidal noise to the specified power rail only. [ai] 0.1uF capacitor placed on modulated power rail. [aj] For proper device operation, the input frequency must be divided down to 150MHz or less (DPLL Phase Detector maximum frequency = 150MHz).

88©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Applications Information Recommendations for Unused Input and Output Pins Inputs CLKx / nCLKx Input For applications that do not require the use of the reference clock input, both CLK and nCLK should be left floating. If the CLK/nCLK input is connected but not used by the device, it is recommended that CLK and nCLK not be driven with active signals. LVCMOS Control Pins LVCMOS control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k  resistor can be used. Outputs LVCMOS Outputs Any LVCMOS output can be left floating if unused. There should be no trace attached. The mode of the output buffer should be set to tri-stated to avoid any noise being generated. Differential Outputs All unused differential outputs can be left floating. Renesas recommends that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Power Connections The power connections of the RC38612 can be grouped as shown if all members of the groups are using the same voltage level: ▪ VDD_DIG, VDD_CLK ▪ VDDA_PDCP_XTAL ▪ VDDA_FB ▪ VDDA_BG_LC VDD_GPIO_FOD , VDDA_DIA_FOD_A , VDDA_DIA_FOD_B (combining these is a possible source of coupling between frequency domains; should remain separate unless all outputs are in the same frequency domain) ▪ VDDO_Qn (can share supplies if output frequencies are the same, otherwise keep separated to avoid spur coupling)

• If all outputs Qn/nQn associated with any particular V DDO_Qn pin are not used, the power pin can be left floating Clock Input Interface The RC38612 accepts both single-ended and differential inputs. For information on input terminations, see Quick Guide - Output Terminations (AN-953) located on the RC38612 product page. If you have additional questions on input types not covered in the application discussion, or if you require information about register programming sequences for changing the differential inputs to accept LVCMOS inputs levels, see Termination - AC Coupling Clock Receivers (AN-844) or contact Renesas technical support.

Figure 51. AC Coupled LVDS Termination product page, or contact Renesas for support. For the latest vendor / frequency recommendations, please contact Renesas. values for external tuning capacitors, see Table 39. For power and current consumption calculations, refer to Renesas’ Timing Commander tool. Table 39. Recommended Tuning Capacitors for Crystal Input Synthesizer mode and referenced only to the crystal.

on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and/or testing are recommended to determine the minimum number needed. Base Package, Amkor Technology. Figure 52. P .C. Assembly for Exposed Pad Thermal Release Path – Side View (Drawing not to Scale) Table 40. Thermal Characteristics [a] Multi-Layer PCB with 2 ground and 2 voltage planes. [b] Assumes ePAD is connected to a ground plane using a grid of 9x9 thermal vias.

93©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. Marking Diagram

Ordering Information

Table 41. Ordering Information “000” for unprogrammed parts.

1. Line 1 indicates the manufacturer.
2. Lines 2 a nd 3 indicate the part number.
3. Line 4 indicates the following:

▪ “$” denotes the mark code.

Table 42. Pin 1 Orientation in Tape and Reel Packaging Table 43. Product Identification

95©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet Glossary Term Definition 1PPS One Pulse Per Second. eCLK Embedded clock. eCSR Embedded CSR access. eDATA Embedded DATA channel. ePP2S Embedded PP2S. ePPS Embedded PPS. This describes a means to embed 1PPS on a clock using PWM. PPES Pulse per ev en second. ESEC Even Second pulse. PP2S and ESEC are used interchangeably or sometimes combined as PP2S/ESEC. eSYNC Embedded SYNC pulse. PP2S Pulse Per 2 Second. This represents a 0.5Hz pulse. PPS Pulse Per Second. SCSR Standard Control / Status Register ZDB Zero Delay Buffer ZDPLL Zero Delay Phase Locked Loop

96©2022 Renesas Electronics Corporation April 13, 2022 RC38612 Datasheet

Revision History

Revision Date Description of Change April 13, 2022 Updated the 8A3xxxx Family Programming Guide version reference to v5.3 (see Functional Description ). November 15, 2021 Removed footnote [b] from Table 25. February 9 , 2021 Initial release.

© Renesas Electronics Corporation

© Renesas Electronics Corporation Package Revision HistoryRev No.Date CreatedDescriptionMay 10,2021Rev 04Added Chamfer on page 2May 6, 2021Rev 03Change Land Pattern Dimension

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.