RC38108

RC38208 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 Pin Assignments
• 1.2 Pin Descriptions
• 1.3 Pin Characteristics
• 2.1 Absolute Maximum Ratings
• 2.2 Recommended Operating Conditions
• 2.3 Thermal Specifications
• 2.4 APLL Phase Jitter
• 2.5 FOD Phase Jitter
• 2.6 TOD and Synthesis Phase Jitter
• 2.7 APLL Phase Noise
• 2.8 Peak APLL Spurious Power
• 2.9 Power Supply Noise Rejection
• 2.10 Crystal Oscillator Input and APLL AC/DC Electrical Characteristics
• 2.11 Recommended Crystal Characteristics
• 2.12 Clock Input (CLKIN/nCLKIN) AC/DC Characteristics
• 2.13 Output Frequencies and Start-Up Time
• 2.14 Phase and Frequency Uncertainty
• 2.15 Output-to-Output Skew and Input-to-Output Delay
• 2.16 LVCMOS Output AC/DC Characteristics
• 2.17 LVDS Output AC/DC Characteristics
• 2.18 HCSL Output AC/DC Characteristics
• 2.19 CML Output AC/DC Characteristics
• 2.20 Power Supply Current
• 2.21 GPIO, Serial Port, and nMR DC Electrical Characteristics
• 2.22 CMOS GPIO, Serial Port, and nMR Common Electrical Characteristics
• 2.23 I 2C Bus Target Timing Diagram
• 2.24 I 2C Bus Target Timing
• 2.25 I 2C Bus AC/DC Electrical Characteristics
• 2.26 SPI Target Timing Diagrams
• 2.27 SPI Target Timing
• 3.1 Overview
• 3.2 APLL Frequency Reference
• 3.3 Analog PLL
• 3.4 Integer Output Dividers
• 3.5 Fractional Output Dividers
• 3.6 Divider Synchronization
• 3.7 Digital PLLs
• 3.7.1 DPLL Free-Run State
• 3.7.2 DPLL Acquire State
• 3.7.3 DPLL Normal State
• 3.7.4 DPLL Holdover State
• 3.7.5 DPLL Hitless Switch State
• 3.8 DPLL External Feedback
• 3.9 DPLL Reference Switching
• 3.9.1 Hitless Reference Switching
• 3.9.2 Aligned Reference Switching
• 3.10 Clock Output Enable
• 3.11 Reference Monitors

Features

▪ Ultra-low phase noise synthesizer with jitter below 25fs RMS, 12kHz to 20MHz with 4MHz HPF ▪ Two independent low phase noise sync domains ▪ Four independent low phase noise frequency domains ▪ Support for JESD204B/C ▪ Time sync block with time to digital converter (TDC), time of day (TOD) counter, and PTP clocks ▪ 8 clock outputs with independent integer dividers

• 6: LVDS, HCSL (AC-LVPECL) or CML
• 2: LVDS, HCSL (AC-LVPECL) or LVCMOS ▪ Output frequency range:
• CML: DC to 2.5GHz
• LVDS or HCSL: DC to 1GHz
• LVCMOS: DC to 250MHz ▪ Two differential clock inputs configurable as four single-ended clock inputs ▪ Operates from a 1.8V supply. ▪ Clock inputs tolerate 1.8V input when the device is powered off, sinking less than 1mA ▪ CLKIN input frequency range: DC to 1GHz ▪ Time Sync TDC supports 1PPS and PP2S inputs ▪ DPLLs comply with ITU-T G.8262 and G.8262.1 ▪ DPLL input-to-output phase variation ≤ 100ps ▪ DCO frequency resolution < 10 -13 ▪ Package: 7 × 7 mm, 64-BGA

Figure 1. Typical Optical Front-End Use Case

R31DS0163EU0113 Rev.1.13 Page 4 May 11, 2026 RC38208/RC38108 Datasheet

1.1 Pin Assignments

Figure 4. Pin Assignments - Bottom View

1.2 Pin Descriptions

Table 1. Pin Descriptions A1 VDD_VCO Power - Power supply for the VCO. 1.8V is supported. A2 GND Power - Ground reference rail. unused. This pin must not be allowed to float. unused. This pin must not be allowed to float.

B1 VDD_FAN Power - Power supply for internal buffering to FODs and IODs. 1.8V is supported. B2 GND Power - Ground reference rail. unused. This pin must not be allowed to float. negative pin of a differential pair. negative pin of a differential pair. unused. This pin must not be allowed to float. negative pin of a differential pair. negative pin of a differential pair. C1 GND Power - Ground reference rail. C2 GND Power - Ground reference rail. C3 GND Power - Ground reference rail. C4 GND Power - Ground reference rail. C5 GND Power - Ground reference rail. C6 GND Power - Ground reference rail. C7 GND Power - Ground reference rail. C8 GND Power - Ground reference rail. D1 VDDXO_DCD Power - Power supply for XIN, XOUT and DCD block. 1.8V is supported. D2 GND Power - Ground reference rail. D3 GND Power - Ground reference rail. characteristics apply to this pin. operation. GPIO DC electrical characteristics apply to this pin. D6 GND Power - Ground reference rail. unused. This pin must not be allowed to float. unused. This pin must not be allowed to float. E1 XIN I - Crystal oscillator/ xCXO input. E2 GND Power - Ground reference rail. E3 VDD_DIG Power - Power supply for digital core, serial port, digital in FODs, and digital in the APLL. positive pin of a differential pair. positive pin of a differential pair. Table 1. Pin Descriptions (Cont.)

negative pin of a differential pair. F1 XOUT O - Crystal oscillator output. F2 GND Power - Ground reference rail. negative pin of a differential pair. negative pin of a differential pair. negative pin of a differential pair. G1 GND Power - Ground reference rail. G2 GND Power - Ground reference rail. electrical characteristics apply to this pin. characteristics apply to this pin. G6 VDD_FOD2 Power - Power supply for FOD2. 1.8V is supported. G7 VDD_FOD0 Power - Power supply for FOD0, nMR, GPIO0, and GPIO1. 1.8V is supported. unused. This pin must not be allowed to float. H1 GND Power - Ground reference rail. H2 GND Power - Ground reference rail. REP Power - Power supply for FOD1 and all FOD digital. 1.8V is supported. indicates the negative pin of a differential pair. indicates the positive pin of a differential pair. unused. This pin must not be allowed to float. indicates the negative pin of a differential pair. indicates the positive pin of a differential pair.

1.3 Pin Characteristics

Table 2. Input Characteristics

2.1 Absolute Maximum Ratings

conditions can adversely impact product reliability and result in failures not covered by warranty. Table 3. Absolute Maximum Ratings

1. This limit only applies when XIN is overdriven by an external oscillator. No limit is implied when connected directly to a crystal.
2. V DDx refers to the supply powering the GPIO. For VDD pin mapping, see GPIO VDD Pin Assignments.

2.2 Recommended Operating Conditions

2.3 Thermal Specifications

2.4 APLL Phase Jitter

Table 4. Recommended Operating Conditions[1][2]

1. All electrical characteristics are specified over Recommended Operating Conditions unless noted otherwise.
2. All conditions in this table must be met to guarantee device functionality and performance.

Table 5. Thermal Resistance Table 6. APLL Phase Jitter[1][2][3][4]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Characterized using a Rohde and Schwarz SMA100 overdriving the crystal interface.
3. Measured after the APLL has locked and settled.

2.5 FOD Phase Jitter

2.6 TOD and Synthesis Phase Jitter

2.7 APLL Phase Noise

1. All outputs enabled and generating clocks with the same frequency sourced from the APLL via integer output dividers.
2. Measured after the DPLL has locked and settled using a jitter free and wander-free reference.

Table 7. FOD Phase Jitter[1][2][3][4]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Characterized using a Rohde and Schwarz SMA100 overdriving the crystal interface.
3. Measured after the APLL has locked and settled.
4. All OUT[10:6] enabled and generating the same frequency sourced from the same FOD, other OUT[x] disabled.
5. Measured after the DPLL has locked and settled using a jitter free and wander-free reference.
6. See Table 12 for VCO frequencies supported by each part number.

Table 8. TOD and Synthesis Phase Jitter[1][2][3][4][5]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Characterized using a Rohde and Schwarz SMA100 overdriving the XTAL interface.
3. Measured after the APLL has locked and settled.
4. All OUT[10:7] enabled and generating the same frequency, other OUT[x] disabled.
5. Measured after the DPLL has locked and settled using a jitter free and wander-free reference.

Table 9. APLL Phase Noise[1][2][3][4]

2.8 Peak APLL Spurious Power

2.9 Power Supply Noise Rejection

1. The device will meet specifications after thermal equilibrium has been reached.
2. Characterized using a Rohde and Schwarz SMA100 overdriving the crystal interface.
3. Measured after the DPLL and APLL have locked and settled.
4. All OUT[7:1] enabled and generating the same frequency.
5. Measured after the DPLL has locked and settled using a jitter free and wander-free reference.

Table 10. Peak APLL Spurious Power[1][2][3][4][5][6]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Characterized using a Rohde and Schwarz SMA100 overdriving the crystal interface.
3. Measured after the APLL has locked and settled.
4. Measured after the DPLL has locked and settled using a jitter free and wander-free reference.
5. All OUT[7:1] enabled and generating the same frequency.
6. All FODs and OUT[8:11] disabled.

Table 11. Power Supply Noise Rejection[1]

1. The device will meet specifications after thermal equilibrium has been reached.
2. 100mV peak-to-peak sine wave applied to any VDDO, excluding VDDO of the output being measured and excluding VDD_VCO.
3. Relative to 156.25MHz carrier frequency.
4. Measured on any differential output.

Table 9. APLL Phase Noise[1][2][3][4] (Cont.)

2.10 Crystal Oscillator Input and APLL AC/DC Electrical Characteristics

2.11 Recommended Crystal Characteristics

Table 12. Crystal Oscillator Input and Analog PLL AC/DC Characteristics

1. For applications where the XIN input is overdriven, xo_buf_digicap_x1, xo_buf_digicap_x2, and xo_fixedcap_on should all be set to 0x0 for best
2. F TOL refers to the frequency accuracy of the APLL frequency reference, either a crystal connected between XIN and XOUT, or an oscillator

connected to XIN and overdriving the crystal interface. The APLL can reliably lock to a reference that meets the FTOL limits.

1. Inclusive of initial tolerance at 25°C, temperature stability, and aging.
2. The APLL frequency steering range (±F STEER) available for a DPLL or DCO to digitally steer the APLL is determined by the following expression:

APLL frequency reference is ±100PPM. then the APLL frequency steering range will be ±350PPM.

1. The frequency accuracy of the APLL frequency reference should be chosen to meet the free-running frequency requirements of the application,

information, see APLL Frequency Reference. Table 13. Recommended Crystal Characteristics

1. Refers to power in the crystal (equivalent series resistance).

2.12 Clock Input (CLKIN/nCLKIN) AC/DC Characteristics

2.13 Output Frequencies and Start-Up Time

Table 14. Clock Input (CLKIN/nCLKIN) AC/DC Characteristics

1. Common mode is defined as the cross-point.
2. Internal input dividers may be used to reduce the CLKIN/nCLKIN frequency to be within the valid range.

Table 15. Output Frequencies and Start-Up Time

1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output. A stable clock is defined

needed to load a configuration from internal OTP.

1. Start-up time will depend on the actual configuration used. For more information, please contact Renesas Technical Support.

2.14 Phase and Frequency Uncertainty

2.15 Output-to-Output Skew and Input-to-Output Delay

Table 16. Phase and Frequency Uncertainty[1][2]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Measured after the DPLL has locked and settled using a jitter free and wander-free reference.

Table 17. Output-to-Output Skew and Input-to-Output Delay[1][2]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Measured across the full operating temperature range.
3. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
4. This parameter is defined in accordance with JEDEC Standard 65.
5. Input-to-output delay is defined as the time between the rising edge of a reference clock at CLKINx and the associated rising edge of an output

reference input dividers must be bypassed.

1. Measured after the DPLL has locked and settled using a jitter free and wander-free reference to the DPLL.

2.16 LVCMOS Output AC/DC Characteristics

2.17 LVDS Output AC/DC Characteristics

Table 18. LVCMOS Output AC/DC Characteristics[1]

1. Measured with outputs terminated with 50Ω to V DDO/2.
2. These values are compliant with JESD8-7A.

Table 19. LVDS Output AC/DC Characteristics[1]

1. Terminated with 100Ω across OUTx and nOUTx, out_pull_down = 0x0, out_pull_up = 0x0.
2. Single-ended measurement.

2.18 HCSL Output AC/DC Characteristics

2.19 CML Output AC/DC Characteristics

Table 20. HCSL Output AC/DC Characteristics[1]

1. Terminated with 50Ω to ground on each of OUTx and nOUTx, out_pull_down = 0x0, out_pull_up = 0x0.
2. Single-ended measurement.
3. Output frequency = 10MHz.

Table 21. CML Output AC/DC Characteristics[1]

1. Terminated with 50Ω to V DDOx on each of OUTx and nOUTx, out_pull_down = 0x0, out_pull_up = 0x0.
2. Single-ended measurement.
3. Output frequency = 10MHz.

2.20 Power Supply Current

Table 22. Power Supply Current[1]

1. Internal dynamic switching current at maximum f OUT is included, unless otherwise noted.
2. For I DD_FOD0 this value does not include supply currents for GPIO outputs.
3. Measured with outputs unloaded.

2.21 GPIO, Serial Port, and nMR DC Electrical Characteristics

2.22 CMOS GPIO, Serial Port, and nMR Common Electrical Characteristics

Table 23. GPIO, Serial Port, and nMR DC Electrical Characteristics[1][2][3][4]

1. Applies to GPIO[4:0], SCL_SCLK, SDA_SDIO, SDO_A1, nCS_A0, and nMR.
2. Input specifications refer to pins acting as inputs, output specifications refer to pins acting as outputs.
3. V DDx refers to VDD_DIG for SCL_SCLK, SDA_SDIO, SDO_A1, and nCS_A0; and it refers to VDD_FOD0 for GPIO[4:0] and nMR (see Pin
4. Values are compliant with JESD8-7A.

Table 24. CMOS GPIO, Serial Port, and nMR Common Electrical Characteristics[1][2][3]

1. Applies to GPIO[4:0], SCL_SCLK, SDA_SDIO, SDO_A1, nCS_A0, and nMR.
2. Input specifications refer to pins acting as inputs, output specifications refer to pins acting as outputs.
3. V DDx refers to VDD_DIG for SCL_SCLK, SDA_SDIO, SDO_A1, and nCS_A0; and it refers to VDD_FOD0 for GPIO[4:0] and nMR (see Pin

up/pull-down resistor current.

2.23 I 2C Bus Target Timing Diagram

Figure 5. I2C Bus Target Timing Diagram

2.24 I 2C Bus Target Timing

2.25 I 2C Bus AC/DC Electrical Characteristics

Table 25. I2C Bus Target Timing

1. Device rejects noise spikes of a duration up to the maximum specified value.

Table 26. I2C Bus AC/DC Electrical Characteristics [1]

1. VOH is governed by the V PUP, the voltage rail to which the pull-up resistors are connected.

2.26 SPI Target Timing Diagrams

Figure 6. SPI Timing Diagrams

2.27 SPI Target Timing

Table 27. SPI Target Timing

1. This is the time until the device releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength and PCB trace

R31DS0163EU0113 Rev.1.13 Page 24 May 11, 2026 RC38208/RC38108 Datasheet 3. Functional Description

3.1 Overview

The RC38208/RC38108 is an ultra-low phase noise radio synchronizer, multi-frequency clock synthesizer, and digitally controlled oscillator (DCO). This flexible, low-power device outputs clocks with ultra-low, in-band phase noise and spurious for 4G and 5G RF transceivers and with jitter below 25fs-rms for 112Gbps and 224Gbps SerDes. The RC38208/RC38108 both have two differential clock inputs and eight differential clock outputs. The RC38208 provides two digital PLLs (DPLL) and the RC38108 provides one DPLL. Both devices provide an ultra-low phase noise analog PLL (APLL) based clock synthesizer, and three low phase noise fractional output divider (FOD) based clock synthesizers. For device block diagrams, see Figure 2 and Figure 3. The differential clock inputs can each be configured as two single-ended inputs. The clock inputs can operate at frequencies up to 1GHz for differential and 250MHz for single-ended. Six of the differential outputs can be configured for LVDS, HCSL (AC-LVPECL), or CML. Two of the differential outputs can be configured as LVDS or HCSL (AC-LVPECL) outputs, or they can each be configured as two LVCMOS outputs. The LVDS and HCSL (AC-LVPECL) outputs can operate at frequencies up to 1GHz, the CML outputs can operate at frequencies up to 2.5GHz, and the LVCMOS outputs can operate at frequencies up to 250MHz.

3.2 APLL Frequency Reference

The RC38208/RC38108 requires an APLL frequency reference. The frequency reference must support the phase noise, frequency accuracy, and frequency stability requirements of the intended application. The frequency reference can be implemented using an external crystal resonator connected between the XIN and XOUT pins and the device oscillator circuitry. Alternatively, an external oscillator can be connected to the XIN pin to overdrive the internal oscillator circuitry. If a crystal resonator is used for the frequency reference, the resonant frequency must be from 25MHz to 80MHz. If an external oscillator is used, it must provide a low-phase noise clock with frequency from 25MHz to 100MHz. For frequency reference requirements, see Table 12 and Table 13. For all applications, the phase noise of the frequency reference, after filtering by the APLL, is the minimum phase noise that will appear on all clocks output by the device. For DPLL applications, the accuracy of the frequency reference determines the frequency accuracy of the reference monitors and free-running clocks. The stability of the frequency reference determines the holdover stability of the DPLL and it affects the lowest filtering bandwidth the DPLL can support. For DCO applications, the accuracy of the frequency reference determines the frequency accuracy of the free- running clocks. The stability of the frequency reference determines the stability of the DCO clocks when a source of synchronization is not available, and it affects the lowest filtering bandwidth that a filtering algorithm can support. The accuracy of the frequency reference should be chosen to meet the free-running frequency accuracy requirements of the application (see Table 28 for examples) and to allow sufficient APLL frequency steering range for a DPLL or DCO to lock the APLL to its reference and to track reference noise. The available APLL frequency steering range (±FSTEER) is determined by the following expression: FSTEER = |FTOL| - |FACC|; where FACC is the accuracy of the frequency reference. See Table 12 for the value of FTOL and for additional details.

3.3 Analog PLL

this determines the free-run frequency accuracy of the device. undivided APLL clock is supplied to FOD[3:0].

3.4 Integer Output Dividers

Each IOD divides its input clock by a programmable 23-bit integer value.

3.5 Fractional Output Dividers

frequency resolution. The FOD output clocks are available via cross-connect to IOD[10:6]. digital steering of the APLL. The frequency steering range of the FODs is ±244PPM.

3.6 Divider Synchronization

For each DPLL, the feedback divider is synchronized with the IODs selected to divide the output of its synthesizer. Table 28. Recommended Free-Running Frequency Accuracy by Application

R31DS0163EU0113 Rev.1.13 Page 26 May 11, 2026 RC38208/RC38108 Datasheet paths is 10,000,000. Therefore, the outputs of IOD1 and IOD2 will be aligned with the input reference once for every 10,000,000 edges of the 10GHz clock. In other words, the 1kHz reference, the 8kHz and the 125MHz clocks will be aligned for every edge of the 1kHz input reference (excluding the effects of reference noise and DPLL filtering).

3.7 Digital PLLs

Up to four of the clock inputs can be selected as inputs for the reference monitors and the DPLL reference selection multiplexer. The DPLLs can lock to reference frequencies from 1kHz to 33MHz; clock inputs with frequencies above 33MHz must be divided using the internal reference dividers. Each DPLL steers its respective synthesizer (APLL or FOD) using digital frequency control words via the Combo Bus. The DPLLs support loop filter settings from 1mHz to 1kHz. In DCO mode, the DPLLs do not lock to an input reference and its frequency is steered by external software instead. The DPLLs operate in five states: Free-run, Acquire, Normal, Holdover, and Hitless Switch.

3.7.1 DPLL Free-Run State

In the Free-run state, a DPLL does not generate frequency control words and its respective synthesizer operates based on the frequency reference, and, if so configured, on information from other channels via the Combo Bus.

3.7.2 DPLL Acquire State

In the Acquire state, a DPLL tracks the selected qualified reference with the acquisition bandwidth and damping factor settings until the DPLL declares lock. The acquisition bandwidth and damping factor can be configured to accelerate the locking process. When a DPLL achieves lock it automatically transitions to the Normal state.

3.7.3 DPLL Normal State

In the Normal state, a DPLL tracks the selected reference with the normal locking bandwidth and damping factor settings. The normal bandwidth and damping factor can be configured to meet the filtering requirements of the intended application. In the Normal state, the long-term FFO of the DPLL synthesizer output clocks is the same as the long-term FFO of the reference and no cycle slips will occur.

3.7.4 DPLL Holdover State

In the Holdover state, a DPLL outputs digital frequency control words based on data acquired while in the Normal state so that its synthesizer outputs accurate frequencies when a reference is not provided to the DPLL. While a DPLL is in the Holdover state, its synthesizer operates based on the frequency reference, the DPLL holdover data, and, if so configured, on information from other channels via the Combo Bus.

3.7.5 DPLL Hitless Switch State

In the Hitless Switch state, the DPLL enters Holdover and measures the phase offset between the selected reference and the DPLL feedback clock. The measured phase offset is stored by the DPLL and is used to minimize the phase transient at the output of the DPLL when it locks to the new reference.

3.8 DPLL External Feedback

In some applications it is useful to use an external feedback path from the synthesizer to the DPLL. The DPLL reference selection multiplexer can select one of the external references for use as the feedback clock for the DPLL. When external feedback is used, the feedback clock must have the same frequency as the selected DPLL reference.

3.9 DPLL Reference Switching

The active reference for a DPLL is determined by forced selection or by automatic selection based on user- programmed priorities, locking allowances, reference monitors, revertive and non-revertive settings, and GPIO LOS inputs.

R31DS0163EU0113 Rev.1.13 Page 27 May 11, 2026 RC38208/RC38108 Datasheet A DPLL will act to close phase differences between the selected reference and the feedback clock. A step change in the phase difference can occur when a new reference is selected while the DPLL is in the Acquire state or the Normal state, or when the DPLL exits the Holdover state and enters the Acquire state. The resulting phase transient is filtered by the DPLL loop filter and the phase slope limiter, and there will not be any instantaneous phase steps or glitches on the device outputs.

3.9.1 Hitless Reference Switching

Hitless reference switching causes a DPLL to ignore the phase difference between the newly selected reference and the DPLL feedback clock; the DPLL will track the FFO of the newly selected reference. When hitless reference switching is enabled – and a DPLL is in the Acquire state or the Normal state, and the selected reference is changed – the DPLL enters the Holdover state and measures the phase offset between the newly selected reference and the DPLL feedback clock. The measured phase offset is stored and is subtracted from later phase offsets measured by the DPLL phase detector. The DPLL then enters the Acquire state. When the DPLL is in the Holdover state due to a reference failure or any other reason, hitless reference switching can be used when entering the Acquire state.

3.9.2 Aligned Reference Switching

Hitless reference switching does not allow a deterministic phase relationship to exist between the DPLL reference and its output clocks. When a deterministic phase relationship is needed, hitless reference switching should not be enabled so that the DPLL can align its output clocks with the DPLL reference.

3.10 Clock Output Enable

The RC38208/RC38108 enables and disables clock outputs synchronously to ensure there are no runt pulses during clock output enable and disable operations. Clock output enables can be controlled by software using the global_oe and out_driver_en register fields. Alternatively, GPIOs can be assigned the clock output enable function using the oe_source_sel and gpio_func register fields. For more information, see the RC38312, RC38112, RC38208, RC38108 Programming Guide. When a GPIO is assigned an output enable function it should be configured with gpio_resync = 0x0 and gpio_deglitch_bypass = 0x1; this disables GPIO resynchronization and bypasses the GPIO deglitcher ensuring lowest latency. When so configured, the maximum time delay from the time the voltage level on a GPIO input changes state until the clock output is enabled or disabled is 13ns plus 4 periods of the output clock.

3.11 Reference Monitors

The references can be continually monitored for loss of signal and for frequency offset per user programmed thresholds.

3.12 SYSREF

The RC38208/RC38108 includes a SYSREF controller that can output SYSREF signals on any of OUT[10:1]. The SYSREF controller can be configured to generate a continuous stream of SYSREF pulses triggered by a signal on a level-sensitive GPIO, active high or active low. Continuous SYSREF generation can also be controlled by a register bit. The SYSREF controller can be configured to generate a programmable number, from 1 to 255, of SYSREF pulses triggered by a signal on an edge-sensitive GPIO. The GPIO can be programmed to be rising or falling edge sensitive. A programmable number of SYSREF pulses can also be triggered by writing a register bit. A single RC38208/RC38108 device can control several other connected RC38208/RC38108 devices so that they all generate simultaneous and aligned SYSREF signals. The controlling device can be triggered as described above.

R31DS0163EU0113 Rev.1.13 Page 28 May 11, 2026 RC38208/RC38108 Datasheet

3.13 Time Sync

The RC38208/RC38108 includes a Time Sync block that enables external software to monitor and control phase and time alignment of the device with external signals and devices. The time of day (TOD) and Synthesis block synthesizes a time clock with a frequency between 10MHz and 250MHz. The block includes a 60-bit addressable TOD accumulator that counts time clock pulses and generates sync pulses with a frequency between 0.5Hz and 8kHz. The phase of the time sync pulses can be controlled by external software without disturbing the time clock. Any one of the FODs can be used to control the frequency of time clock. The time clock and time sync signals are available on any of OUT[10:8]. A time-to-digital converter (TDC) is provided to make precision phase and time comparisons between external signals, between internal signals, or between internal and external signals with frequencies between one-time- event and 33MHz. Internal signals available to the TDC are the time clock, time sync, and the DPLL feedback clocks. The precision of the TDC is better than 100ps.

3.14 Status and Control

All control and status registers are accessed through a 1MHz I2C or 20MHz SPI Target microprocessor interface. The device can automatically load a configuration from internal one time programmable (OTP) memory. Alternatively, the I2C controller interface can automatically load a configuration from an external EEPROM after reset. For more information about the device’s registers, please contact Renesas Technical Support.

4.1 Power Considerations

controller reset must be initiated to ensure the output dividers are synchronized. For power and current consumption calculations, see the Renesas IC Toolbox (RICBox) software tool.

4.2 Power-On Reset and Reset Controller

asserted and the voltage level on the nMR pin is high. minimum VIH and maximum VIL (see Table 23). Figure 7. Controller Reset Sequence Initiation nOUTx = high. Disabled LVCMOS outputs with cmos_same_phase = 1 will have OUTx = low and nOUTx = low. Disabled LVCMOS outputs with cmos_same_phase = 0 will have OUTx = low and nOUTx = high. to indicate the state of the device_ready_sts register bit by setting the associated gpio_func register field to 0x18. When a reset sequence completes, the rst_done_sts register bit is set to 0x1.

1 Uncertain

the device_ready_sts bit is set to 1. Any GPIO can be configured to indicate the state of the device_ready_sts bit.

4.3 Recommendations for Unused Input and Output Pins

4.3.1 CLKIN/nCLKIN Pins

connected but not used, should not be driven with active signals.

4.3.2 LVCMOS Control Pins

4.3.3 LVCMOS Output Pins

LVCMOS outputs should be configured to a high-impedance state to prevent noise generation.

4.3.4 Differential Output Pins

sides of a differential output pair should be either left to float or terminated.

4.4 Overdriving the Crystal Interface

should not be less than 0.6V/ns. Figure 8. LVCMOS Driver to Crystal Input Interface

Figure 9 shows one side of an LVPECL driver overdriving the XIN pin. Figure 9. LVPECL Driver to Crystal Input Interface

4.5 Differential Output Termination

other than LVDS, HCSL, or CML can be AC-coupled. Figure 10. The value of resistors RO1, RO2, RO3, and RO4 is 50Ω. Figure 10. Internal Termination Resistors for Differential Drivers components shown in this section are needed.

4.5.1 Direct-Coupled HCSL Termination

direct-coupled. The RC38208/RC38108 supports several programmable HCSL voltage swing options. amplitude at the receiver by 50%, this can be mitigated by adjusting the output amplitude of the driver.

Figure 11. HCSL Source Termination Using Internal Termination Figure 12 shows an HCSL driver direct-coupled with an HCSL receiver using end termination. Figure 12. HCSL End Termination

4.5.2 Direct-Coupled LVDS Termination

mounted and placed as close to the receiver as practical. Figure 13. LVDS Termination

4.5.3 Direct-Coupled CML Termination

coupled. The RC38208/RC38108 supports several programmable CML voltage swing options. Figure 14 shows a CML driver direct-coupled with a CML receiver.

Figure 14. Direct-Coupled CML Termination

4.5.4 AC-Coupled Differential Termination

RC38208/RC38108 supports several programmable HCSL voltage swing options. receiver by 50%; this can be mitigated by adjusting the output amplitude of the driver. Figure 15. AC-Coupled Differential Termination For more information on AC-coupling, see Renesas application note AN-953, Quick Guide - Output Terminations.

4.5.5 AC-Coupled LVPECL (AC-LVPECL) Termination

AC-coupling should be used for LVPECL receivers. termination resistors and biasing.

Figure 16. AC-LVPECL Termination for LVPECL Receiver with Internal Termination Resistors and Biasing For more information on AC-coupling, see Renesas application note AN-953, Quick Guide - Output Terminations.

Table 29. Ordering Information

1. Replace “xx” in the part number with the desired pre-programmed configuration code provided by Renesas in response to a custom configuration

request or use “00” for unprogrammed parts.

1. Temperature range refers to board temperature.

Table 30. Pin 1 Orientation in Tape and Reel Packaging ▪ Lines 1 and 2: part number.

• “$” indicates the mark code.
• “YWW” indicates the last digit of the year and work week the part was assembled.
• “#” indicates the last three characters of assembly lot. RC38108A ▪ Lines 1 and 2: part number. ▪ Line 3:
• “$” indicates the mark code.
• “YWW” indicates the last digit of the year and work week the part was assembled.
• “#” indicates the last three characters of assembly lot. RC38208A

R31DS0163EU0113 Rev.1.13 Page 36 May 11, 2026 RC38208/RC38108 Datasheet 8. Revision History Revision Date Description

1.13 May 11, 2026 ▪ Added a caution statement to Absolute Maximum Ratings

1.12 Nov 17, 2025 ▪ Clarified the use of nMR in power sequencing in Power Considerations

▪ Added a note to footnote 2 in Table 29

1.11 Sep 2, 2025

▪ Updated Overdriving the Crystal Interface to indicate the slew rate should not be less than 0.6V/ns.; previously, it indicated 0.2V/ns ▪ Updated footnote 3 in Table 24 ▪ Changed use of the terms “master/slave” to “controller/target” 1.10 Aug 18, 2025 ▪ Updated footnote 2 in Table 20 and Table 21 to indicate “Single-ended measurement.”

1.09 May 9, 2025

▪ Updated Figure 2 and Figure 3 ▪ Updated Table 3:

• Changed VDDOx to VDDx
• Changed the maximum value of the fourth condition for V IN

1.08 Mar 25, 2025

▪ Changed “device frequency reference” to “APLL frequency reference” in Table 12 and APLL Frequency Reference ▪ Updated t R/tF in Table 20

1.07 Jan 7, 2025 ▪ Updated the footnotes in Table 19 , Table 20, and Table 21

1.06 Dec 13, 2024

▪ Updated Table 6 ▪ Updated Z OUTDC in Table 18 ▪ Updated the minimum value of V OVS in Table 20 ▪ Added Clock Output Enable ▪ Updated the temperature range in Table 29

1.05 Oct 29, 2024 ▪ Updated footnote 1 in Ordering Information

1.04 Oct 18, 2024 ▪ Added ECAD Design Information

1.03 Sep 26, 2024

▪ Updated the descriptions of pin numbers E3 and F3 in Table 1 ▪ Updated footnote 2 in Table 19 ▪ Updated footnote 3 in Table 23 ▪ Completed other minor changes 1.02 Aug 7, 2024 ▪ Updated I DD_FODDIGBASE and IDD_PERFODDIG in Table 22. ▪ Updated the typical value of I DDOx for CML and output disabled in Table 22

1.01 Jul 16, 2024

▪ Updated the Features list ▪ Updated the following tables: Table 14, Table 22, Table 23, Table 24, Table 26, Table 27, and Table 28 1.00 Jun 28, 2024 Initial release.

R31DS0163EU0113 Rev.1.13 Page 37 May 11, 2026 RC38208/RC38108 Datasheet A. ECAD Design Information This appendix supports the development of the PCB ECAD model for this device. It is intended to be used by PCB designers. A.1 Part Number Indexing A.2 Symbol Pin Information A.2.1 64-BGA Orderable Part Number [1] 1. Replace “xx” in the part number with the desired pre-programmed configuration code provided by Renesas in response to a custom configuration request or use “00” for unprogrammed parts. Number of Pins Package Type Package Code/POD Number RC38208A1xxGBB#HC0 64 BGA BJG64 RC38208A1xxGBB#KC0 64 BGA BJG64 RC38208A1xxGBB#BC0 64 BGA BJG64 RC38108A1xxGBB#HC0 64 BGA BJG64 RC38108A1xxGBB#KC0 64 BGA BJG64 RC38108A1xxGBB#BC0 64 BGA BJG64 RC38208A2xxGBB#HC0 64 BGA BJG64 RC38208A2xxGBB#KC0 64 BGA BJG64 RC38208A2xxGBB#BC0 64 BGA BJG64 RC38108A2xxGBB#HC0 64 BGA BJG64 RC38108A2xxGBB#KC0 64 BGA BJG64 RC38108A2xxGBB#BC0 64 BGA BJG64 Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s) A1 VDD_VCO Power - A2 GND Power - A3 VDDO1 Power - A4 OUT1 Output - A5 OUT2 Output - A6 VDDO4 Power - A7 OUT4 Output - A8 OUT5 Output - B1 VDD_FAN Power - B2 GND Power - B3 VDDO2 Power - B4 nOUT1 Output - B5 nOUT2 Output - B6 VDDO5 Power - B7 nOUT4 Output - B8 nOUT5 Output - C1 GND Power - C2 GND Power - C3 GND Power - C4 GND Power - C5 GND Power - C6 GND Power - C7 GND Power - C8 GND Power - D1 VDDXO_DCD Power - D2 GND Power - D3 GND Power - D4 nCS_A0 Input - D5 nMR Input - D6 GND Power -

R31DS0163EU0113 Rev.1.13 Page 38 May 11, 2026 RC38208/RC38108 Datasheet D7 VDDO6 Power - D8 VDDO7 Power - E1 XIN Input - E2 GND Power - E3 VDD_DIG Power - E4 CLKIN0 Input - E5 CLKIN2 Input - E6 GPIO1 I/O - E7 nOUT6 Output - E8 OUT6 Output - F1 XOUT Output - F2 GND Power - F3 VDD_CLK Power - F4 nCLKIN0 Input - F5 nCLKIN2 Input - F6 GPIO0 I/O - F7 nOUT7 Output - F8 OUT7 Output - G1 GND Power - G2 GND Power - G3 SDO_A1 I/O - G4 SCL_SCLK I/O - G5 SDA_SDIO I/O - G6 VDD_FOD2 Power - G7 VDD_FOD0 Power - G8 VDDO8 Power - H1 GND Power - H2 GND Power - H3 VDD_FOD1_REP Power - H4 nOUT10 Output - H5 OUT10 Output - H6 VDDO10 Power - H7 nOUT8 Output - H8 OUT8 Output - Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

R31DS0163EU0113 Rev.1.13Page 39 May 11, 2026 RC38208/RC38108 Advance/Preliminary Datasheet A.3 Symbol Parameters Orderable Part Number [1] 1. Replace “xx” in the part number with the desired pre-programmed configuration code provided by Renesas in response to a custom configuration request or use “00” for unprogrammed parts. Qualification Mounting Type Min Operating Temperature Max Operating Temperature Min Input Voltage Max Input Voltage RoHS Output Type DPLL Channels Interface Max Output Frequency Phase Jitter XTAL Frequency RC38208A1xxGBB#HC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 2 I2C,SPI 2500 MHz 25 fs 80 MHz RC38208A1xxGBB#KC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 2 I2C,SPI 2500 MHz 25 fs 80 MHz RC38208A1xxGBB#BC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 2 I2C,SPI 2500 MHz 25 fs 80 MHz RC38108A1xxGBB#HC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 1 I2C,SPI 2500 MHz 25 fs 80 MHz RC38108A1xxGBB#KC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 1 I2C,SPI 2500 MHz 25 fs 80 MHz RC38108A1xxGBB#BC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 1 I2C,SPI 2500 MHz 25 fs 80 MHz RC38208A2xxGBB#HC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 2 I2C,SPI 2500 MHz 25 fs 80 MHz RC38208A2xxGBB#KC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 2 I2C,SPI 2500 MHz 25 fs 80 MHz RC38208A2xxGBB#BC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 2 I2C,SPI 2500 MHz 25 fs 80 MHz RC38108A2xxGBB#HC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 1 I2C,SPI 2500 MHz 25 fs 80 MHz RC38108A2xxGBB#KC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 1 I2C,SPI 2500 MHz 25 fs 80 MHz RC38108A2xxGBB#BC0 Industrial SMD -40 °C 85 °C 1.71 V 1.89 V Yes LVCMOS,LVDS,HCSL,CML 1 I2C,SPI 2500 MHz 25 fs 80 MHz

R31DS0163EU0113 Rev.1.13 Page 40 May 11, 2026 RC38208/RC38108 Datasheet A.4 Footprint Design Information A.4.1 64-BGA IPC Footprint Type Package Code/ POD Number Number of Pins BGA BJG64 64 Description Dimension Value (mm) Diagram Minimum body span (vertical side) Dmin 6.9 Maximum body span (vertical side) Dmax 7.1 Average length of grid (vertical side) D1ave 5.6 Minimum body span (horizontal side) Emin 6.9 Maximum body span (horizontal side) Emax 7.1 Average length of grid (horizontal side) E1ave 5.6 Minimum Standoff Height A1min 0.30 Maximum Height Amax 1.19 Average ball diameter Bnom 0.469 Distance between the center of any two adjacent balls (vertical side) PitchD 0.8 Distance between the center of any two adjacent balls (horizontal side) PitchE 0.8 P = Plain Grid, S = Staggered Grid GridType P F = Full Matrix, P = Perimeter, SD = Selectively Depopulated, TE = Thermally Enhanced MatrixType F Number of balls (vertical side) Rows 8 Number of balls (horizontal side) Columns 8 Maximum number of ball positions (Rows x Columns) Nmax 64 Number of actual balls present PinCount 64 Ball positions removed from matrix. Example: C5-H10, B6-B9, A1 DepopulateBalls - Ball positions added back into depopulated matrix. Example: C8, D6-F9 RepopulateBalls - Recommended Land Pattern (NSMD Design) Description Dimension Value (mm) Diagram Diameter of pad. If specified this overrides the calculated value. This can be used to specify a manufacturer's recommended pad size. X 0.365 Solder Mask Expansion S 0.05 A A1 min Amax 8 7 6 5 4 3 21 E B Pi tch E D PitchD B C D E F G A H B A1 Ball Area P X R, A&B

nxØb TOP VIEW

1234567 ABCDEFGH

RECOMMENDED LAND PATTERN(PCB Top View, NSMD Design) Detail BØ0.365 Cu landØ0.465 Solder mask opening Package Outline B Detail A(Rotated 90° CW) A1 BallArea 64 X Ø0.469 ±0.05 0.405, SRO (0.35)0.10CC CC' BOTTOM VIEW A1 Ball Area7.00 ±0.10 7.00 ±0.10 7.00 7.00 Detail C - C' 0.80 0.80A 1.09 ±0.10(0.74) © Renesas Electronics Corporation

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