RC32508ADDDGNE#KB0

RC32508A_V01 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 Clock Generator Mode
• 1.2 Jitter Attenuator or Synchronizer Mode
• 1.3 Power-Up, Configuration, and Serial Interfaces
• 1.4 Input Clocks
• 1.4.1 Crystal/Oscillator Input
• 1.4.2 Reference Clock Input
• 1.5 Input Monitors
• 1.5.1 DPLL Input Monitors
• 1.5.2 APLL Input Monitors
• 1.6 APLL
• 1.6.1 APLL Feedback Divider
• 1.6.2 APLL Lock Detector
• 1.6.3 Direct DCO Control
• 1.7 DPLL
• 1.8 DPLL Reference Selection
• 1.8.1 Manual Reference Selection
• 1.8.2 Automatic Reference Selection
• 1.8.3 Hitless Reference Switching
• 1.9 DPLL Operating Modes
• 1.9.1 Free-run
• 1.9.2 Acquire
• 1.9.3 Normal
• 1.9.4 Holdover
• 1.9.5 Hitless Switch
• 1.9.6 Write Frequency
• 1.9.7 Manual Mode
• 1.10 DPLL Lock Detector
• 1.11 Output Dividers
• 1.11.1 Integer Output Dividers
• 1.12 Clock Outputs
• 1.12.1 Output Buffer in Single-Ended Mode
• 1.12.2 Output Buffer in Differential Mode
• 1.12.3 Output Enable Control
• 1.13 OTP
• 4.1 Absolute Maximum Ratings
• 4.2 Recommended Operating Conditions
• 4.3 Reference Clock Phase Jitter and Phase Noise
• 4.4 AC Electrical Characteristics
• 4.5 DC Electrical Characteristics
• 5.1 Recommendations for Unused Input and Output Pins
• 5.1.1 Inputs

Features

▪ Can be configured as clock generator or jitter attenuator/synchronizer ▪ Low power, less than 0.8W typical ▪ Low jitter, less than 50fs-RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter ▪ PCIe Gen 1-6 CC, SRIS, and SRNS support ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ Up to two independent frequency domains and eight integer output dividers ▪ Each frequency domain can be slaved with DPLL or free-run ▪ DPLL can be configured as DCO ▪ LVCMOS, AC-LVPECL, AC-LVDS, HCSL, AC-CML output modes supported with programmable output swing ▪ Up to two single ended or one differential clock inputs, one crystal/XO/TCXO/OCXO input ▪ Supports 1MHz I2C, 400kHz SMBus, or 50MHz SPI serial port ▪ Internal non-volatile memory (up to eight different configurations) provides default device settings on power-up ▪ 1.8V core and output operation ▪ -40° to +85°C industrial temperature operation Figure 1. Switch Line Card Figure 2. Switch Fabric Card

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device supports SyncE for network-based synchronization. Figure 3. Block Diagram

1.1 Clock Generator Mode

namely OUT0-0, OUT1-0, OUT2-0, and OUT3-0. differential or 16 LVCMOS outputs can be obtained. Figure 4. Clock Generator Mode with RC32508A when External Reference is Fed into CLKIN

▪ When locking to an external crystal applied to XIN/REF-0/XOUT-0, APLL0 is locked to the crystal. output dividers that is in term fed to four clock outputs, OUT0-1, OUT1-1, OUT2-1, and OUT3-1. differential outputs and 1 LVCMOS output or 15 LVCMOS outputs can be obtained. Figure 5. Clock Generator Mode with RC32508A when External Crystal fed into XIN/REF-0/XOUT-0

1.2 Jitter Attenuator or Synchronizer Mode

▪ APLL0 is locked to external crystal or oscillator that is applied to XIN/REF-0/XOUT-0. dividers that is in term fed to four clock outputs, OUT0-1, OUT1-1, OUT2-1, and OUT3-1. differential outputs and one LVCMOS output or 15 LVCMOS outputs can be obtained. Figure 6. Jitter Attenuator or Synchronizer Mode with RC32508A when External Reference is Fed into CLKIN

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1.3 Power-Up, Configuration, and Serial Interfaces

The RC32508A can be powered up and configured in two ways: ▪ From internal non-volatile memory using OTP user configurations (UserCfgs) ▪ From its slave serial interface – The RC32508A supports two slave serial interfaces: I2C and SPI. These interfaces share the same pins, so only one is available at a time. Additionally, all of the device logic pins are sampled at the rising edge of the internal master reset signal and some of them may be used in setting the initial configuration.

1.4 Input Clocks

The RC32508A supports one crystal/reference input that is used as a reference to each of the two analog PLLs (APLLs). One differential or two single-ended clock inputs that are used as a reference to the digital PLL (DPLL) and support hitless reference switching.

1.4.1 Crystal/Oscillator Input

The crystal input supports crystal frequencies of 25MHz to 80MHz with a recommended load capacitance of 8- 12pF. The crystal input can being overdriven with differential or single-ended inputs with proper external terminations. The supported frequency range is 25MHz to 80MHz when doubler logic for APLL is enabled, and 50Mz to 160MHz when doubler logic for APLL is disabled. An available LOS monitor detects the loss of signal on crystal input.

1.4.2 Reference Clock Input

There is differential reference clock input that supports one differential or two single-ended CMOS logic levels without external terminations. If set to single-ended type, each of the differential inputs turn into two single-ended inputs. Internal biasing is available for AC-coupled applications. The two clock inputs can be left floating when unused. An available LOS monitor detects the loss of signal on reference clock inputs.

1.5 Input Monitors

1.5.1 DPLL Input Monitors

There are two types of reference clock monitors. The APLL input is monitored for Loss of Signal (LOS). While the DPLL clock inputs (CLKIN, nCLKIN) each have LOS, activity, and frequency monitoring. ▪ The LOS monitor detects missing edges over a window of several reference clock periods. For the best accuracy, it is recommended to program the window to be equal to at least eight times that of the measuring clock period. ▪ The frequency monitor can be configured to measure the reference over a nominal 5ms time window in order to achieve ~1ppm granularity. ▪ The frequency monitor can be configured to measure the reference over a nominal 0.4s time window in order to achieve ~12ppb granularity.

1.5.2 APLL Input Monitors

The APLL input is monitored for Loss of Signal (LOS). The LOS monitor detects missing edges over a window of several reference clock periods. For the best accuracy, it is recommended to program the window to be equal to at least eight times that of the measuring clock period.

1.6 APLL

Each of the two APLLs, APLL0 and APLL1, is a fractional LC-VCO based PLL with an operating range from 9.7GHz to 10.7GHz. The crystal or oscillator input clock is used to drive each of the APLLs, and can be frequency doubled for increased performance. The APLLs are temperature compensated for the utmost

R31DS0136EU0102 Rev.1.02 Page 11 Dec 6, 2024 RC32508A Datasheet frequency stability. The high-frequency clock output from each of the APLL is provided to each of the four output dividers that feed into two pairs of four outputs each (OUT0-0/1, OUT1-0/1, OUT2-0/1, OUT3-0/1).

1.6.1 APLL Feedback Divider

Each of the APLL Feedback dividers consists of two parts. The Multi-Modulus Divider (MMD) performs the actual division of the VCO frequency down to the nominal frequency needed to match the PFD input reference frequency (from frequency doubler). The MMD contains a number of integer divide ratios that are switched between under control of the Sigma-Delta Modulator (SDM) block. This allows a fractional divide ratio to be achieved while also providing noise shaping to minimize the spurs that switching would otherwise cause. The fractional portion of the divide ratio is a 27-bit integer representing the numerator of an M/N fraction. The denominator is fixed at 227. It is recommended that fractions close to 0, 1, or 1/2 be avoided for best phase noise performance.

1.6.2 APLL Lock Detector

The APLL lock detector is available for each APLL and each indicates whether the APLL is locked to a functioning crystal or reference input by monitoring the phase errors. Lock status is available on the LOCK-x or in the register map.

1.6.3 Direct DCO Control

When each of the APLLs is in Synthesizer mode, a frequency offset can be programmed. The frequency adjustment’s LSB resolution is 2-40, which translates to approximately 0.91ppt.

1.7 DPLL

To operate in Jitter Attenuator or Synchronizer mode, the APLL0 is used as a DCO and forms a fractional-N DPLL architecture that is locked to the chosen reference clock input. T he fractional portion of the divide ratio is a 27-bit integer representing the numerator of an M/N fraction. The denominator is fixed at 227. It is recommended that fractions close to 0, 1, or 1/2 be avoided for best phase noise performance.

1.8 DPLL Reference Selection

The DPLL can lock to either the differential or one of the two single-ended input clocks. The reference selection can be either automatic or manual and when enabled, hitless switching results in negligible (<100ps) output clock initial phase hit during reference switching or the DPLL exiting from holdover.

1.8.1 Manual Reference Selection

In manual mode, the selection is set in the register map.

1.8.2 Automatic Reference Selection

In automatic mode, the selection is based on clock quality statuses and priorities. The quality statuses are from clock monitors. If two clock inputs are programmed to the same priority, the one with lower index number takes precedence. The automatic reference selection can either be revertive or non-revertive. In revertive mode, the reference clock that is qualified and of the highest priority is always selected. If a reference clock of higher priority than the currently selected one becomes qualified, the DPLL will switch to that reference clock. If a reference clock of equal or lower priority than the currently selected one becomes qualified, the DPLL will keep the current reference clock. In non-revertive mode, if there is a higher priority reference clock is coming back (from disqualified to qualified), the current selected reference clock remains selected unless it gets disqualified.

1.8.3 Hitless Reference Switching

If hitless switching is enabled, the output clock initial phase hit will be minimized (< 200ps) during reference switching or the DPLL exiting from holdover, while the input clock and output clock may no longer be aligned. If

R31DS0136EU0102 Rev.1.02 Page 12 Dec 6, 2024 RC32508A Datasheet hitless switching is disabled, the output clock phase change slope is determined by DPLL loop characteristics and phase slope limit. Minimal initial phase hit of < 200ps can only be met during reference switching when the reference clocks are of same fractional frequency offset. If they are of different fractional frequency offset (up to 244ppm), the output clock phase will track to the new reference clock.

1.9 DPLL Operating Modes

The DPLL can operate in six different states: Free-run, Acquire, Normal, Holdover, Hitless-switch, and Write- frequency. The state transitions can be either manual or automatic.

1.9.1 Free-run

During power-on reset or VCO calibration or in synthesizer mode, the DPLL is in the free-run state. In this state, no reference clock is used and the output clocks track the APLL reference clock.

1.9.2 Acquire

When there is at least one qualified reference, the DPLL tracks the selected qualified reference at the acquisition bandwidth and damping factor settings. If the reference clock is disqualified and no other qualified reference clock is available, the DPLL transitions to either the free-run state or the holdover state. When lock-detector detects a lock, DPLL transitions to the normal state.

1.9.3 Normal

In the normal state, the DPLL tracks the selected reference clock with the normal locking bandwidth and damping factor settings. If the selected reference clock is disqualified, state machine goes to either the holdover or the free-run state. At a reference switch, the state machine goes via the Holdover state to the Hitless Switch state or the Acquire state.

1.9.4 Holdover

In the holdover state, the DPLL output frequency is held at the instantaneous value or a value that is low-pass filtered and/or restored from the holdover history registers.

1.9.5 Hitless Switch

At a hitless reference switch or a hitless transition from the holdover state, the DPLL’s TDC measures the phase offset between the (newly) selected reference clock and the feedback clock, both of which are averaged. This offset is stored in an internal phase offset register. As a result, the output clocks experience a minimal phase transient due to the reference switch or coming out of holdover. After the hitless switch procedure finishes, the state machine transitions to the Acquire state unless the reference clock fails.

1.9.6 Write Frequency

In the write-frequency mode the DPLL tracks an external stable oscillator like TCXO or OCXO. The DPLL feedback divider is controlled via I2C or SPI to operate the DPLL in DCO mode.

1.9.7 Manual Mode

The DPLL operation can be forced to the free-run, holdover, and write-frequency states.

1.10 DPLL Lock Detector

The DPLL lock detector declares lock when the phase from the phase detector remains within a programmable range for a programmable time interval both of which are set in the register map. This indicates that the DPLL is locked to the reference clock input. When the phase output from the phase detector is below the lock threshold for half of the programmed lock interval, the internal lock signal is asserted and the normal loop filter bandwidth and damping applied to the DPLL’s loop filter instead of the acquire filter settings.

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1.11 Output Dividers

The RC32508A provides eight integer output dividers (IOD), and each of the two APLLs feeds into four output dividers.

1.11.1 Integer Output Dividers

All eight IODs are identical and first four IODs derive the input clock from APLL0, and second four IODs derive the input clock from APLL1. Each IOD provides output frequencies from 1MHz to 1GHz. Changing IOD values results in an immediate change to the new frequency. Glitchless squelch and release of the IOD clock is supported.

1.12 Clock Outputs

The RC32508A supports up to 8 differential or 16 single-ended clock outputs or any combination of differential and single-ended clock outputs. Each differential clock output can be programmed as two single-ended clock outputs.

1.12.1 Output Buffer in Single-Ended Mode

When used as a single-ended output buffer, two copies of the same output clock are created with LVCMOS output levels. Each clock will have the same frequency, phase, voltage, and current characteristics.

1.12.2 Output Buffer in Differential Mode

When used as a differential output buffer, the user can control the output voltage swing (VOVS) and common mode voltage (VCMR) of the buffer that can be DC-coupled to HCSL input interface and AC-coupled to LVDS, LVPECL, or CML input interfaces.

1.12.3 Output Enable Control

During the power-up sequence, the clock output drivers are powered down (OUTx-0/1 and nOUTx-0/1 are tri- stated) until the power supplies have stabilized. Then the output drivers are powered up in the default disabled state (OUTx-0/1 and nOUTx-0/1 are both held low). After the OTP configuration load completes, the clock output drivers can be held disabled until the APLL and/or DPLL locks: ▪ Clock output drivers are disabled until APLL lock asserts ▪ Clock output drivers are disabled until DPLL lock asserts ▪ Clock output drivers are enabled immediately After startup, the clock output drivers are then user-controllable using output enable control.

1.13 OTP

The RC32508A supports four user-definable, non-volatile start-up configurations stored in an internal OTP (one- time programmable) memory that covers the blocks related to DPLL, APLL0, four output dividers feeding OUT0-0, OUT1-0, OUT2-0, OUT3-0. An additional four user-definable non-volatile start-up configurations stored in an internal OTP memory that covers the blocks related to APLL1, four output dividers feeding OUT0-1, OUT1-1, OUT2-1, OUT3-1. Each configuration can store values for all write-able configuration registers. The configuration for DPLL, APLL0 and the four outputs fed by APLL0 is selected by the values of LOCK-0, OE_nCS-0, and latched at power-up. The configuration for APLL1 and the four outputs fed by APLL1 is selected by the values of LOCK-1, OE_nCS-1 and latched at power-up. The serial interfaces are inactive until all register values specified in the selected configuration are written. The OTP contents can be locked to prevent further programming. The RC32508A supports OTP read with a VDDD0/1 supply voltage of 1.8V.

Figure 7. Pin Assignments Table 1. Pin Descriptions

1 XIN/REF-0 I

2 XOUT-0 O

Crystal Output for APLL0. This pin should be connected to a crystal. rail. XIN/REF-0 and XOUT-0 are referenced to this voltage supply.

5 XIN/REF-1 I

then this pin should be left unconnected.

6 XOUT-1 O

Crystal Output for APLL1. This pin should be connected to a crystal.

rail. XIN/REF-1 and XOUT-1 are referenced to this voltage supply. 9 VDDREF Power Reference input supply. This pin should be connected to 1.8V supply rail. CLKIN and nCLKIN are referenced to this voltage supply.

10 CLKIN I

reference clock input. Input buffer should be disabled if unused. single leg of an LVDS clock (no additional external termination).

13 OE_nCS-0 I

pull-up enable, and pull-down enable can be programmed.

14 OE_nCS-1 I

pull-up enable, and pull-down enable can be programmed. SPI Mode: Chip Select, active low for programming APLL1 blocks.

15 SCL_SCLK I Optional

I2C Mode: I2C interface bi-directional clock.

16 SDA_SDIO I/O Optional

I2C Mode: I2C interface bi-directional data in open-drain mode.

17 VDDD-0 Power

be connected to 1.8V supply rail. OE_nCS-0, SCL_SCLK, and SDA_SDIO are referenced to this voltage.

18 VDDD-1 Power

connected to 1.8V supply rail. OE_nCS-1, SCL_SCLK, and SDA_SDIO are referenced to this voltage. 19 nOUT3-0 O Output Clock 3 negative from APLL0. 20 OUT3-0 O Output Clock 3 positive from APLL0.

21 VDDO3-0 Power

connected to 1.8V supply rail. and outputs are programmed to be powered down. 22 nOUT3-1 O Output Clock 3 negative from APLL1. 23 OUT3-1 O Output Clock 3 positive from APLL1.

24 VDDO3-1 Power

connected to 1.8V supply rail. and outputs are programmed to be powered down. 25 nOUT2-1 O Output Clock 2 negative from APLL1. 26 OUT2-1 O Output Clock 2 positive from APLL1. Table 1. Pin Descriptions (Cont.)

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27 VDDO2-1 Power

Supply voltage for output pair OUT2-1 and nOUT2-1. This pin should be connected to 1.8V supply rail. This pin can be left unconnected if clock output 2 from APLL1 is unused and outputs are programmed to be powered down. 28 nOUT2-0 O Output Clock 2 negative from APLL0. 29 OUT2-0 O Output Clock 2 positive from APLL0.

30 VDDO2-0 Power

Supply voltage for output pair OUT2-0 and nOUT2-0. This pin should be connected to 1.8V supply rail. This pin can be left unconnected if clock output 2 from APLL0 is unused and outputs are programmed to be powered down. 31 nOUT1-1 O Output Clock 1 negative from APLL1. 32 OUT1-1 O Output Clock 1 positive from APLL1.

33 VDDO1-1 Power

Supply voltage for output pair OUT1-1 and nOUT1-1. This pin should be connected to 1.8V supply rail. This pin can be left unconnected if clock output 1 from APLL1 is unused and outputs are programmed to be powered down. 34 nOUT1-0 O Output Clock 1 negative from APLL0. 35 OUT1-0 O Output Clock 1 positive from APLL0.

36 VDDO1-0 Power

Supply voltage for output pair OUT1-0 and nOUT1-0. This pin should be connected to 1.8V supply rail. This pin can be left unconnected if clock output 1 from APLL0 is unused and outputs are programmed to be powered down. 37 OUT0-1 O Output Clock 0 positive from APLL1. 38 nOUT0-1 O Output Clock 0 negative from APLL1.

39 VDDO0-1 Power

Supply voltage for output pair OUT0-1 and nOUT0-1. This pin should be connected to 1.8V supply rail. This pin can be left unconnected if clock output 0 from APLL1 is unused and outputs are programmed to be powered down. 40 OUT0-0 O Output Clock 0 positive from APLL0. 41 nOUT0-0 O Output Clock 0 negative from APLL0.

42 VDDO0-0 Power

Supply voltage for output pair OUT0-0 and nOUT0-0. This pin should be connected to 1.8V supply rail. This pin can be left unconnected if clock output 0 from APLL0 is unused and outputs are programmed to be powered down. 43 NC NA No connect.

44 VDDA-1 Power

Analog function supply for core analog functions of APLL1. This pin should be connected to 1.8V supply rail. LOCK-1 is referenced to this voltage.

45 LOCK-1 O See

description

APLL1 lock status or other status, including polarity, pull-up enable and pull-down enable, can be programmed. 46 NC NA No connect.

47 VDDA-0 Power

Analog function supply for core analog functions of DPLL and APLL0. This pin should be connected to 1.8V supply rail. LOCK-0 is referenced to this voltage.

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48 LOCK-0 O See

DPLL/APLL0 lock status or other status, including polarity, pull-up enable and pull-down enable, can be programmed. EPAD GND Power Ground supply voltage. EPAD must be connected before any positive supply voltage is applied. Table 2. Pin Characteristics

4.1 Absolute Maximum Ratings

implied. Exposure to absolute maximum rating conditions can affect device reliability.

4.2 Recommended Operating Conditions

Table 3. Absolute Maximum Ratings

1. This limit only applies to the XIN/REF-0 and XIN/REF-1 inputs when being overdriven by an external signal. No limit is implied when this

is connected directly to a crystal. Table 4. Recommended Operating Conditions [1][2]

4.3 Reference Clock Phase Jitter and Phase Noise

1. It is the user’s responsibility to ensure that device junction temperature remains below the maximum allowed.
2. All conditions in this table must be met to ensure device functionality.
3. Supports 1.8V ±5% or 3.3V ±5% operation, not a continuous range.
4. VDDOx represents any of VDDO3-0, VDDO3-1, VDDO2-0, VDDO2-1, VDDO1-0, VDDO1-1, VDDO0-0, VDDO0-1.
5. Currents for the outputs are shown in Table 11 as appropriate for the mode the individual output is operating in.
6. This implies all supply rails must reach their minimum voltage within maximum TPU.

Table 5. Output Phase Jitter Characteristics [1][2]

1. Electrical parameters are ensured over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. APLL0 at 10.625GHz to allow for outputting common ETH/FC frequencies.

Table 4. Recommended Operating Conditions [1][2] (Cont.)

4.4 AC Electrical Characteristics

1. Characterized using a Rohde and Schwarz SMA100A driving the CLKIN.
2. Characterized using a Rohde and Schwarz SMA100A overdriving the XTAL Interface.
3. Characterized using a Rohde and Schwarz SMA100A driving the CLKIN.

Table 6. Input Frequency Characteristics [1]

1. For crystal characteristics, see Table 7.
2. For proper device operation, the input frequency must be divided down to fTDC or less (see Table 8).

Table 7. Crystal Characteristics [1]

1. Measured ESR is always more than 2 × 80Ω.

Table 8. PLL Characteristics [1][2]

1. Electrical parameters are ensured over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Measured from when all power supplies have reached > 80% of nominal voltage to the first stable clock edge on the output. A stable

perturbations in frequency expected. Table 9. Output Frequency Characteristics [1][2] Table 8. PLL Characteristics [1][2] (Cont.)

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
2. This parameter is defined in accordance with JEDEC Standard 65.
3. Measured at the differential cross points.
4. Measured at VDDOx-0/1 / 2.
5. This parameter is measured across the full operating temperature range and the difference between the slowest and fastest numbers is
6. Defined as the time between the output rising edge and the input rising edge that caused it.
7. ClkIn was from Rhode and Schwarz SMA 100B Signal Generator.
8. Defined as the time between the output rising edge and the input rising edge that caused it.
9. ClkIn was from Rhode and Schwarz SMA 100B Signal Generator.
10. Measured with outputs terminated with 50Ω to GND.
11. Measured with outputs terminated with 50Ω to VDDOx / 2.

Table 10. Power Supply Noise Rejection [1][2]

1. Electrical parameters are ensured over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. 50mV peak-to-peak sine-wave noise signal injected on indicated power supply pin(s).
2. Noise spur amplitude measured relative to 156.25MHz carrier.
3. Excluding VDDOx of the output being measured.

Table 9. Output Frequency Characteristics [1][2] (Cont.)

4.5 DC Electrical Characteristics

Table 11. Power Supply DC Characteristics – Supply Current [1][2][3]

1. Output current consumption is not affected by any of the core device power supply voltage levels.
2. Internal dynamic switching current at maximum fOUT is included.

1. Voltage of the input signal must be appropriate for the VDDREF voltage supply level when using a DC-coupled connection.
2. IDDOx-0/1 denotes the current consumed by each VDDOx-0/1 supply.
3. Measured with outputs unloaded.

Table 12. LVCMOS Status and Control Signal DC Characteristics [1][2]

1. 3.3V characteristics in accordance with JESD8C-01, 1.8V characteristics in accordance with JESD8-7A.

Figure 8. I2C Slave Timing Diagram Table 13. I2C Slave Timing [1]

1. All values referred to VIH (minimum) and VIL (maximum) levels (see Table 12).
2. tHD:DAT is the data hold time that is measured from the falling edge of SCL, and applies to data in transmission and the acknowledge.
3. A device must internally provide a hold time of at least 300ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

1. The maximum tHD:DAT could be 3.45μs and 0.9μs for Standard mode and Fast mode, but must be less than the maximum of tVD:DAT or

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

1. A Fast mode I2C-bus device can be used in a Standard mode I2C-bus system, but the requirement tSU:DAT 250ns must then be met.

Standard mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

Figure 9. SPI Timing Diagram Table 14. I2C Bus Characteristics

1. A device must internally provide a hold time of at least 300ns for the SDA signal (with respect to the VIH (minimum) of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

1. If mixed with Hs-mode devices, faster fall times are allowed.
2. The maximum tf for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tf is specified at

exceeding the maximum specified tf.

1. In Fast Mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

1. Necessary to be backwards compatible to Fast mode.

Table 15. SPI Slave Timing

1. Adding the extra half period of delay is a register programming option to emulate read data being clocked out on the opposite edge of
2. This is the time until the RC32508A releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength and

Table 16. Differential Clock Input DC Characteristics [1]

1. VIL should not be less than -0.3V.
2. VPP is the single-ended amplitude of the input signal. The differential specification is 2*VPP.
3. VDDREF = 1.8V ±5%. Voltage of the input signal must be appropriate for the VDDREF voltage supply level when using a DC-coupled
4. Common-mode voltage is defined as the cross-point.
5. Voltage of the input signal must be appropriate for the VDDREF voltage supply level when using a DC-coupled connection. For example,

Table 17. LVCMOS Clock Input DC Characteristics [1][2][3]

1. 1.8V characteristics in accordance with JESD8-7A.
2. Input specifications see both CLKIN and nCLKIN.

Table 18. Differential Clock Output DC Characteristics [1][2][3]

1. Terminated with 100Ω across OUTx-0/1 and nOUTx-0/1.
2. OUTx-0/1 refers to any of the output pairs OUT3-0, OUT3-1, OUT2-0, OUT2-1, OUT1-0, OUT1-1, OUT0-0, OUT0-1.
3. Measurement taken from single-ended waveform.
4. Defined as the minimum instantaneous voltage including undershoot.
5. Defined as the maximum instantaneous voltage including overshoot.
6. Terminated with 50Ω to GND on each of OUTx-0/1 and nOUTx-0/1.
7. Defined as the total variation of all crossing voltages of rising OUTx-0/1 and falling nOUTx-0/1, This is the maximum allowed variance
8. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
9. VOVS is the single-ended amplitude of the output signal. The differential specs is 2*VOVS.
10. Terminated with 100Ω across OUTx-0/1 and nOUTx-0/1.

Table 19. LVCMOS Clock Output DC Characteristics [1][2][3]

1. Applies to any of OUT3-0, OUT3-1, OUT2-0, OUT2-1, OUT1-0, OUT1-1, OUT0-0, OUT0-1.
2. Output voltages compliant with JESD8-7A, Normal Range.

Table 18. Differential Clock Output DC Characteristics [1][2][3] (Cont.)

R31DS0136EU0102 Rev.1.02 Page 30 Dec 6, 2024 RC32508A Datasheet 5. Applications Information

5.1 Recommendations for Unused Input and Output Pins

5.1.1 Inputs

5.1.1.1 CLKx / nCLKx Input

For applications that do not require the use of the reference clock input, both CLK and nCLK should be left floating. If the CLK/nCLK input is connected but not used by the device, it is recommended that CLK and nCLK not be driven with active signals.

5.1.1.2 LVCMOS Control Pins

LVCMOS control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.

5.1.2 Outputs

5.1.2.1 LVCMOS Outputs

Any LVCMOS output can be left floating if unused. There should be no trace attached. The mode of the output buffer should be set to tri-stated to avoid any noise being generated.

5.1.2.2 Differential Outputs

All unused differential outputs can be left floating. Renesas recommends that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

5.1.3 Power Connections

The power connections of the RC32508A can be grouped as shown if all members of the groups are using the same voltage level: ▪ VDDD-0/1 ▪ VDDA-0/1 ▪ VDDOx-0/1 (can share supplies if output frequencies are the same, otherwise keep separated to avoid spur coupling)

• If all outputs OUTx-0/1/nOUTx-0/1 associated with any particular VDDOx-0/1 pin are not used, the power pin can be left floating

5.2 Clock Input Interface

The RC32508A accepts both single-ended and differential inputs. For information on input terminations, see Quick Guide - Output Terminations (AN-953) located on the RC32508A product page. If you have additional questions on input types not covered in the application discussion, or if you require information about register programming sequences for changing the differential inputs to accept LVCMOS inputs levels, see Termination - AC Coupling Clock Receivers (AN-844) or contact Renesas technical support.

5.3 Overdriving the XTAL Interface

AC coupling capacitor. The XIN/REF-0/1 input is internally biased at 1V. The XOUT-0/1 pin can be left floating. interference with the power rail and to reduce internal noise. Figure 10. 1.8V LVCMOS Driver to XTAL Input Interface transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. Figure 11. LVCMOS Driver to XTAL Input Interface purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input.

Figure 12. LVPECL Driver to XTAL Input Interface

5.4 Wiring the Differential Input to Accept Single-Ended Levels

For information, see the Differential Input to Accept Single-ended Levels Application Note (AN-836).

5.5 Differential Output Termination

schemes are the same as normally used for an LVDS output type. close to the receiver as possible. Figure 13. AC Coupled LVDS Termination located on the device product page, or contact Renesas for support.

5.6 Power Considerations

For power and current consumption calculations, refer to Renesas’ Timing Commander tool.

6.1 VFQFPN ePad Thermal Release Path

between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. Electrically Enhance Lead frame Base Package, Amkor Technology. Figure 14. P .C. Assembly for Exposed Pad Thermal Release Path – Side View (Drawing not to Scale)

6.2 Thermal Characteristics

Table 20. Thermal Characteristics

1. Multi-Layer PCB with two ground and two voltage planes.
2. Assumes ePad is connected to a ground plane using a grid of 9x9 thermal vias.

R31DS0136EU0102 Rev.1.02 Page 34 Dec 6, 2024 RC32508A Datasheet 7. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see package links in Ordering Information). The package information is the most current data available and is subject to change without revision of this document. 8. Marking Diagram 9. Ordering Information 10. Revision History ▪ Lines 2 and 3 are the part number ▪ Line 4:

• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” indicates the mark code. Part Number Package MSL Rating Carrier Type Temperature Range RC32508AdddGNE#BB0[1] 1. Replace “ddd” with the desired pre-programmed configuration code provided by Renesas in response to a custom configuration request or use “000” for unprogrammed parts. 7 × 7 × 0.9 mm, 48-VFQFPN 3 Tray -40° to +85°C RC32508AdddGNE#KB0 Tape and Reel, Pin 1 Orientation: EIA-481-D Revision Date Description

1.02 Dec 6, 2024

▪ Changed VSS to GND throughout the document. ▪ In Table 1, in the description of EPAD, changed “Negative supply voltage” to “Ground supply voltage”. 1.01 Jan 8, 2024 Updated the typical values for CIN in Table 2. 1.00 Sep 23, 2022 Initial release.

(PCB Top View, NSMD Design) TOP VIEWBOTTOM VIEW SIDE VIEW 7.00 ±0.15 7.00 ±0.15 Pin 1 ID Seating Plane0.08C0.85 C(0.20)0.05 Max (0.275)0.500.20 0.40 5.65 ±0.15 5.65 ±0.15 0.24 ±0.06 148 12132425 3637 0.125 7.306.20 7.30 5.650.20 Package Outline0.250.50 5.65 © Renesas Electronics Corporation

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