RC32308

RC32312 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 34

Technical content

Datasheet sections

• 1.1 Pin Assignments
• 1.2 Pin Descriptions
• 2.1 Absolute Maximum Ratings
• 2.2 Thermal Resistance
• 2.3 Recommended Operating Conditions
• 2.4 APLL Phase Jitter
• 2.5 FOD Phase Jitter
• 2.6 Power Supply Noise Rejection
• 2.7 Crystal Oscillator Input and APLL AC/DC Electrical Characteristics
• 2.8 Recommended Crystal Characteristics
• 2.9 Clock Input (CLKIN/nCLKIN) AC/DC Characteristics
• 2.10 Output Frequencies and Start-Up Time
• 2.11 Phase and Frequency Uncertainty
• 2.12 Output-to-Output and Input-to-Output Skew
• 2.13 LVCMOS Output AC/DC Characteristics
• 2.14 LVDS Output AC/DC Characteristics
• 2.15 HCSL Output AC/DC Characteristics
• 2.16 Power Supply Current
• 2.17 GPIO and Serial Port DC Electrical Characteristics
• 2.18 CMOS GPIO and Serial Port Common Electrical Characteristics
• 2.19 I 2C Bus Target Timing Diagram
• 2.20 I 2C Bus Target Timing Characteristics
• 2.21 I 2C Bus AC/DC Electrical Characteristics
• 2.22 SPI Target Timing Diagrams
• 2.23 SPI Target Timing Characteristics
• 3.1 Overview
• 3.2 Device Frequency Reference
• 3.3 Analog PLL
• 3.4 Integer Output Dividers
• 3.5 Fractional Output Dividers
• 3.6 Divider Synchronization
• 3.7 Digital PLL
• 3.7.1 DPLL Free-run State
• 3.7.2 DPLL Acquire State
• 3.7.3 DPLL Normal State
• 3.7.4 DPLL Holdover State
• 3.7.5 DPLL Hitless Switch State
• 3.8 DPLL External Feedback
• 3.9 DPLL Reference Switching
• 3.9.1 Hitless Reference Switching
• 3.9.2 Aligned Reference Switching
• 3.10 Clock Output Enable
• 3.11 Reference Monitors
• 3.12 Status and Control
• 4.1 Power Considerations
• 4.2 Power-On Reset and Reset Controller
• 4.3 Recommendations for Unused Input and Output Pins
• 4.3.1 CLKIN/nCLKIN Pins

Features

▪ Jitter 25fs RMS, 12kHz to 20MHz with 4MHz HPF ▪ Output frequency range:

• 4kHz to 1GHz for differential outputs
• 4kHz to 250MHz for single-ended outputs ▪ Up to 12 HCSL (AC-LVPECL) or LVDS outputs with independent integer dividers; differential outputs can be configured as two single-ended outputs ▪ Up to four clock inputs that can each be configured as differential or as two single-ended inputs ▪ Input frequency range:
• 1kHz to 1GHz for differential inputs
• 1kHz to 250MHz for single-ended inputs ▪ Compliant to ITU-T G.8262 and G.8262.1 ▪ Hitless reference switching, manual or automatic ▪ DPLL input-to-output phase variation ≤ 500ps ▪ DCO frequency resolution < 10 -13 ▪ Factory programmable internal OTP ▪ RC32312
• 4 inputs and 12 outputs
• 9 × 9 mm, 64-VFQFPN ▪ RC32308
• 3 inputs and 8 outputs
• 7 × 7 mm, 48-VFQFPN ▪ Operating voltage: 1.8V
• Serial ports support 1.8V or 3.3V ▪ Operating temperature:
• -40°C to 85°C ambient
• -40°C to 105°C board

Figure 1. Typical Wireline Infrastructure Use Case

R31DS0128EU0116 Rev.1.16 Page 4 Nov 17, 2025 RC32312, RC32308 Datasheet

1.1 Pin Assignments

1.2 Pin Descriptions

Table 1. Pin Descriptions XIN 4 4 I Crystal oscillator / xCXO input. XOUT 5 5 O Crystal oscillator output. Clock reference input, differential pair / single-ended. CLKINx indicates the positive pin of a differential pair. nCLKINx indicates the negative pin of differential pair. Clock output, differential pair / single ended. LVDS, HCSL, or LVCMOS. OUTx indicates the positive pin of a differential pair. nOUTx indicates the negative pin of a differential pair.

Clock output, differential pair / single ended. LVDS, HCSL, or LVCMOS. OUTx indicates the positive pin of a differential pair. nOUTx indicates the negative pin of a differential pair. Clock output, differential pair / single ended. LVDS, HCSL, or LVCMOS. OUTx indicates the positive pin of a differential pair. nOUTx indicates the negative pin of a differential pair. nCS_A0 6 6 I I2C mode: address bit 0. SPI mode: active-low chip select. SCL_SCLK 17 15 I/O I 2C Mode: I2C interface bi-directional clock. SPI Mode: serial clock. directional serial data. SPI 4-wire mode: input serial data. General purpose input/output. VDD_VCO 1 1 Power Power supply for the VCO. 1.8V is supported. Power supply for digital core, digital in FODs, and digital in the APLL. 1.8V and 3.3V are supported. VDDD33_SERIAL 8 8 Power Power supply for serial port. 1.8V and 3.3V are supported. VDDO1_FOD0 56 - Power Power supply for OUT1/nOUT1, IOD1, and FOD0. 1.8V is supported. VDDO1 - 41 Power Power supply for OUT1/nOUT1 and IOD1. 1.8V is supported. VDD_FOD0 - 40 Power Power supply for FOD0. 1.8V is supported. Table 1. Pin Descriptions (Cont.)

VDDO2 55 - Power Power supply for OUT2/nOUT2 and IOD2. 1.8V is supported. VDDO3 50 37 Power Power supply for OUT3/nOUT3, IOD3, and GPIO5. 1.8V is supported. VDDO4 48 - Power Power supply for OUT4/nOUT4, IOD4, and GPIO6. 1.8V is supported. VDDO5 44 36 Power Power supply for OUT5/nOUT5, IOD5 and GPIO1. 1.8V is supported. VDDO6 37 29 Power Power supply for OUT6/nOUT6, IOD6, and GPIO2. 1.8V is supported. VDDO7 33 25 Power Power supply for OUT7/nOUT7, IOD7, and GPIO3. 1.8V is supported. VDDO8_FOD1 32 24 Power Power supply for OUT8/nOUT8, IOD8, and FOD1. 1.8V is supported. VDDO9 27 - Power Power supply for OUT9/nOUT9 and IOD9. 1.8V is supported. Power supply for OUT10/nOUT10, IOD10, FOD2, and FOD calibration. VDDO11 21 - Power Power supply for OUT11/nOUT11 and IOD11. 1.8V is supported. VDDXO_DCD 3 3 Power Power supply for the analog reference and the LOCK output. VSS ePad ePad Power Device ePad. Must be connected to ground. Table 2. Input Characteristics

2.1 Absolute Maximum Ratings

2.2 Thermal Resistance

Table 3. Absolute Maximum Ratings

1. This limit only applies when XIN is overdriven by an external oscillator. No limit is implied when connected directly to a crystal.
2. V DDOx refers to the supply powering the GPIO or nMR. For VDD pin mapping, see Pin Assignments.

Table 4. Thermal Resistance

2.3 Recommended Operating Conditions

2.4 APLL Phase Jitter

2.5 FOD Phase Jitter

Table 5. Recommended Operating Conditions[1][2]

1. All electrical characteristics are specified over Recommended Operating Conditions unless noted otherwise.
2. All conditions in this table must be met to guarantee device functionality and performance.

Table 6. APLL Phase Jitter[1][2][3][4]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Characterized using a Rohde and Schwarz SMA100 overdriving the crystal interface.
3. Measured after the APLL has locked and settled.
4. All outputs enabled and generating clocks with the same frequency sourced from the APLL via integer output dividers.
5. Measured after the DPLL has locked and settled using a jitter free and wander-free reference to the DPLL.

Table 7. FOD Phase Jitter[1][2][3][4]

2.6 Power Supply Noise Rejection

2.7 Crystal Oscillator Input and APLL AC/DC Electrical Characteristics

1. The device will meet specifications after thermal equilibrium has been reached.
2. Characterized using a Rohde and Schwarz SMA100 overdriving the crystal interface.
3. Measured after the APLL has locked and settled.
4. All outputs enabled and generating clocks with the same frequency sourced from the same FOD.
5. Measured after the DPLL has locked and settled using a jitter free and wander-free reference to the DPLL.

Table 8. Power Supply Noise Rejection[1]

1. The device will meet specifications after thermal equilibrium is reached.
2. 100mV peak-to-peak sine wave applied to any V DDO, excluding VDDO of the output being measured and excluding VDD_VCO.
3. Relative to 156.25MHz carrier frequency.
4. Measured on any differential output.

Table 9. Crystal Oscillator Input and Analog PLL AC/DC Characteristics

1. APLL configured with integer_mode = 0x1. Note this configuration does not permit the APLL to be steered by the DPLL/DCO.
2. APLL configured with integer_mode = 0x0, apll_fb_div_frac ≠ 0x0.
3. Capacitance increases by 0.25pF for each step of both xobuf_digicap_x1 and xobuf_digicap_x2.
4. F TOL refers to the frequency accuracy of the Device Frequency Reference, either a crystal connected between XIN and XOUT, or an oscillator

connected to XIN and overdriving the crystal interface. The APLL can reliably lock to a frequency reference that meets the FTOL limits.

1. Inclusive of initial tolerance at 25°C, temperature stability, and aging.

2.8 Recommended Crystal Characteristics

2.9 Clock Input (CLKIN/nCLKIN) AC/DC Characteristics

1. The APLL frequency steering range (±F STEER) available for a DPLL or DCO to digitally steer the APLL is determined by the following expression:

Device Frequency Reference is ±100PPM. then the APLL frequency steering range will be ±350PPM.

1. The frequency accuracy of the device frequency reference should be chosen to meet the free-running frequency requirements of the application,

information, see Device Frequency Reference. Table 10. Recommended Crystal Characteristics

1. Specified by the crystal manufacturer.
2. Refers to power delivered by the oscillator circuit and dissipated in the crystal. The crystal must tolerate this drive level.

Table 11. Clock Input (CLKIN/nCLKIN) AC/DC Characteristics

1. Common mode is defined as the cross-point.
2. Internal input dividers can be used to reduce the CLKIN/nCLKIN frequency to be within the valid range.

2.10 Output Frequencies and Start-Up Time

2.11 Phase and Frequency Uncertainty

Table 12. Output Frequencies and Start-Up Time

1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output. A stable clock is defined

needed to load a configuration from internal OTP.

1. Start-up time will depend on the actual configuration used. For more information, please contact Renesas Technical Support.

Table 13. Phase and Frequency Uncertainty[1][2]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Measured after the DPLL has locked and settled using a jitter free and wander-free reference.

2.12 Output-to-Output and Input-to-Output Skew

2.13 LVCMOS Output AC/DC Characteristics

Table 14. Output-to-Output and Input-to-Output Skew[1][2][3]

1. The device will meet specifications after thermal equilibrium has been reached.
2. Output bank 1 refers to OUT[3:0], output bank 2 refers to OUT[7:4], and output bank 3 refers to OUT[11:8].
3. Measured across the full operating temperature range.
4. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
5. This parameter is defined in accordance with JEDEC Standard 65.
6. Input-to-output delay is defined as the time between the rising edge of a reference clock at CLKINx and the associated rising edge of an output

reference input dividers must be bypassed.

1. Measured after the DPLL has locked and settled using a jitter free and wander-free reference to the DPLL.

Table 15. LVCMOS Output AC/DC Characteristics[1]

1. Measured with outputs terminated with 50Ω to V DDO/2.
2. These values are compliant with JESD8-7A.

2.14 LVDS Output AC/DC Characteristics

2.15 HCSL Output AC/DC Characteristics

Table 16. LVDS Output AC/DC Characteristics[1]

1. Outputs terminated with 100Ω across OUTx and nOUTx.
2. Single-ended measurement.

Table 17. HCSL Output AC/DC Characteristics[1]

1. Outputs terminated with 50Ω to GND on each OUTx and nOUTx pin.
2. Peak-to-peak output voltage swing on each OUTx and nOUTx pin.

2.16 Power Supply Current

Table 18. Power Supply Current[1] Current adder with FOD at 120MHz.

2.17 GPIO and Serial Port DC Electrical Characteristics

2.18 CMOS GPIO and Serial Port Common Electrical Characteristics

1. Internal dynamic switching current at maximum f OUT is included, unless otherwise noted.
2. Added to supply current for VDDO1_FOD0, VDD_FOD0, VDDO8_FOD1, VDDO9_FOD2, VDDO10_FOD2 according to the conditions for the FOD
3. Values do not include I DD_FODxADD.
4. OUT[11:0] are powered down by setting: out_en_bias = 0x0, out_dis_state = 0x3, and out_driver_en = 0x0.
5. IOD[3:0] and IOD[11:8] are powered down by setting: iod_apll_vco_fanout_en = 0x0, iod_mux_sel = 0x7, and iod_enable = 0x0.
6. IOD[7:4] are powered down by setting: iod_apll_vco_fanout_en = 0x0 and iod_enable = 0x0.

Table 19. GPIO and Serial Port DC Electrical Characteristics[1][2][3][4]

1. Applies to GPIOx, nMR, nCS_A0, SCL_SCLK, SCA_SDIO, and SDO_A1.
2. Input specifications refer to pins acting as inputs, output specifications refer to pins acting as outputs.
3. V DDx refers to the VDDOx or VDDD33_SERIAL supply powering the GPIO or serial port (see Pin Assignments).
4. Values are compliant with JESD8-7A.

Table 20. CMOS GPIO Common Electrical Characteristics[1][2][3]

1. Applies to GPIOx, nMR, nCS_A0, SCL_SCLK, SCA_SDIO, and SDO_A1.
2. Input specifications refer to pins acting as inputs, output specifications refer to pins acting as outputs.
3. V DDx refers to the VDDOx or VDDD33_SERIAL supply powering the GPIO or serial port (see Pin Assignments).

up/pull-down resistor current. Table 18. Power Supply Current[1] (Cont.)

2.19 I 2C Bus Target Timing Diagram

Figure 4. I2C Bus Target Timing Diagram

2.20 I 2C Bus Target Timing Characteristics

2.21 I 2C Bus AC/DC Electrical Characteristics

Table 21. I2C Bus Target Timing Characteristics

1. Device rejects noise spikes of a duration up to the maximum specified value.

Table 22. I2C Bus AC/DC Electrical Characteristics [1]

1. VOH is governed by the VPUP, the voltage rail to which the pull-up resistors are connected.
2. See CMOS GPI/GPIO Common Electrical Characteristics in Table 20.

2.22 SPI Target Timing Diagrams

Figure 5. SPI Target Timing Diagrams

2.23 SPI Target Timing Characteristics

Table 23. SPI Target Timing Characteristics

1. This is the time until the device releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength and PCB trace

R31DS0128EU0116 Rev.1.16 Page 21 Nov 17, 2025 RC32312, RC32308 Datasheet 3. Functional Description

3.1 Overview

The RC32312/RC32308 is an ultra-low phase noise jitter attenuator, multi-frequency synthesizer, synchronous Ethernet synchronizer, and digitally controlled oscillator (DCO). This flexible, low-power device outputs clocks with 50fs RMS (12kHz to 20MHz) jitter supporting SerDes operating at rates up to 112Gbps and 25fs RMS (12kHz to 20MHz with 4MHz high pass filter) supporting SerDes operating at 224Gbps. The RC32312 has four differential clock inputs and 12 differential clock outputs, see Figure 2. The RC32308 has three differential clock inputs and eight differential clock outputs, see Figure 3. Both devices provide a digital PLL (DPLL) with an ultra-low phase noise analog PLL (APLL) based clock synthesizer and three fractional output divider (FOD) based clock synthesizers. The differential clock inputs can each be configured as two single-ended inputs. The clock inputs can operate at frequencies up to 1GHz for differential and 250MHz for single-ended. The differential outputs can be configured as LVDS or HCSL (AC-LVPECL). When configured for LVDS or HCSL (AC-LVPECL), the differential outputs can operate at frequencies up to 1GHz. Each differential output can be configured as two LVCMOS outputs that can operate at frequencies up to 250MHz.

3.2 Device Frequency Reference

The RC32312, RC32308 requires a device frequency reference. The frequency reference must support the phase noise, frequency accuracy, and frequency stability requirements of the intended application. The frequency reference can be implemented using an external crystal resonator connected between the XIN and XOUT pins and the device oscillator circuitry. Alternatively, an external oscillator can be connected to the XIN pin to overdrive the internal oscillator circuitry. If a crystal resonator is used for the frequency reference, the resonant frequency must be from 25MHz to 80MHz. If an external oscillator is used, it must provide a low-phase noise clock with frequency from 25MHz to 150MHz. For frequency reference requirements, see Table 9 and Table 10. For all applications, the phase noise of the frequency reference, after filtering by the APLL, is the minimum phase noise that will appear on all clocks output by the device. For DPLL applications, the accuracy of the frequency reference determines the frequency accuracy of the reference monitors and free-running clocks. The stability of the frequency reference determines the holdover stability of the DPLL and it affects the lowest filtering bandwidth the DPLL can support. For DCO and synthesizer applications, the accuracy of the frequency reference determines the frequency accuracy of the free-running clocks. For DCO applications, the stability of the frequency reference determines the stability of the DCO clocks when a source of synchronization is not available, and it affects the lowest filtering bandwidth that a filtering algorithm can support. The accuracy of the frequency reference should be chosen to meet the free-running frequency accuracy requirements of the application (see Table 24 for examples) and to allow sufficient APLL frequency steering range for a DPLL or DCO to lock the APLL to its reference and to track reference noise. The available APLL frequency steering range (±FSTEER) is determined by the following expression: FSTEER = |FTOL| - |FACC|; where FACC is the accuracy of the frequency reference. For the value of FTOL and for additional details, see Table 9.

3.3 Analog PLL

frequency between 9.70GHz and 10.75GHz. term frequency accuracy as the reference. undivided APLL clock is supplied to FOD[2:0].

3.4 Integer Output Dividers

Each IOD divides its input clock by a programmable 21-bit integer value.

3.5 Fractional Output Dividers

that their output frequencies are virtually unaffected by the DPLL.

3.6 Divider Synchronization

divide ratios along the paths from the APLL to the divider outputs. Table 24. Recommended Free-Running Frequency Accuracy by Application

R31DS0128EU0116 Rev.1.16 Page 23 Nov 17, 2025 RC32312, RC32308 Datasheet other words, the 1kHz reference, the 8kHz and the 125MHz clocks will be aligned for every edge of the 1kHz input reference (excluding the effects of reference noise and DPLL filtering).

3.7 Digital PLL

Up to four of the clock inputs can be selected as inputs for the reference monitors and the DPLL reference selection multiplexer. The DPLL can lock to reference frequencies between 1kHz and 33MHz; clock inputs with frequencies above 33MHz must be divided using the internal reference dividers. The DPLL steers the APLL using digital frequency control words via the Combo Bus. The DPLL supports programmable filtering bandwidths between 0.05Hz and 1kHz. The DPLL operates in five states: Free-run, Acquire, Normal, Holdover, and Hitless Switch. In DCO mode, the DPLL does not lock to an input reference and its frequency is steered by external software instead.

3.7.1 DPLL Free-run State

In the Free-run state, the DPLL does not generate frequency control words and the APLL synthesizes clocks based on the frequency reference.

3.7.2 DPLL Acquire State

In the Acquire state, the DPLL tracks the selected qualified reference with the acquisition bandwidth and damping factor settings until the DPLL declares lock. The acquisition bandwidth and damping factor can be configured to accelerate the locking process. When the DPLL achieves lock it automatically transitions to the Normal state.

3.7.3 DPLL Normal State

In the Normal state, the DPLL tracks the selected reference with the normal locking bandwidth and damping factor settings. The normal bandwidth and damping factor can be configured to meet the filtering requirements of the intended application. In the Normal state the long-term FFO of the APLL output clocks is the same as the long- term FFO of the reference and no phase slips will occur.

3.7.4 DPLL Holdover State

In the Holdover state, the DPLL outputs digital frequency control words based on data acquired while in the Normal state so that the APLL outputs an accurate frequency when a reference is not provided to the DPLL. While the DPLL is in the Holdover state, the APLL generates clocks based on the frequency reference and DPLL holdover data.

3.7.5 DPLL Hitless Switch State

In the Hitless Switch state, the DPLL enters Holdover and measures the phase offset between the selected reference and the DPLL feedback clock. The measured phase offset is stored by the DPLL and is used to minimize the phase transient at the output of the DPLL when it locks to the new reference.

3.8 DPLL External Feedback

In some applications it is useful to use an external feedback path from the APLL to the DPLL. The DPLL reference selection multiplexer can select one of the external references for use as the feedback clock for the DPLL. When external feedback is used, the feedback clock must have the same frequency as the selected DPLL reference.

3.9 DPLL Reference Switching

The active reference for the DPLL is determined by forced selection or by automatic selection based on user- programmed priorities, locking allowances, reference monitors, revertive and non-revertive settings, and GPIO LOS inputs. The DPLL will act to close phase differences between the selected reference and the feedback clock. A step change in the phase difference can occur when a new reference is selected while the DPLL is in the Acquire state

R31DS0128EU0116 Rev.1.16 Page 24 Nov 17, 2025 RC32312, RC32308 Datasheet or the Normal state; or when the DPLL exits the Holdover state and enters the Acquire state. The resulting phase transient is filtered by the DPLL loop filter and the phase slope limiter; and there will not be any sudden phase steps or glitches on the device outputs.

3.9.1 Hitless Reference Switching

Hitless reference switching causes the DPLL to ignore the phase difference between the newly selected reference and the DPLL feedback clock; the DPLL will track the FFO of the newly selected reference. When hitless reference switching is enabled – and the DPLL is the Acquire state or the Normal state, and the selected reference is changed – the DPLL enters the Holdover state and measures the phase offset between the newly selected reference and the DPLL feedback clock. The measured phase offset is stored and is subtracted from later phase offsets measured by the DPLL phase detector. The DPLL then enters the Acquire state. When the DPLL is in the Holdover state due to a reference failure or any other reason, hitless reference switching can be used when entering the Acquire state.

3.9.2 Aligned Reference Switching

Hitless reference switching does not allow a deterministic phase relationship to exist between the DPLL reference and its output clocks. When a deterministic phase relationship is needed, hitless reference switching should not be enabled so that the DPLL can align its output clocks with the DPLL reference.

3.10 Clock Output Enable

The RC32312, RC32308 enables and disables clock outputs synchronously to ensure there are no runt pulses during clock output enable and disable operations. Clock output enables can be controlled by software using the global_oe and out_driver_en register fields. Alternatively, GPIOs can be assigned the clock output enable function using the oe_source_sel and gpio_func register fields. For more information, see the RC32312, RC32308 Programming Guide. When a GPIO is assigned an output enable function it should be configured with gpio_resync = 0x0 and gpio_deglitch_bypass = 0x1; this disables GPIO resynchronization and bypasses the GPIO deglitcher ensuring lowest latency. When so configured, the maximum time delay from the time the voltage level on a GPIO input changes state until the clock output is enabled or disabled is 14ns plus 4 periods of the output clock.

3.11 Reference Monitors

The references can be continually monitored for loss of signal and for frequency offset per user programmed thresholds.

3.12 Status and Control

All control and status registers are accessed through a 1MHz I2C or 20MHz SPI target microprocessor interface. The device can automatically load a configuration from internal one time programmable (OTP) memory. Alternatively, the I2C controller interface can automatically load a configuration from an external EEPROM after reset. Note: For registers information, contact Renesas Technical Support.

4.1 Power Considerations

For power and current consumption calculations, see the Renesas IC Toolbox (RICBox) software tool.

4.2 Power-On Reset and Reset Controller

asserted and the voltage level on the nMR pin is high. minimum VIH and maximum VIL (see Table 19). Figure 6. Controller Reset Sequence Initiation out_startup register field. Disabled outputs behave according to the associated out_dis_state register field. to indicate the state of the device_ready_sts register bit by setting the associated gpio_func register field to 0x18. When a reset sequence completes, the rst_done_sts register bit is set to 0x1.

1 Uncertain

the device_ready_sts register bit is set to 0x1.

4.3 Recommendations for Unused Input and Output Pins

4.3.1 CLKIN/nCLKIN Pins

connected but not used should not be driven with active signals.

4.3.2 LVCMOS Control Pins

4.3.3 LVCMOS Output Pins

LVCMOS outputs should be configured to a high-impedance state to prevent noise generation.

4.3.4 Differential Output Pins

sides of a differential output pair should be either left to float or terminated.

4.4 Overdriving the Crystal Interface

should not be less than 0.6V/ns. XIN is below 1.2V peak-to-peak. Figure 7. LVCMOS Driver to Crystal Input Interface Figure 8 shows one side of an LVPECL driver overdriving the XIN pin.

Figure 8. LVPECL Driver to Crystal Input Interface

4.5 Differential Output Termination

than HCSL or LVDS can be AC-coupled. Figure 9. The value of resistors RO1 and RO2 is 50Ω. Figure 9. Internal Termination Resistors for Differential Drivers components shown in this section are needed.

4.5.1 Direct-Coupled HCSL Terminations

be direct-coupled. The RC32312, RC32308 supports a wide range of programmable HCSL voltage swing options. Figure 10 shows an HCSL driver direct-coupled with an HCSL receiver and configured for internal termination. The RC32312, RC32308 supports source termination, with internal 50Ω resistors to ground at the transmitter. the receiver by 50% – this can be mitigated by adjusting the output amplitude of the driver.

Figure 10. HCSL Internal Termination by 50% – this can be mitigated by adjusting the output amplitude of the driver. Figure 11. HCSL External Termination RC32312/RC32308 product page, or contact Renesas for support.

4.5.2 Direct-Coupled LVDS Termination

mounted and placed as close to the receiver as practical. RC32312/RC32308 product page, or contact Renesas for support. Figure 12. LVDS Termination

4.5.3 AC-Coupled Differential Termination

RC32308 supports several programmable HCSL voltage swing options. receiver by 50%; this can be mitigated by adjusting the output amplitude of the driver. Figure 13. AC-Coupled Differential Termination For more information on AC-coupling, see Renesas application note AN-953, Quick Guide - Output Terminations.

4.5.4 AC-Coupled LVPECL (AC-LVPECL) Termination

termination scheme. Consult receiver specifications for input swing and bias requirements. termination resistors and biasing. Figure 14. AC-LVPECL Termination for LVPECL Receiver with Internal Termination Resistors and Biasing For more information on AC-coupling, see Renesas application note AN-953, Quick Guide - Output Terminations.

R31DS0128EU0116 Rev.1.16 Page 30 Nov 17, 2025 RC32312, RC32308 Datasheet 5. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 6. Device ID Register 7. Marking Diagram 8. Ordering Information Device Device_ID (Base Address 0x02) RC32308 0xC5C1 RC32312 0xC5C2 ▪ Lines 1 and 2 are the part number. ▪ Line 3:

• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. ▪ Lines 1 and 2 are the part number. ▪ Line 3:
• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. Part Number [1] 1. Replace “xxx” in the part number with the desired preprogrammed configuration code provided by Renesas in response to a custom configuration request. Description Package Description Carrier Type Temp. Range RC32308A000GNE#KB0 8-output unprogrammed part 48-VFQFPN, 7 × 7 mm Tape -40 to +85°C RC32308A000GNE#BB0 Tray RC32308A001GNE#KB0 8-output unprogrammed part for use with EEPROM (Datasheet Addendum and RBS) Tape -40 to +85°C RC32308A001GNE#BB0 Tray RC32308AxxxGNE#KB0 8-output preprogrammed part Tape -40 to +85°C RC32308AxxxGNE#BB0 Tray RC32312A000GN1#KB0 12-output unprogrammed part 64-VFQFPN, 9 × 9 mm Tape -40 to +85°C RC32312A000GN1#BB0 Tray RC32312A002GN1#KB0 12-output unprogrammed part for use with EEPROM (Datasheet Addendum and RBS) Tape -40 to +85°C RC32312A002GN1#BB0 Tray RC32312AxxxGN1#KB0 12-output preprogrammed part Tape -40 to +85°C RC32312AxxxGN1#BB0 Tray

R31DS0128EU0116 Rev.1.16 Page 31 Nov 17, 2025 RC32312, RC32308 Datasheet 9. Revision History Revision Date Description

1.16 Nov 17, 2025

▪ Updated the HCSL minimum and maximum values in Table 17 ▪ Clarified the use of nMR in power sequencing in Power Considerations ▪ Updated Ordering Information

1.15 Sep 24, 2025

▪ Fixed a pin typo – changed RC32308 pin 15 to SCL_SCLK in Pin Assignments ▪ Changed GND to V SS in Pin Assignments ▪ Changed use of master/slave terminology to controller/target

1.14 Dec 19, 2024 ▪ Changed the maximum time delay number in Clock Output Enable to 14ns from 13ns

1.13 Dec 13, 2024 ▪ Added Clock Output Enable

1.12 Oct 11, 2024 ▪ Updated footnote 2 in Table 16

▪ Complete other minor changes

1.11 Aug 27, 2024

▪ Updated the minimum and maximum values for “Load Capacitance” in Table 10. Also added a footnote to the parameter. ▪ Updated the footnote associated with “Drive Level” in Table 10 1.10 Jul 9, 2024 ▪ Updated Table 23.

1.09 Jul 5, 2024

▪ Updated the description of V DDO9_FOD2 and VDDO10_FOD2 in Table 1 ▪ Updated the following specification tables: Table 9, Table 10, Table 17, Table 18, Table 21, and Table 23 ▪ Updated Device Frequency Reference ▪ Updated AC-Coupled Differential Termination ▪ Added AC-Coupled LVPECL (AC-LVPECL) Termination. ▪ Completed other minor changes

1.08 May 17, 2024 ▪ Updated the nMR, nCS_A0, SCL_SCLK, SDA_SDIO, and SDO_A1 pins in Table 1

▪ Updated Table 19 and Table 20

1.07 Apr 5, 2024 ▪ Completed minor changes

1.06 Mar 28, 2024 ▪ Updated Figure 3 and Figure 5

1.05 Mar 15, 2024

▪ Updated the nMR, nCS_A0, SCL_SCLK, SDA_SDIO and SDO_A1 pins in Table 1 ▪ Updated footnote 1 in Table 20 ▪ Updated Power-On Reset and Reset Controller ▪ Updated footnotes 3 and 4 and added footnote 5 in Table 18 ▪ Moved Soft Reset section to the RC32312, RC32308 Programming Guide ▪ Completed other minor changes

1.04 Feb 28, 2024

▪ Updated the description of the LOCK pin in Table 1 ▪ Updated the frequency tolerance values in Table 10 ▪ Updated footnotes 1 and 2 in Table 17 ▪ Updated Power Considerations ▪ Added two new sections, Power-On Reset and Reset Controller and Soft Reset ▪ Updated the slew rate in Overdriving the Crystal Interface

1.03 Jan 22, 2024 ▪ Updated Table 5 and Table 18

▪ Updated the second paragraph of Overdriving the Crystal Interface

1.02 Dec 6, 2023 ▪ Updated Table 9 and Table 10

▪ Updated the second paragraph of Overdriving the Crystal Interface

1.01 Nov 21, 2023

▪ Updated the footnotes in Table 6 ▪ Reformatted Table 7 and updated its footnotes ▪ Updated the footnotes in Table 8 ▪ Separated Table 9 into Table 9 and Table 10 ▪ Updated Table 11 and its footnotes ▪ Updated the footnotes in Table 12 to Table 14 ▪ Updated Table 15 to Table 18 and their footnotes

1.00 Oct 20, 2023 Initial release

(PCB Top View, NSMD Design) TOP VIEWBOTTOM VIEW SIDE VIEW 7.00 ±0.15 7.00 ±0.15 Pin 1 ID Seating Plane0.08C0.85 C(0.20)0.05 Max (0.275)0.500.20 0.40 5.65 ±0.15 5.65 ±0.15 0.24 ±0.06 148 12132425 3637 0.125 7.306.20 7.30 5.650.20 Package Outline0.250.50 5.65 © Renesas Electronics Corporation

TOP VIEWBOTTOM VIEW2x0.15C0.15C SIDE VIEW64x0.10C0.08C Seating Plane 9.00A 9.00 BIndex Area (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN 0.20 RefC0.00 ~ 0.05 0.90 ±0.10 9.308.200.250.55 9.308.200.25 0.500.55 C0.356.15 6.15C0.114 Package Outline 16173233 6.256.00 6.256.00 C0.114 (8x) 0.50C0.35 0.50 © Renesas Electronics Corporation

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