RC32012A

RC32012A RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 Block Diagram
• 1.2 Typical Application
• 2.1 Pin Assignments
• 2.2 Pin Descriptions
• 2.3 Pin Characteristics
• 3.1 Abbreviations Used
• 3.2 Absolute Maximum Ratings
• 3.3 Recommended Operating Conditions
• 3.4 Supply Voltage Characteristics
• 3.5 DC Electrical Characteristics
• 3.6 AC Electrical Characteristics
• 4.1 Clock Generator Mode
• 4.2 Jitter Attenuator or Synchronizer Mode
• 4.3 Power-Up, Configuration and Serial Interfaces
• 4.4 Input Clocks
• 4.4.1 Crystal/Oscillator Input
• 4.4.2 XO_DPLL Input
• 4.4.3 Reference Clock Inputs
• 4.5 Clock Input Monitors
• 4.6 Clock Input Monitor
• 4.7 APLL
• 4.7.1 APLL Lock Detector
• 4.8 System DPLL
• 4.9 DPLL
• 4.10 DPLL Operating Modes
• 4.10.1 Free-Run Mode
• 4.10.2 Locked Mode
• 4.10.3 Holdover Mode
• 4.10.4 Manual Holdover Mode
• 4.11 DPLL Input Clock Qualification and Selection
• 4.11.1 Automatic Input Clock Selection
• 4.11.2 Manual Input Clock Selection via Register or GPIO
• 4.11.3 Slave or GPIO Slave Selection
• 4.12 DPLL Switchover Management
• 4.12.1 Revertive and Non-Revertive Switching
• 4.12.2 Hitless Reference Switching
• 4.12.3 Phase Slope Limiting
• 4.12.4 DPLL Frequency Offset Limit Setting
• 4.12.5 DPLL Fast Lock Operation
• 4.13 Digitally-Controlled Oscillator Operation via External Control
• 4.13.1 Write-Frequency Mode
• 4.13.2 Increment / Decrement Registers and Pins

Features

▪ Can be configured as clock generator or jitter attenuator/synchronizer ▪ Low power, less than 1.2W typical ▪ Low jitter, less than 100 fs-RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter ▪ PCIe Gen 1-6 CC, SRIS and SRNS support ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ Up to four fractional output dividers and 12 integer output dividers

• Each fractional output divider can be slaved with DPLL or SYS-DPLL or free-run locked to APLL ▪ DPLL can be configured as DCO and each fractional output divider can be configured as NCO or DCO ▪ Combo bus allows frequency sharing between DPLL, System DPLL, and each of the four fractional output dividers ▪ LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL, HSTL output modes supported with programmable output swing and common mode voltage ▪ JESD204B/C support on differential or single ended outputs with DC-coupling or AC-coupling ▪ Up to seven single-ended or two differential clock inputs, one crystal/XO input, and one XO/TCXO/OCXO input ▪ Up to nine GPIO pins programmable to device select or system monitor options ▪ Supports 1MHz I2C, 400kHz SMBus, or 50MHz SPI serial port ▪ Internal non-volatile memory (up to 16 different configurations), or external serial I2C EEPROM provide default device settings on power-up. output operation ▪ -40° to +85°C industrial temperature operation RC32012A FemtoClock Jitter Attenuator and Clock Generator

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R31DS0078EU0103 Rev.1.03 Page 4 Sep 15, 2022 RC32012A Datasheet

1.1 Block Diagram

Figure 1. Block Diagram

1.2 Typical Application

Figure 2. Switch Line Card Use Case Figure 3. Switch Fabric Card Use Case

2.1 Pin Assignments[1]

2.2 Pin Descriptions

software compatibility with other members of the family of devices. Table 1. Pin Descriptions [1] fundamental mode parallel-resonant crystal.

3 VDDA_PDCP_XTAL Power Analog power supply voltage for System Analog PLL’s phase

4 VDDA_FB Power Analog power supply voltage for System Analog PLL’s feedback

2.5V, or 3.3V as appropriate for the input clock swing. 7 XO_DPLL Input Single-ended crystal oscillator input for System Digital PLL.

8 CLK0 Input Pull-down Positive input for differential input Clock 0 or single-ended input for

10 CLK1 Input Pull-down Positive input for differential input Clock 1 or single-ended input for

16 VDD_DIG Power Power supply for digital logic. 1.2V or 1.8V supported. I2C Master Operation. External pull-up recommended in I2C mode. optionally as an Address Bit 0 select input in I2C mode.

24 VDDA_LC_BG Power Analog power supply voltage for System Analog PLL’s LC Resonator

26 GPIO[3] I/O Pull-up [3] General Purpose Input / Output 3. 27 nQ11 Output Q11 clock negative output. 28 Q11 Output Q11 clock positive output. Table 1. Pin Descriptions [1] (Cont.)

powers FOD_2 and FOD_7. 1.8V supply required. 32 Q7 Output Q7 clock positive output. 33 nQ7 Output Q7 clock negative output. 34 GPIO[9] I/O Pull-up [3] General Purpose Input / Output 9. 35 nQ6 Output Q6 clock negative output. 36 Q6 Output Q6 clock positive output. 39 Q5 Output Q5 clock positive output. 40 nQ5 Output Q5 clock negative output. 42 Q4 Output Q4 clock positive output. 43 nQ4 Output Q4 clock negative output. 45 Q10 Output Q10 clock positive output. 46 nQ10 Output Q10 clock negative output. 47 GPIO[2] I/O Pull-up [3] General Purpose Input / Output 2.

48 VDD_GPIO_FOD Power Combined Power Supply input for all the digital pins, including GPIO

pins and serial ports pins as well as FOD_5. Only 1.8V supported. 49 GPIO[1] I/O Pull-up [3] General Purpose Input / Output 1. 50 nQ9 Output Q9 clock negative output. 51 Q9 Output Q9 clock positive output. 53 nQ3 Output Q3 clock negative output. 54 Q3 Output Q3 clock positive output. 56 GPIO[5] I/O Pull-up [3] General Purpose Input / Output 5. 57 nQ2 Output Q2 clock negative output. 58 Q2 Output Q2 clock positive output. 61 Q1 Output Q1 clock positive output. 62 nQ1 Output Q1 clock negative output. 63 GPIO[4] I/O Pull-up [3] General Purpose Input / Output 4. 64 nQ0 Output Q0 clock negative output. 65 Q0 Output Q0 clock positive output.

2.3 Pin Characteristics

powers FOD_0. 1.8V supply required. 69 Q8 Output Q8 clock positive output. 70 nQ8 Output Q8 clock negative output. 71 GPIO[0] I/O Pull-up [3] General Purpose Input / Output 0.

72 CREG_XTAL Power Filter capacitor for voltage regulator for oscillator circuit associated

with OSCI / OSCO pins. Requires a 10F filter capacitor to ground. ePad VSS Power Device ePad must be connected to Ground.

1. Pull-up and pull-down refer to internal input resistors (see Table 2, Pin Characteristics, for typical values).
2. VDDA_PDCP_XTAL and VDDA_LC_BG can be driven with either 2.5V or 3.3V, however, both must use the same voltage level. Register
3. GPIO pins can be configured via EEPROM and/or OTP with a pull-up or a pull-down. Pull-up is the default configuration.
4. For voltages supported, see Clock Outputs.

Table 2. Pin Characteristics

1. VDDO_Qx denotes: VDDO_Q0, VDDO_Q1, VDDO_Q2, VDDO_Q3, VDDO_Q4, VDDO_Q5, VDDO_Q6, VDDO_Q7, VDDO_Q8, VDDO_Q9, VDDO_Q10, or
2. Output impedance values for the Qx / nQx outputs are provided in Table 26.

3.1 Abbreviations Used

abbreviations used and will be referred to in footnotes for the various other tables.

3.2 Absolute Maximum Ratings

implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3. Abbreviated Signal Names and the Detailed Signal Names Referenced by Them Table 4. Absolute Maximum Ratings

1. For information on the signals referenced by this abbreviation, see Table 3.
2. This limit only applies to the OSCI input when being over-driven by an external signal. No limit is implied when this is connected directly

3.3 Recommended Operating Conditions

3.4 Supply Voltage Characteristics

Table 5. Recommended Operating Conditions [1]

1. It is the user’s responsibility to ensure that device junction temperature remains below the maximum allowed.
2. Measured at solder connection to Printed Circuit Board on any signal, voltage, or ePad.

Table 6. Power Supply DC Characteristics[1][2]

1. Current consumption figures represent a worst-case consumption with all functions associated with the particular voltage supply being

support all possible register-based configurations for the device.

1. IDD_CLKx denotes the current consumed by the appropriate VDD_CLKx supply voltage.
2. Supports 2.5V +5% or 3.3V +5% operation, not a continuous range.
3. Supports 1.2V +5% or 1.8V +5% operation, not a continuous range.
4. IDD_DCO_Qx denotes the current consumed by the appropriate VDD_DCO_Qx supply voltage. This is the current consumption for each

supply, not the total for all VDD_DCO_Qx.

1. The IDD_GPIO_FOD current consumed is dependent on the number of FODs attached to the voltage rail that are supported and the

NumFOD is the number of FODs on that supply that are enabled. Note that only the base current is needed if all FODs are disabled.

1. The IDDA_DIA current consumed is dependent on the number of FODs attached to the voltage rail that are supported and the frequency

NumFOD is the number of FODs on that supply that are enabled. Note that only the base current is needed if all FODs are disabled.

1. VDDA_DIA_FOD_B consumes higher current than VDDA_DIA_FOD_A because it has some additional circuitry, besides the FODs on it.
2. For information on the signals referenced by this abbreviation, see Table 3.
3. Currents for the outputs are shown in Table 7 or Table 8 as appropriate for the mode the individual output is operating in.

Table 7. Output Supply Current (Output Configured as Differential) [1][2][3]

1. Output current consumption is not affected by any of the core device power supply voltage levels.
2. Internal dynamic switching current at maximum fOUT is included.
3. Refers to the output voltage (swing) setting programed into device registers for each output.
4. IDDO_Qx denotes the current consumed by each VDDO_Qx supply.
5. Measured with outputs unloaded.
6. For information on the signals referenced by this abbreviation, see Table 3.

3.5 DC Electrical Characteristics

Table 8. Output Supply Current (Output Configured as LVCMOS) [1][2][3]

1. Output current consumption is not affected by any of the core device power supply voltage levels.
2. Internal dynamic switching current at maximum fOUT is included.
3. Refers to the LVCMOS output drive strength (termination) setting programed into device registers for each output.
4. IDDO_Qx denotes the current consumed by each VDDO_Qx supply.
5. Measured with outputs unloaded.
6. For information on the signals referenced by this abbreviation, see Table 3.
7. Measured with outputs unloaded.

Table 9. LVCMOS/LVTTL DC Characteristics [1][2][3][4][5]

1. VIL should not be less than -0.3V.
2. When Output Q are configured as LVCMOS, their output characteristics are specified in Table 15.
3. Input pair used as two single-ended clocks rather than as a differential clock.

Table 10. Low-swing Mode Single-ended Input DC Characteristics[1][2][3][4][5]

1. VIL should not be less than -0.3V.
2. VIH should not be higher than VDD_CLK.
3. Input pair used as two single-ended clocks rather than a differential clock.
4. Input must be AC coupled.

Table 9. LVCMOS/LVTTL DC Characteristics [1][2][3][4][5] (Cont.)

Table 11. Differential Input DC Characteristics[1]

1. VIL should not be less than -0.3V.
2. VPP is the single-ended amplitude of the output signal. The differential specs is 2 * VPP.
3. Common mode voltage is defined as the cross-point.

0.1 VDD_CLK -

0.7 VDD_CLK

Table 12. Differential Output DC Characteristics (VDDO_Qx = 3.3V +5%, VSS = 0V, TA = -40°C to 85°C)[1][2][3][4]

1. For information on the signals referenced by this abbreviation, see Table 3.
2. Terminated with 100Ω across Qx and nQx.
3. If LVDS operation is desired, select SWING = 00 and CENTER = 001 or 010.
4. If LVPECL operation is desired, select SWING = 10 and CENTER = 101 or 110 for 3.3V LVPECL, and SWING = 10 and CENTER= 001

or 010 for 2.5V LVPECL operation.

1. VOVS is the single-ended amplitude of the output signal. The differential specs is 2 * VOVS.
2. Refers to the differential voltage swing setting programed into device registers for each output.
3. Not all VCMR selections can be supported with particular VDDO_Qx and VOVS settings.
4. Refers to the differential voltage crossing point (center voltage) setting programed into device registers for each output.

Table 13. Differential Output DC Characteristics (VDDO_Qx = 2.5V +5%, VSS = 0V, TA = -40°C to 85°C)[1][2][3][4]

1. For information on the signals referenced by this abbreviation, see Table 3.
2. Terminated with 100Ω across Qx and nQx.
3. If LVDS operation is desired, select SWING = 00 and CENTER = 001 or 010.

LVPECL levels cannot be generated.

1. VOVS is the single-ended amplitude of the output signal. The differential specs is 2 * VOVS.
2. Refers to the differential voltage swing setting programed into device registers for each output.
3. Not all VCMR selections can be supported with particular VDDO_Qx and VOVS settings.
4. Refers to the differential voltage crossing point (center voltage) setting programed into device registers for each output.

Table 14. Differential Output DC Characteristics (VDDO_Qx = 1.8V +5%, VSS = 0V, TA = -40°C to 85°C)[1][2][3]

1. For information on the signals referenced by this abbreviation, see Table 3.
2. Terminated with 100Ω across Qx and nQx.
3. If LVDS operation is desired, select SWING = 00 and CENTER = 010.
4. VOVS is the single-ended amplitude of the output signal. The differential specs is 2 * VOVS.

1. Refers to the differential voltage swing setting programed into device registers for each output.
2. Not all VCMR selections can be supported with particular VDDO_Qx and VOVS settings.
3. Refers to the differential voltage crossing point (center voltage) setting programed into device registers for each output.

Table 15. LVCMOS Clock Output DC Characteristics[1][2]

1. VDDO_Qx is used to refer to the appropriate VDDO_Qx power supply voltage for each output. For more information, see Table 3 and
2. This refers to the register settings for the LVCMOS output drive strength within the device.

Table 16. Input Frequency Characteristics[1]

1. For crystal characteristics, see Table 17.
2. Refer to Overdriving the XTAL Interface.
3. For information on the signals referenced by this abbreviation, see Table 3.
4. For proper device operation, the input frequency must be divided down to 150MHz or less (DPLL Phase Detector maximum frequency =
5. If the System DPLL needs to be driven with a higher frequency, one of the CLKx / nCLKx inputs can be routed via register settings to the

System DPLL instead of using XO_DPLL. Table 17. Crystal Characteristics[1]

3.6 AC Electrical Characteristics

Table 18. AC Characteristics[1][2]

differential mode when using internal loopback. Table 18. AC Characteristics[1][2] (Cont.)

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. VDDA_X refers to VDDA_PDCP, VDDA_XTAL, VDDA_LC, and VDDA_BG.
2. Long-term frequency error with respect to the DPLL input reference. The typical value shown assumes the DPLL has been phase-locked

holdover state on disqualification of the input reference.

1. This parameter will vary with the quality of the reference to the system DPLL. The typical value shown assumes an ideal reference used
2. This parameter will vary with the quality of the TDC and system DPLL references. The typical value shown assumes an ideal reference is

used as input to the TDC and system DPLL.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage
2. This parameter is defined in accordance with JEDEC Standard 65.
3. Measured at the differential cross points.
4. Measured at VDDO_Qx / 2.
5. Using LVCMOS with VDDO_Qx = 1.5V or 1.2V will result in much larger skews and is not recommended for skew-sensitive applications.
6. Banks are defined as a list of outputs driven by a specific FOD. Results do not apply if the output is driven by a different FOD.
7. This parameter is measured across the full operating temperature range and the difference between the slowest and fastest numbers is
8. Measured from the differential cross point of the input to the differential cross point of the associated output after device is locked and input

is stable. Measured using integer-related input and output frequencies.

1. Rise and fall times on differential outputs are independent of the power supply voltage on the output.
2. Measured with outputs terminated with 50Ω to GND.
3. For information on the signals referenced by this abbreviation, see Table 3.
4. Refers to the differential voltage swing setting programed into device registers for each output.
5. Measured with outputs terminated with 50Ω to VDDO_Qx / 2.
6. Refers to the LVCMOS output drive strength (termination) setting programed into device registers for each output.
7. This parameter has been characterized with FOUT = 50MHz.
8. Measured from the rising edge of nMR after all power supplies have reached > 80% of nominal voltage to the first stable clock edge on

no further perturbations in frequency expected.

1. At power-up, the nMR signal must be asserted for at least this period of time.
2. Start-up time will depend on the actual configuration used. For more information on estimating start-up time, contact Renesas technical
3. Noise spur amplitude measured relative to 156.25MHz carrier.
4. Typical PSNR values specified over the modulation frequency range of 10kHz to 1MHz.
5. Injected as sinusoidal noise to the specified power rail only.
6. 0.1uF capacitor placed on modulated power rail.

Table 19. Phase Jitter and Phase Noise

Figure 4. I2C Slave Timing Diagram Table 20. I2C Slave Timing

Figure 5. SPI Timing Diagram Table 21. SPI Timing

40 MHz

Figure 6. Input-Output Delay

1. Measurement performed approximately 1cm away from device pad. Observing at a greater distance on a heavily loaded trace may show

slower edge rates and longer delays. This is highly dependent on PCB loading.

1. Adding the extra half period of delay is a register programming option to emulate read data being clocked out on the opposite edge of the
2. This is the time until the RC32012A releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength and

Table 21. SPI Timing (Cont.)

Figure 9. Phase Noise of 312.5MHz Output in Jitter Attenuator Mode

R31DS0078EU0103 Rev.1.03 Page 31 Sep 15, 2022 RC32012A Datasheet 4. Functional Description The RC32012A is a fully integrated, low-power, high-performance frequency synthesizer with jitter attenuation and network synchronization capabilities. The device can be set up as either of the following: ▪ Clock generator, that is locked to the external crystal or oscillator and providing free-run clock outputs ▪ Jitter attenuator, that is locked to an external reference and providing low-jitter clock outputs when used with an external crystal or oscillator The device is optimized to deliver excellent phase noise as required for driving up to 28Gbps Ethernet PHYs, ASICs or FPGAs in 10G, 25G, 40G, 100G, 200G, or 400G switch line cards and switch fabric cards. The RC32012A supports JEDEC JESD204B/C for converter synchronization and SyncE for network-based synchronization.

4.1 Clock Generator Mode

The RC32012A can be set in Clock Generator mode by completing the following steps: 1. DPLL/DCO and System DPLL are powered down. 2. CLK0, CLK1 and GPIO0, GPIO3, GPIO9 are unused for reference clock inputs. 3. APLL is locked to external crystal or oscillator and provides high-frequency clocks to FOD_0, FOD_2, FOD_5, and FOD_7. 4. Free-run clock outputs are generated from FOD_0, FOD_2, FOD_5, or FOD_7, and each FOD can be independently set to integer or fractional divide values. Note: Up to four unrelated clock frequency domains can be achieved.

4.2 Jitter Attenuator or Synchronizer Mode

The RC32012A can be set in Jitter Attenuator or Synchronizer mode by completing the following steps: ▪ CLK0, CLK1 and GPIO0, GPIO3, GPIO9 are used for reference clock inputs. ▪ APLL is locked to external crystal or oscillator and provides high-frequency clocks to SYS_DPLL and FOD_0, FOD_2, FOD_5, FOD_7. ▪ System DPLL locks to external oscillator or TCXO or OCXO. ▪ DPLL/DCO uses FOD_0 to be synchronized and locked to the chosen reference clock input. ▪ Clock outputs, generated from synchronized DPLL/DCO, are generated from FOD_0 ▪ Clock outputs, generated from free-run APLL or from System DPLL or from synchronized DPLL/DCO, are generated from FOD_2, FOD_5, and FOD_7, which can be set to integer or fractional divider values Note: Up to four unrelated clock frequency domains can be achieved

4.3 Power-Up, Configuration and Serial Interfaces

The RC32012A can be powered up and configured in three ways: ▪ From internal non-volatile memory using OTP user configurations (UserCfgs) ▪ From its slave serial interface ▪ From an external I2C EEPROM The RC32012A supports three slave serial interfaces: I2C, SPI, and SMBUS, and one serial master interface (I2C). These interfaces share the same pins, so only one is available at a time. Additionally, all of the device GPIO pins are sampled at the rising edge of the nMR (master reset) signal and some of them can be used in setting the initial configuration.

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4.4 Input Clocks

The RC32012A supports one crystal/reference input that is used as a reference to the analog PLL (APLL). Up to two differential or seven single-ended clock inputs can be used as a reference to the digital PLL (DPLL) and support hitless reference switching. GPIO0, GPIO3, and GPIO9 can alternately be set as reference clock inputs in Jitter Attenuator mode.

4.4.1 Crystal/Oscillator Input

The crystal input supports crystal frequencies of 25MHz to 54MHz with a recommended load capacitance of 12pF. The crystal input can be over-driven with differential or single-ended inputs with proper external terminations. The supported frequency range is 25MHz to 62.5MHz when doubler logic for APLL is enabled, and 50Mz to 125MHz when doubler logic for APLL is disabled. An available LOS monitor detects the loss of signal on crystal input.

4.4.2 XO_DPLL Input

The XO_DPLL input supports frequencies of 1MHz to 150MHz when driven by an external oscillator, TCXO, or OCXO. An available LOS monitor detects the loss of signal on XO_DPLL input.

4.4.3 Reference Clock Inputs

There are two differential reference clock inputs that support differential or single-ended CMOS logic levels without external terminations. If set to single-ended type, each differential input turns into two single-ended inputs. Additionally, GPIO0, GPIO3, and GPIO9 can each be individually programmed to act as a single-ended input. Internal biasing is available for AC-coupled applications. The two clock inputs can be left floating when unused. An available LOS monitor detects the loss of signal on reference clock inputs.

4.5 Clock Input Monitors

There are two types of reference clock monitors: one to monitor the APLL input and the other to monitor the DPLL inputs. The APLL input is monitored for Loss of Signal (LOS). While the DPLL clock inputs (CLKIN0, CLKIN0B, CLKIN1, CLKIN1B, GPIO0, GPIO3, and GPIO9) each have LOS, activity and frequency monitoring. ▪ The LOS monitor detects missing edges over a window of several reference clock periods. For the best accuracy, it is recommended to program the window to be equal to at least eight times that of the measuring clock period. ▪ The frequency monitor can be configured to measure the reference over a nominal 5ms time window in order to achieve ~1ppm granularity. ▪ The frequency monitor can be configured to measure the reference over a nominal 0.4s time window in order to achieve ~12ppb granularity.

4.6 Clock Input Monitor

The APLL input is monitored for Loss of Signal (LOS). The LOS monitor detects missing edges over a window of several reference clock periods. For the best accuracy, it is recommended to program the window to be equal to at least eight times that of the measuring clock period.

4.7 APLL

The APLL is an integer LC-VCO based PLL with an operating range from 13.4GHz to 13.9GHz. The crystal or oscillator input clock is used to drive the APLL, and can be frequency doubled for increased performance. The APLL is temperature compensated for utmost frequency stability. The high-frequency clock output from the APLL is provided to each of the four fractional output dividers (FOD_0, FOD_2, FOD_5, FOD_7).

4.7.1 APLL Lock Detector

The APLL lock detector indicates whether the APLL is locked to a functioning crystal or reference input by monitoring the phase errors. Lock status is available on a GPIO pin or in the register map.

4.8 System DPLL

DPLL and with each of the four fractional output dividers (FOD_0, FOD_2, FOD_5, and FOD_7).

4.9 DPLL

feedback divider, which is comprised of 48-b numerator and 48-b denominator, is static during normal operation.

4.10 DPLL Operating Modes

is not connected directly to any output stages. One channel of the DPLL is shown in Figure 10. Figure 10. DPLL Channel

The DPLL operating mode operation can be set to automatic, forced locked, forced free-run and forced holdover. Figure 11. DPLL Automatic State Machine

1. Reset, the device enters Free-Run State
2. Once an input clock is qualified and it is selected: enter the LockAcq State
3. If the DPLL selected input clock is disqualified AND no qualified input clock is available: go back to Free-Run
4. DPLL switches to another qualified clock: remain in LockAcq State
5. The DPLL locks to the selected input clock: enter Locked State.
6. The DPLL selected input clock is disqualified AND No qualified input clock is available: enter Holdover State.
7. A qualified input clock is now available: enter LockRec State.
8. If the DPLL selected input clock is disqualified AND no qualified input clock is available: go back to Holdover
9. The DPLL switches to another qualified clock: enter LockRec State
10. The DPLL locks to the selected input clock: go to Locked State
11. The DPLL switches to another qualified clock: remain in LockRec State

or the device is set to Forced selection to another input clock.

R31DS0078EU0103 Rev.1.03 Page 35 Sep 15, 2022 RC32012A Datasheet

4.10.1 Free-Run Mode

In Free-Run mode the DPLL synthesizes clocks based on the system clock (crystal oscillator) and has no influence from a current or a previous input clock. Combo mode can be used with Free-Run mode. In that case the input clock of the combo master affects the combo slave's free-Run frequency.

4.10.2 Locked Mode

In Locked mode, the DPLL is synchronized to an input clock. The frequency and phase of the output clock track the DPLL selected input clock. The bandwidth (BW) and damping factor are programmable and are used by the DPLL when locked to an input reference. Table 22 includes some common BW settings and their associated applications.

4.10.3 Holdover Mode

If all the input clocks for a particular DPLL become invalid, then that DPLL will enter holdover state. In holdover mode, the DPLL uses stored frequency data acquired in Locked mode to control its output clocks. There are several programmable modes for the frequency offset acquisition method; it can use the frequency offset just before it entered holdover state (simple holdover), or a previously stored post-filtered frequency offset (advanced holdover). For the advanced holdover mode, the holdover value can be post filtered and is stored in two registers at a programmable rate while the DPLL is in locked state. When the DPLL enters the advanced holdover mode, the Table 22. DPLL Bandwidth

1. Values shown are the nominal loop bandwidths that will be provided by the DPLL. Data entry via registers

Description

92.6 m GR-253 stratum 3, SMC and G.8262 EEC-option 2 BW<0.1Hz 278 m 556 m 1.11 G.8262 EEC-option 1 1<BW<10, GR-1244 stratum 3 BW<3Hz 2.22 G.8262 EEC-option 1 1<BW<10, GR-1244 stratum 3 BW<3Hz 4.45 G.8262 EEC-option 1 1<BW<10 8.89 G.8262 EEC-option 1 1<BW<10 17.8 35.6 71.2 94.4 142 285 G.8251 (OTN) 333 571 11.4 k 12.1 k Jitter attenuators and Clock generators

updated is programmable between 0 and 63 s in steps of 1s. accurate values before being used. in holdover even if there are valid references available for the DPLL to lock to.

4.10.4 Manual Holdover Mode

the DPLL manual holdover value register bits under user control.

4.11 DPLL Input Clock Qualification and Selection

shown in Table 23. There is an independent reference selection process for the DPLL.

4.11.1 Automatic Input Clock Selection

valid, the priority of each input clock, and the input clock configuration. additional table allows several outputs to be placed in a group of equal priority.

4.11.2 Manual Input Clock Selection via Register or GPIO

case where there are other input clocks that are valid.

4.11.3 Slave or GPIO Slave Selection

GPIO input is used to tell this device that it is now the slave and to switch to and monitor the designated input only. Table 23. DPLL Reference Mode

0000 Automatic input clock selection

0001 Manual input clock selection

0010 GPIO

0011 Slave

0100 GPIO_Slave

4.12 DPLL Switchover Management

4.12.1 Revertive and Non-Revertive Switching

considered of equal priority).

4.12.2 Hitless Reference Switching

compensates for the measured phase offset resulting in minimal disruption to the phase of the DPLL output clock. reference switching can be enabled or disabled through register settings.

4.12.3 Phase Slope Limiting

to meet Telecom standards as shown in Table 24. Table 24. Some Key DPLL Phase-Slope Limits Supported

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4.12.4 DPLL Frequency Offset Limit Setting

Each DPLL has an independent setting to limit its maximum frequency range This setting is used in conjunction with the advanced reference monitoring to provide pull-in / hold-in limit enforcement as required in many telecom standards. It will also limit the frequency deviation during locking, during holdover and while performing switchovers. This limit must be set wide enough to cover the expected frequency range of the input when locking.

4.12.5 DPLL Fast Lock Operation

Each DPLL also has the ability to support a Fast Lock function. There are two options the user can choose from to perform the fast lock: ▪ Frequency Snap ▪ Phase Snap ▪ Open-loop phase pull-in (mutually exclusive with Phase Snap) ▪ Wide Acquisition Bandwidth Any of the options can be independently enabled or disabled, and selected to be applied when the DPLL is in either the LOCKACQ state or the LOCKREC state. Although the options are mutually exclusive, the order of precedence is as listed (with frequency snap being the highest). The frequency and phase snap options are recommended for locking to mid-kHz-range input clocks or lower. For frequency snap, the RC32012A will measure the input clock from the current DPLL operating frequency, determine an approximate frequency offset and digitally write that directly to the steerable FOD block, causing the output frequency to snap directly to the correct output frequency. The frequency snap can be optionally limited using a Frequency Slope Limit (FSL). For the phase snap and the open loop phase pull-in options, the measurement is used to determine the phase offset. With phase snap, the phase is snapped to the correct value; with open loop pull-in, the DPLL's PFD & LPF are temporarily isolated to allow for an unfiltered phase pull-in to the correct value. The combination of these methods will achieve lock very quickly, but there may be severe disruptions on the output clock while locking occurs; mainly due to the frequency/phase snaps. The wide acquisition bandwidth option uses the DPLL in a normal operating mode, but with temporary relaxation of items like DPLL loop bandwidth, phase slope limits (PSL) or damping factor until lock is achieved. At that point, the normal DPLL limits are resumed. The user is able to control what limits are to be applied. In addition, for LOCKACQ state only, the DPLL's bandwidth may be temporarily opened to its maximum for a short duration of time (in ms); with the temporary phase slope limit still being applied. This pre-acquisition option is applied before the wide acquisition bandwidth option. These methods are recommended for higher frequency signals since it results in fewer perturbations on the output clock. It also allows the user to trade-off the level of changes on the clock during the locking process versus the speed of locking.

4.13 Digitally-Controlled Oscillator Operation via External Control

The DPLL channel may be operated as an externally-controlled DCO. There are several different control methods that can be used depending on the application needs. Each is described individually in the following sub-sections. Phase and/or frequency updates will be calculated using external methods and written into the RC32012A over the serial port.

4.13.1 Write-Frequency Mode

this clock. The output will remain at this frequency until a new FCW is written. Figure 12. External DCO Control via Frequency Control Word extended to 48-bits to be written into the register. changing the frequency, the phase will move smoothly over time without any jumps.

4.13.2 Increment / Decrement Registers and Pins

1 FFO

4.13.3 Write-Phase Mode

limiting are programmable and will affect the output phase as it is adjusted. should not cause any issues, if properly configured, with devices receiving this clock. the “phase error”. This can be adjusted by external software. Figure 13. External DCO Control via Phase Control Word range of up to 65.535 seconds. moving the clock edges to the left as seen on an oscilloscope. A negative value will slow the output frequency.

4.13.4 Adjusting Phase while in Closed Loop Operation

reference and feedback value) to drive the DPLL to the desired phase. on-chip Phase / Frequency Detector to the Digital Loop Filter when the DPLL is operating in closed loop. Figure 14. Phase Control in Closed Loop Operation

4.14 DPLL Lock Detector

applied to the DPLL’s loop filter instead of the acquire filter settings.

4.15 Output Dividers

The RC32012A provides four fractional output dividers (FOD) and 12 integer output dividers (IOD).

4.15.1 Integer Output Dividers

mimics a gapped clock behavior when an IOD frequency is changed.

4.15.1.1 SYSREF Generation

available per IOD channel with a step size of one FOD output clock period.

R31DS0078EU0103 Rev.1.03 Page 42 Sep 15, 2022 RC32012A Datasheet

4.15.2 Fractional Output Dividers

There are four fractional output dividers (FOD) with FOD_0 as a part of DPLL/DCO in Jitter Attenuator mode. Each FOD can divide down either the APLL VCO clock or the DPLL output clock to provide frequencies of 500MHz to 1GHz. The fractional divide value involves two unsigned integer values, representing the integer (INT) and fraction (FRAC) portion of the divide ratio. The fraction portion is an integer representing the 43-bit numerator of a fraction, where the denominator of that fraction is fixed at 243. The equation for the FOD output frequency is as follows. Note: Fractions that approach 0, 1, or 1/2 can result in increased phase noise on the output signal due to integer- boundary spurs. It is recommended that APLL frequency and FOD divider settings be coordinated to avoid such fractions.

4.15.2.1 Output Phase Adjustment

Fine phase adjustments of the FOD output can be performed by increasing or decreasing the frequency of operation of the FOD for a period of time. This results in the clock edges of the FOD output clock being advanced (increased FOD output frequency will move edges to the left as seen on an oscilloscope relative to some fixed reference point) or delayed (decreased FOD output frequency moves edges to the right) by some amount. Coarse phase adjustments of the IOD output can be performed, and is the same as FOD phase adjustment but with a step size of one FOD output clock period.

4.15.2.2 Digital Controlled Oscillator (DCO) Mode

In DCO mode, a frequency control word (FCW) is passed directly from an external processor or FPGA to the DPLL with a step size of 1.11×10-10ppm and a full range of +244.20ppm to -244.08 ppm of the nominal DCO frequency. A positive value will increase the output frequency and a negative one will decrease the output frequency. The formula for the calculation of the FCW from the fractional frequency offset (FFO) is as follows: Where, FFO = Fractional Frequency Offset, in ppm FCW = Frequency Control Word (Positive or Negative Integer)

4.15.2.3 Numerically Controlled Oscillator (NCO) Mode

In NCO mode, each FOD in open-loop, except for FOD_0 in Jitter Attenuator mode, can adjust its output clock frequency with a step size of (1/243)/N where N is the nominal fractional output divide value, and is based on incrementing the numerator where the denominator of that fraction is fixed at 243. This frequency change at the output clock is gradual without glitches. The device can be in either Clock Generator mode or in Jitter Attenuator mode.

4.16 Clock Outputs

The RC32012A supports up to 12 differential or 24 single-ended clock outputs or any combination of differential and single-ended clock outputs. Every differential clock output can be programmed as two single-ended clock outputs. fFOD fAPLL INT FRAC       FCW 1 1                     253=

4.16.1 Output Buffer in Single-Ended Mode

coupling to other output clocks in the device, so it should be used with caution. options that can be selected from.

4.16.2 Output Buffer in Differential Mode

listed in Table 25. Note that VDDO_Qx options of 1.5V or 1.2V cannot be used in differential mode.

4.16.3 Output Banks

Table 25. Configurable Output Mode Options Table 26. Output Bank Assignment

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4.17 General Purpose Input/Outputs (GPIOs)

The GPIO signals are intended to provide a user with a flexible method to manage the control and status of the part via pins without providing dedicated pins for each possible function that may be wasted in a lot of applications. The GPIOs are fully configurable so that any GPIO can perform any function on any target logic block.

4.17.1 GPIO Modes

Each of the GPIO pins may be individually configured to operate in one of the following modes. Note that these modes are effective only once the RC32012A has completed its reset sequence. During the reset sequence one or more of these pins may have different functions as outlined in the Use of GPIO Pins at Reset section: ▪ General Purpose Input - in this mode of operation, the GPIO pin will act as an input whose logic level will be monitored and reflected in an internal register that may be read over the serial port. This is the default mode if no other option is programmed in OTP or EEPROM. ▪ General Purpose Output - in this mode of operation, the GPIO pin will act as an output that is driven to the logic level specified in an internal register. That register may be written over the serial port. ▪ Alarm output - In this mode of operation, the GPIO pin will act as a single-purpose alarm or Alert (aggregated alarm) output. For information on when an alarm output will be asserted or released and alarm sources, see Alarm Output Operation. Note that each GPIO can be independently configured and so if multiple GPIOs are configured the same way, they will all have the same output values.

• Loss-of-Signal status - in this mode of operation, the GPIO pin will act as an active-high Loss-of-Signal output. When the GPIO output is asserted, that indicates the selected input reference monitor is indicating an alarm condition. The related reference monitor and the associated GPIO pin are configured via registers. Configuration of the reference monitor will determine what constitutes an alarm. Note that the GPIO output reflects the actual state of the alarm signal from the selected reference monitor. This is not a latched or ‘sticky’ signal. Note that this is different than the other alarm sources below.
• Loss-of-Lock status - in this mode of operation, the GPIO pin will act as an active-high Loss-of-Lock output. When the GPIO output is asserted, that indicates the System APLL or DPLL has lost lock. The related PLL channel and associated GPIO pin are configured via registers. Note that the GPIO output reflects the ‘sticky’ state of the alarm signal from the selected PLL channel. This is a latched or ‘sticky’ signal and so must be cleared by register access to the ‘sticky’ bit clear register to remove the alarm signal.
• Holdover status - in this mode of operation, the GPIO pin act as an active-high Holdover status. When the GPIO output is asserted, that indicates the DPLL for the selected PLL channel has lost all its input references and is in a holdover state. The related PLL channel and associated GPIO pin are configured via registers. Note that the GPIO output reflects the ‘sticky’ state of the alarm signal from the selected PLL channel. This is a latched or ‘sticky’ signal and so must be cleared by register access to the ‘sticky’ bit clear register to remove the alarm signal.
• Alert (aggregated alarm) status - In this mode of operation, the GPIO will act as the logical OR of all alarm indicators that are enabled to drive this output. Only ‘sticky’ bits are available to drive the GPIO in this mode. This output will be asserted if any of the ‘sticky’ bits are asserted and enabled to cause the Alert (aggregated alarm). To clear this output, all contributing ‘sticky’ bits must be individually cleared This output will be active- high to indicate one or more alarms are asserted. ▪ Output Disable control - in this mode of operation, the GPIO pin will act as a control input. When the GPIO input is high, the selected output clock(s) will be disabled, then placed in high-impedance state. When the GPIO pin is low, the selected output clock(s) will be enabled and drive their outputs as configured. Selection of which output(s) are controlled by which GPIO(s) is configured via registers over the serial port or by OTP or EEPROM at reset. Each GPIO can be configured to control any or all outputs (or none). So all combinations can be setup from a single GPIO controlling all outputs, to all outputs responding to individual GPIO signals and any grouping in between. ▪ Single-ended Input Clock - in this mode of operation a single-ended input clock may be applied to certain GPIOs that map to specific input stages. This may be used if extra single-ended inputs are needed due to all

R31DS0078EU0103 Rev.1.03 Page 45 Sep 15, 2022 RC32012A Datasheet input reference clock pins are taken-up by differential input references. This mode can not be used if an input stage already has two single-ended input references from the CLKx/nCLKx input pins. ▪ Manual Clock Selection control - in this mode of operation, the GPIO pin acts as an input that will manually select between one of two inputs for a specific DPLL channel. The specific input references and the PLL channel must be pre-configured via registers. Assertion of the GPIO will select the higher priority input and de- assertion will select the lower priority input. ▪ DCO Increment - in this mode of operation, the GPIO pin will act as an increment command input pin for a specific channel configured as a DCO. The rising edge of the GPIO pin will cause an increment function on the indicated DCO. The amount of the increment and the related DCO to increment must be previously configured via registers. ▪ DCO Decrement - in this mode of operation, the GPIO pin will act as an decrement command input pin for a specific channel configured as a DCO. The rising edge of the GPIO pin will cause an decrement function on the indicated DCO.The amount of the decrement and the related DCO to decrement must be previously configured via registers.

4.17.2 GPIO Pin Configuration

The GPIO pins are all powered off a single voltage supply that only supports 1.8V operation. An internal register must be set to indicate 1.8V. This setting is a global one for all GPIOs. In addition, each GPIO can be enabled or disabled under register control. If enabled and configured in an operating mode that makes it an output, the user can choose if the GPIO output will behave as an open-drain output or a CMOS output. The open-drain output drives low, but is pulled high by a pull-up resistor. There is a very weak pull-up internal to the RC32012A, but an external pull-up is strongly recommended. In CMOS mode, the output voltage will be driven actively both high and low as needed. Register control may also enable a pull-up (default) or pull-down.

4.17.3 Alarm Output Operation

There are many internal status and alarm conditions within the RC32012A that can be monitored over the serial port by polling registers. Several of these can be directed to GPIO pins. In addition there is the ability to designate one of the GPIOs as an Alert (aggregated alarm) output signal called an Alert output. The RC32012A provides both a ‘live’ and a ‘sticky’ status for each potential alarm condition. A ‘live’ bit shows the status of that alarm signal at the moment it is read over the serial port. A ‘sticky’ bit will assert when an alarm condition changes state and will remain asserted until the user clears it by writing to the appropriate clear bit over the serial port. When a GPIO is configured to show the status of a specific alarm, it will show the ‘live’ or sticky status of that alarm, depending on the specific alarm, where a high output on the GPIO indicates the alarm is present. The Alert (aggregated alarm) output logic only uses the ‘sticky’ status bit for alarms. This ensures when a software routine reads the RC32012A there will be an indication of what caused the alarm in the first place. Note that there can be multiple sticky bits asserted. Table 27 shows the alarm conditions possible within the RC32012A. Note that the reference monitor, the DPLL, and the System DPLL blocks can generate the indicated alarms.

any or all of the bits that contributed to the alarm output being asserted. In addition to the above controls and status, each potential alarming logic block has its own controls and status. of the block ‘sticky’ alarm. GPIO as an Alert (aggregated alarm) output and determine which individual alarms will be able to drive it. Table 27. Alarm Indications

1. ‘Sticky’ alarm bits are set whenever the associated live alarm changes state. So there will be a new ‘sticky’ alarm on both assertion and

negation of the appropriate live alarm indication.

1. Only the ‘live’ status will negate by itself. The ‘sticky’ needs to be explicitly cleared by the user.

reference period above the threshold. reference period below the threshold. reference frequency above the threshold. reference frequency below the threshold.

1. For the Digital PLL, ‘sticky’ alarms are raised when the state machine transitions into specific states and ‘live’ status indicates that the
2. This includes the System DPLL, as well as all Digital PLL.

4.18 Device Initial Configuration

including any OCXO/TCXOs and generate output clocks. ▪ Default values for internal registers. Each of these will be discussed individually in the following sections and then integrated into the reset sequence.

4.18.1 Use of GPIO Pins at Reset

configuration. All of these register settings can be over-written later via serial port accesses. the one with the highest index will be used. Table 28. GPIO Pin Usage at Start-Up

1. Selection of this mode for a GPIO is performed using the Device Information block in the OTP memory, which is programmed by Renesas

“-000” unprogrammed devices). EEPROM to check for additional start-up information by default. default base address bit A2. Has no effect on serial port selected as SPI.

R31DS0078EU0103 Rev.1.03 Page 48 Sep 15, 2022 RC32012A Datasheet ▪ EEPROM Access Disable control A high input value on a GPIO programmed with this function prevents device from attempting to read device update information or SCSR configuration data from an external I2C EEPROM. This will speed-up device reset time, but prevents access to updated information that may be stored in EEPROM. If no GPIOs are configured in this mode, then the device will attempt to locate an external EEPROM at the appropriate point in the start-up sequence. If multiple GPIOs are configured to perform this function, then any one of them being active will disable EEPROM accesses, so it is recommended that no more than one GPIO be programmed for this function. ▪ Default Configuration Select control If no GPIOs are selected then GPIO[3:0] will be assumed and the value on those pins at the rising edge of the nMR signal will be used to select which of the SCSR configurations in OTP memory is to be used. Note that since a GPIO is pulled-up by default, unless these pins are pulled or driven low during the reset period, this will select SCSR Configuration 15. If one or more GPIOs are selected for this function, then the value on those pins at the rising edge of nMR will be used to select the SCSR configuration to be loaded. The Device Information block of the OTP may be configured to select any of up to four GPIO pins to be used for this purpose if the default GPIOs are not convenient. The GPIOs chosen do not have to be sequential, but whichever ones are chosen, the one with the lowest index number will be the LSB and so on in order of the index until the GPIO with the highest index is the MSB. No GPIO that appears elsewhere in this table should be used for this purpose. If less than four GPIO pins are selected, then the selected GPIOs will be used as the least-significant bits of a 4-bit selection value, with the upper bits set to zero. If more than four GPIOs are programmed for this function, then the GPIOs will form a larger bit-length word for selection of internal configuration.

4.18.2 Default Values for Registers

All registers are defined so that the default state (without any configuration data from OTP or EEPROM being loaded) will cause the device to power-up with none of the outputs enabled and all GPIO signals in General- Purpose Input mode. Users can then program any desired configuration data over the serial port once the reset sequence has completed.

4.19 One-Time Programmable (OTP) Memory

The RC32012A contains a 32KB One-Time Programmable (OTP) memory block. The term “one-time programmable” refers to individual blocks within the memory structure. Different blocks can be programmed at different times, but each block can only be programmed once. The data structure within the OTP is designed to facilitate multiple updates and multiple configurations being stored, up to the limit of the physical memory space. At this time, OTP can only be programmed within Renesas. After reset of the RC32012A, all internal registers are reset to their default values, then OTP contents are loaded into the device’s internal registers. A Device Information block programmed by Renesas at Final Test will always be loaded. This provides information that is specific to the device, including product ID codes and revision information. In addition there are zero or more device configurations stored in the OTP by Renesas at the factory if a special dash-code part number is requested. Certain GPIO pins are sampled at the rising edge of the external nMR input signal. The state of those pins at that time will be used by the RC32012A to determine which of up to 16 configurations stored in the OTP to load into the device registers. For information on how to select a configuration, see Use of GPIO Pins at Reset. Storage of configuration data in OTP does not require having a value stored for every register in the device. Register default values are defined to ensure that most functions will be disabled or otherwise made as neutral as possible. This allows only features that are being used in any particular configuration (and their associated trigger registers as defined in the 8A3xxxx Family Programming Guide) to need to be stored in OTP for that configuration. The intent of this is to minimize the size a configuration takes in OTP to allow more configurations to be stored

R31DS0078EU0103 Rev.1.03 Page 49 Sep 15, 2022 RC32012A Datasheet there. For this reason, the exact number of configurations store-able in OTP can’t be predetermined. There will be a minimum of 2 configurations and a maximum of 16 configuration capacity in the OTP. Part numbers with -000 as the dash code number are considered ‘unprogrammed’ parts, but will come with at least a Device Information block pre-programmed with Renesas-proprietary information including parameters needed to successfully boot the device to the point where it can read its configuration data. One Device Update block may also be programmed if determined to be appropriate by Renesas. Custom user configurations indicated with non-zero dash code part numbers will in addition have one or more SCSR Configuration sections pre-programmed as indicated in the datasheet addendum document for that particular dash code part number. Note that a programmed configuration, Device Information block or Device Update block may be invalidated via the OTP programming interface and if sufficient OTP space remains a new one added to replace it. Note that this does not erase or remove the original data and the space it consumes. It just marks it to be ignored by the device. This allows for a limited ability to update a device in the field either from a device functional update or configuration data perspective. This is a purely software-driven process handled over the serial port. For support if this type of in-field upgrade / change is desired, contact Renesas. Note that the ability to perform this type of in- field update is highly dependent on the size of the change versus the remaining space in OTP, so will not be possible in all cases.

4.19.1 Configuration Data in OTP

Users are able to program multiple configurations into the internal One-Time Programmable memory. The Timing Commander GUI Software can perform this function. Please contact Renesas for sample code if this needs to be performed in another way by the end-user. By using the GPIO pins at start-up as outlined in the Use of GPIO Pins at Reset, one of those configurations can be chosen for use as the initial values in the device registers after reset. Register values can be changed at any time over the serial port, but any such changes are not stored in OTP and will be lost on reset or power-down. The OTP is organized so that only configuration data that changes from the register default values needs to be stored. This saves OTP space and allows the potential for more configurations to be stored in the OTP . If the indicated configuration in OTP has a checksum error, it will not be loaded and registers will be left at their default values.

4.19.2 Configuration Data in External I2C EEPROM

As a final option, the initial configuration may be read from one or more external I2C EEPROMs. The Timing Commander GUI Software can generate the necessary EEPROM load information as an Intel HEX file for this purpose. The RC32012A will search each EEPROM for a valid configuration data block (valid header and checksum). The first valid block found will be loaded into internal registers after checksum validation. The search will terminate after the first valid block is found and loaded. This means that only a single valid configuration block can be stored via the EEPROM method. The RC32012A will look for EEPROMs at I2C base addresses of 1010xxx (binary), and search each EEPROM from the lowest address to the highest. When the device searches for an EEPROM configuration, it will check for a valid block at address offsets 0x0000 and 0xF000 within an EEPROM. If using this configuration method, see the warning in Step 5 – Search for Configuration in External EEPROM.

4.20 Reset Sequence

voltage regulator startup time of 3μsec, then release of nMR should be delayed. Figure 15. Power-Up Reset Sequencing The reset sequence discussed below will begin from the rising (negating) edge of the nMR (master reset) signal.

4.20.1 Step 0 – Reset Sequence Starting Condition

▪ The serial port protocols are not set at this point in the reset sequence, so the ports will not respond.

4.20.2 Step 1 – Negation of nMR (Rising Edge)

later stages of the reset sequence.

4.20.3 Step 2 – Internally Set Default Conditions

values. This will not result in any changes to the GPIO or output clock signals from their Step 0 condition.

R31DS0078EU0103 Rev.1.03 Page 51 Sep 15, 2022 RC32012A Datasheet Based on the serial port protocol selection made via the GPIO pin in Step 1, serial port configuration will be completed as indicated by the GPIO input pin. If SPI mode is selected by the GPIO, the register default values will configure it to use 4-wire SPI mode.

4.20.4 Step 3 – Scan for Device Updates in EEPROM

Unless a GPIO is configured to control this in Step 0 and in Step 1 is sampled in the state requesting no EEPROM read, this step will be performed by the RC32012A. The RC32012A will use the I2C Master port (if available) to check for device functional update information. If such information is found, it will be loaded, the device functionality updated and then the part will reinitialize to Step 0.

4.20.5 Step 4 – Read Configuration from OTP

Using the GPIO values latched in Step 1, the device will search the internal One-Time Programmable memory for the indicated configuration number. If no such configuration is found or the configuration has an invalid checksum, the device will skip to Step 6. Any errors in this process will be reported. If loading from OTP was successful, which configuration number was loaded will be reported. If the requested configuration is found and is valid, the device will load the registers indicated in the configuration data with the stored data values in the internal register image. Any register not included in the configuration data set will remain at its default value in the register image. Note: Many register modules have explicitly defined trigger registers that when written will cause the other register settings in that module to take effect. Users must ensure that the configuration in OTP will cause a write to all applicable trigger registers, even if that register’s contents would be all zero. Multi-byte register fields also require all bytes of the field to be written to ensuring triggering. For information about which trigger registers are associated with which other registers, see the 8A3xxxx Family Programming Guide. The contents of several of the registers will be used to guide the remainder of the reset sequence. ▪ If the APLL feedback divider value was programmed in this step, perform APLL calibration in parallel with remaining reset activities. ▪ Re-configure serial ports to use I2C or SPI protocols as indicated (for information, see the I2C Slave Operation or SPI Operation).

4.20.6 Step 5 – Search for Configuration in External EEPROM

Unless a GPIO is configured to control this in Step 0 and in Step 1 is sampled in the state requesting no EEPROM read, this step will be performed by the RC32012A. The device will use its I2C Master Port to attempt to access an external I2C EEPROM at base address 1010000 (binary) at an I2C frequency of 1MHz. If there is no response, this will be repeated at base address 1010001 (binary) at 1MHz. This will repeat up to address 1010111 (binary) at 1MHz. If there are still no responses, the search will be repeated at 400kHz and then again at 100kHz. If no response is received after this whole sequence, the device will proceed to Step 6. Any errors in the process will be reported in status registers. If at any point in the above search sequence a response is received from an EEPROM, the device will read data from the EEPROM at address offsets 0x0000 and 0xF000 in the EEPROM. If a valid configuration data block is found, it will be read, its checksum validated and if that passes, loaded into internal the internal register image similarly to OTP configuration data described in Step 4. If the data found is not of the correct format or the data block fails a checksum comparison, it will be ignored. The search will continue through the EEPROM and on to the next EEPROM address until the whole range has been searched or a valid configuration block has been found and applied to the internal register image. Then the sequence will proceed to Step 6. Warning: Since OTP and EEPROM configuration data rarely consists of a full register image, reading of configuration data from OTP and then from one or more configuration blocks stored in EEPROM may result in internal registers being loaded with conflicting settings drawn partially from each of the configuration data sets being loaded. It is strongly recommended that a configuration block placed in EEPROM only be used when no valid configuration is being pointed to in OTP by GPIO signals (or there is no valid configuration in OTP at all).

R31DS0078EU0103 Rev.1.03 Page 52 Sep 15, 2022 RC32012A Datasheet If multiple configurations are to be used then the user must ensure all registers are set to the desired values by the final configuration block to be loaded.

4.20.7 Step 6 – Complete Configuration

The RC32012A will complete the reset and initial configuration process at this point and begin normal operations. Completion steps include: ▪ Calibrate the System APLL and lock it to the reference clock on the OSCI input, ▪ Perform a temperature sensor cycle to establish an initial value in internal registers, ▪ Enable serial port operation as configured, ▪ Apply configuration settings from the internal register image to the actual registers and enable output clocks and GPIOs as configured. ▪ Begin operation on input reference monitors and PLL state machine alarms / status, ▪ Enable alarm operation as configured. Note that there are several scenarios in which the reset sequence will reach this point without retrieving any configuration data and with all registers in the default state. This may be intentional for users who wish to configure only via the serial port or the result of a problem in the loading of a configuration. Users may read appropriate status bits to determine what failures, if any, occurred during the reset sequence.

4.21 Clock Gating and Logic Power-Down Control

The RC32012A has the ability to disable the clocks to many logic blocks inside the device. It also has the ability to turn-off internal power regulators, disabling individual power domains within the part. Because of the potentially complex interactions of the logic blocks within the device, logic within the part will handle the decision-making of what will be powered-off versus clock-gated versus fully operational at any time. By default, the device will configure itself with functions in the lowest power-consuming state consistent with powering-up the part and reading a user configuration. User configurations, whether stored in internal OTP , external EEPROM or manually adjusted over the serial port, should make use of register bits to only turn-on functions that are needed. Also if a function is no longer needed, register bits should be used to indicate it is no longer required. Internal logic will reduce its power-consumption state in reaction to these indicators to the greatest extent possible.

4.22 Serial Port Functions

The RC32012A supports 1 serial port. The signals on the port share the functions of an I2C Master port used for loading configuration data at reset and a configurable slave I2C or SPI port that can be used at any time after the reset sequence is complete to monitor and/or configure the device. Note that the I2C master port can only be used when the slave port is configured in I2C mode. Since I2C master operation only occurs immediately after reset, while configuration or other data is being loaded from an external I2C serial EEPROM, I2C mode for the serial port can be selected via GPIOs as indicated in Use of GPIO Pins at Reset. The operation of the serial port when in I2C master operation (during self-configuration only) is described in I2C Master. The SCL and SDIO pins are used for this purpose. For details on the operation of the master I2C and slave I2C or SPI ports, see the appropriate section below. A slave serial port can be reconfigured at any time by accessing the appropriate registers within a single burst write. This includes configuration options with each protocol or switching between protocols (I2C to SPI or vice versa). However it is recommended that the full operating mode configuration, including page sizes for registers, for a serial port be set in the initial configuration data read from OTP or external EEPROM (see Device Initial Configuration for details).

SPI descriptions will refer to the signals by their function in the selected mode, as shown in Table 29.

4.22.1 Addressing Registers within the RC32012A

32kbytes contains user accessible registers. interact to address a register within the RC32012A. Figure 16. Register Addressing Modes via Serial Port Table 29. Serial Port Pin to Function Mapping

4.22.2 I2C Slave Operation

1. Figure 17 shows the sequence of states on the I2C SDA signal for the supported modes of operation.

Figure 17. I2C Slave Sequencing Addr, all bits of the 1B or 2B offset field can be used to address internal registers. come from the page register. written in a single burst write transaction. only needs to be setup once after reset via a 4-byte burst access at offset FFFCh. 2B mode). An internal address pointer is incremented automatically as each data byte is written or read.

4.22.2.1 I2C 1-byte (1B) Addressing Examples

B6* FC 00 CB 10 20 #Set Page Register, *I2C Address is left-shifted one bit. B6* FC 00 C0 10 20 #Set Page Register, *I2C Address is left-shifted one bit. B7 <read back data> #Send address with Read bit set.

4.22.2.2 I2C 2-byte (2B) Addressing

B6* FF FD 00 10 20 #Set Page Register, *I2C Address is left-shifted one bit. B7 <read back data> #Send address with Read bit set.

4.22.3 I2C Master

conditions, see Reset Sequence. master logic will negotiate with any EEPROMs found to use the highest speed of 1MHz, 400kHz or 100kHz. Figure 18. I2C Master Sequencing

4.22.4 SPI Operation

signals (SDI and SDIO respectively). In 3-wire mode, the SDIO signal is used as a single, bidirectional data signal. SPI mode is the default. The R/W bit is high for Read Cycles and low for Write Cycles. Figure 19. SPI Sequencing

• In 1B operation, the 16-bit register address is formed by using the 7-bits of address supplied in the SPI access and taking the upper 9-bits from the page register. The page register is accessed using an Offset Address of 7Ch with a 4-byte burst access.
• In 2B operation, the 16-bit register address is formed by using the 15-bits of address supplied in the SPI access and taking the upper 1-bit from the page register. Note that this bit will always be ‘1’ for register accesses, so the page register only needs to be set once in 2B operation. The page register can be accessed using a 3-byte burst access Offset Address of 7FFDh. It should be accessed in a single burst write transaction to set it. ▪ Data sampling on falling or rising edge of SCLK ▪ Output (read) data positioning relative to active SCLK edge ▪ 4-wire (SCLK, CS, SDIO, SDI) or 3-wire (SCLK, CS, SDIO) operation ▪ In 3-wire mode, SDIO is a bi-directional data pin. ▪ Output signal protocol compatibility / drive strength and termination voltage 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 CS SCLK SDI (4-wire) SDIO (4-wire) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14R/ W CS SCLK SDI (4-wire) SDIO (4-wire) D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Hi-Z SPI Read Sequence* SPI Write Sequence* XX (SDI un us ed while da ta being rea d) A14-A7 are omitted in 7b SPI Addressing Mode Data byte from Addres s provided Data byte from Address + 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A14-A7 are omitted in 7b SPI Addressing Mode Data byte to Address provided Dat a byte to Address + 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14R/ W SDI O (3-wire) D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13R/ W SDIO (3-wire) D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDIO Driven by Master SDIO Driven by Slave SDI O Driven by Master * See the timing diagrams for exact timing relationships.

R31DS0078EU0103 Rev.1.03 Page 57 Sep 15, 2022 RC32012A Datasheet Note: SPI burst mode operation is required to ensure data integrity of multi-byte registers. When accessing a multi-byte register, all data bytes must be written or read in a single SPI burst access. Bursts may be of greater length if desired, but must not extend beyond the end of the register page. An internal address pointer is incremented automatically as each data byte is written or read.

4.22.4.1 SPI 1-byte (1B) Addressing Example

Example write to “50” to register 0xCBE4 7C 80 CB 10 20 #Set Page register 64* 50 #*MSB is 0 for write transactions Example read from 0xC024: 7C 00 C0 10 20 #Set Page register A4* 00 #*MSB is set, so this is a read command

4.22.4.2 SPI 2-byte (2B) Addressing Example

Example write to “50” to register 0xCBE4 7F FD 80 10 20 #Set Page register 4B E4* 50 #*MSB is 0 for write transactions Example read from 0xC024: 7F FD 80 10 20 #Set Page register C0* 24 00 #*MSB is set, so this is a read command 5. Applications Information

5.1 Recommendations for Unused Input and Output Pins

5.1.1 Inputs

5.1.1.1 CLKx / nCLKx Input

For applications that do not require the use of the reference clock input, both CLK and nCLK should be left floating. If the CLK/nCLK input is connected but not used by the device, it is recommended that CLK and nCLK not be driven with active signals.

5.1.1.2 LVCMOS Control Pins

LVCMOS control pins have internal pull-ups. Additional resistance is not required but can be added for additional protection. A 1k resistor can be used.

5.1.2 Outputs

5.1.2.1 LVCMOS Outputs

Any LVCMOS output can be left floating if unused. There should be no trace attached. The mode of the output buffer should be set to tri-stated to avoid any noise being generated.

5.1.2.2 Differential Outputs

All unused differential outputs can be left floating. Renesas recommends that there is no trace attached. Both sides of the differential output pair should be left floating or terminated.

5.1.3 Power Connections

• If all outputs Qn/nQn associated with any particular VDDO_Qn pin are not used, the power pin can be left floating

5.2 Clock Input Interface

Quick Guide - Output Terminations (AN-953). levels, see Termination - AC Coupling Clock Receivers (AN-844) or contact Renesas technical support.

5.3 Overdriving the XTAL Interface

power rail and to reduce internal noise. Figure 20. 1.8V LVCMOS Driver to XTAL Input Interface transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance.

Figure 21. LVCMOS Driver to XTAL Input Interface purposes. The datasheet specifications are characterized and guaranteed using a quartz crystal as the input. Figure 22. LVPECL Driver to XTAL Input Interface

5.4 Wiring the Differential Input to Accept Single-Ended Levels

For information, see Differential Input to Accept Single-ended Levels Application Note (AN-836).

5.5 Differential Output Termination

Figure 24). These schemes are the same as normally used for an LVDS output type. close to the receiver as possible.

Figure 23. Standard LVDS Termination Figure 24. AC Coupled LVDS Termination contact Renesas for support.

5.6 External I2C Serial EEPROM Recommendation

recommends the use of the Microchip 24FC1025 or OnSemi CAT24M01 1Mbit EEPROM.

5.7 Schematic and Layout Information

5.8 Power Considerations

For power and current consumption calculations, see the Renesas Timing Commander tool.

6.1 VFQFN EPAD Thermal Release Path

between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. Lead frame Base Package, Amkor Technology. Table 30. Recommended Tuning Capacitors for Crystal Input

1. Recommendations are based on 4pF stray capacitance on each leg of the crystal. Adjust according to the PCB capacitance.
2. This will tune the crystal to a CL of 12pF, which is fine when channels are running in Jitter attenuator mode or referenced to an XO. It

will present a positive ppm offset for channels running exclusively in Synthesizer mode and referenced only to the crystal.

Figure 25. P .C. Assembly for Exposed Pad Thermal Release Path – Side View (Drawing not to Scale)

6.2 Thermal Characteristics

and is subject to change without revision of this document. Table 31. Thermal Characteristics

1. Multi-Layer PCB with two ground and two voltage planes.
2. Assumes ePAD is connected to a ground plane using a grid of 9x9 thermal vias.

▪ Lines 2 and 3 are the part number.

• “000” denotes dash code; “GN2” denotes the package code. ▪ Line 4:
• “#” denotes stepping; “YYWW” is the last digits of the year and week that the part was assembled; “$” denotes mark code. ▪ “LOT” denotes the lot code; “COO” denotes country of origin

1. Replace “ddd” with the desired pre-programmed configuration code provided by Renesas in response to a custom configuration request

or use “000” for unprogrammed parts.

3 Tray -40° to +85°C

3 Tape and Reel, Pin 1

Table 32. Pin 1 Orientation in Tape and Reel Packaging

1.03 Sep 15, 2022 ▪ Updated the differential output parameter for tR / tF in Table 18

1.02 May 6, 2022 ▪ Deleted the “Temperature Sensor” section

1.01 Nov 1, 2021 ▪ Updated the Functional Description section. ▪ Updated the Marking Diagram section. 1.00 Aug 13, 2021 Initial release.

© Renesas Electronics Corporation

© Renesas Electronics Corporation Package Revision HistoryRev No.Date CreatedDescriptionMay 10,2021Rev 04Added Chamfer on page 2May 6, 2021Rev 03Change Land Pattern Dimension

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