RC31012B001GNA#BB0

RC310XXB_V01 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 68

Technical content

Datasheet sections

• 1.1 Pin Assignments – RCxxx12B (Top View)
• 1.2 Pin Descriptions – RCxxx12B
• 1.3 Pin Assignments – RCxxx12BQ (Top View)
• 1.4 Pin Descriptions – RCxxx12BQ
• 1.5 Pin Assignments – RCxxx08B (Top View)
• 1.6 Pin Descriptions – RCxxx08B
• 1.7 Pin Assignments – RCxxx08BQ (Top View)
• 1.8 Pin Descriptions – RCxxx08BQ
• 1.9 Pin Assignments – RCxxx05BQ (Top View)
• 1.10 Pin Descriptions – RCxxx05BQ
• 1.11 Pin Characteristics
• 2.1 Absolute Maximum Ratings
• 2.2 Recommended Operating Conditions
• 2.3 Electrical Characteristics
• 3.1 Power-Up, Configuration, and Serial Interfaces
• 3.2 Input Clocks
• 3.2.1 Crystal/Reference Input
• 3.2.2 Clock Inputs
• 3.3 Clock Input Monitors
• 3.4 APLL
• 3.4.1 APLL Lock Detector
• 3.5 DPLL
• 3.6 DPLL Reference Selection
• 3.6.1 Manual Reference Selection
• 3.6.2 Automatic Reference Selection
• 3.6.3 Hitless Reference Switching
• 3.7 DPLL Operating Modes
• 3.7.1 Free-run
• 3.7.2 Acquire
• 3.7.3 Normal
• 3.7.4 Holdover
• 3.7.5 Hitless Switch
• 3.7.6 Write Frequency
• 3.7.7 Manual Mode
• 3.8 DPLL Lock Detector
• 3.9 Output Dividers
• 3.9.1 Integer Output Dividers
• 3.9.2 Fractional Output Dividers
• 3.10 Clock Outputs
• 3.10.1 Output Types
• 3.10.2 Output Banks
• 4.1 Recommendations for Unused Pins
• 4.1.1 XIN_REFIN/XOUT_REFINB
• 4.1.2 CLKIN/CLKINb [1:0] Inputs
• 4.1.3 GPIO/GPI Pins
• 4.1.4 LVCMOS Outputs
• 4.1.5 Differential Outputs

Features

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe ® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ Integrated 100 and 85 LP-HCSL terminations ▪ JESD204B/C support on differential or single- ended outputs with DC-coupling or AC-coupling ▪ Up to four single-ended or two differential clock inputs; one crystal/TCXO/OCXO input ▪ 400kHz I 2C / SMBus or 20MHz SPI support ▪ Configuration via factory-programmed One-Time Programmable (OTP) memory, serial interface, or external I2C EEPROM ▪ OTP holds up to four complete or 27 partial configurations ▪ 1.8V, 2.5V, 3.3V, -40° to +85°C operation ▪ RC31012B – 12 output pairs/24 single-ended outputs

• 6 × 6 mm 48-QFN, integrated crystal option ▪ RC31008B – 8 differential/16 single-ended outputs
• 5 × 5 mm 40-QFN, integrated crystal option ▪ RC31005B – 5 differential/10 single-ended outputs
• 4 × 4 mm 32-LGA with integrated crystal

Figure 1. Typical Wire-line Infrastructure Use Case

Figure 2. RC310xxB Block Diagram

R31DS0179EU0124 Rev.1.24 Page 4 Feb 3, 2026 RC310xxB Datasheet

1.1 Pin Assignments – RCxxx12B (Top View)

1.2 Pin Descriptions – RCxxx12B

Table 1. RCxxx12B Pin Descriptions 1 VDDA Power Analog power supply. See Table 8 for supported voltages.

3 XOUT_REFINb I/O

Crystal Output or differential reference clock negative input. this pin must be left unconnected. 4 VDDX Power Crystal oscillator power supply. See Table 8 for supported voltages.

5 CLKIN0_GPI0 I Differential clock positive input / CMOS single-ended reference clock input or general

6 CLKIN0b_GPI1 I Differential clock negative input / CMOS single-ended reference clock input or general

7 VDDR Power CLKIN (receiver) power supply. See Table 8 for supported voltages.

8 CLKIN1_GPI2 I Differential clock positive input / CMOS single-ended reference clock input or general

9 CLKIN1b_GPI3 I Differential clock negative input / CMOS single-ended reference clock input or general

10 SCL_SCLK I

I2C Mode: I2C interface bi-directional clock.

11 SDA_nCS I

programming the OTP, this supply must be 2.5V or 3.3V. 13 GPIO0 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 14 GPIO1 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 15 GPIO2 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 16 GPIO3 I/O General purpose input/output. 17 GPIO4 I/O General purpose input/output. 18 OUT0b O Output Clock 0 negative. 19 OUT0 O Output Clock 0 positive. 20 VDDO0 Power Power supply for output bank 0 and IOD 0. See Table 8 for supported voltages. 21 VDDO1 Power Power supply for output bank 1 and IOD 1. See Table 8 for supported voltages. 22 OUT1b O Output Clock 1 negative. 23 OUT1 O Output Clock 1 positive. 24 VDDO2 Power Power supply for output bank 2 and FOD 0. See Table 8 for supported voltages. 25 OUT2b O Output Clock 2 negative. 26 OUT2 O Output Clock 2 positive. 27 OUT3b O Output Clock 3 negative. 28 OUT3 O Output Clock 3 positive. 29 OUT4b O Output Clock 4 negative. 30 OUT4 O Output Clock 4 positive. 31 OUT5b O Output Clock 5 negative. 32 OUT5 O Output Clock 5 positive. 33 OUT6b O Output Clock 6 negative. 34 OUT6 O Output Clock 6 positive. 35 OUT7b O Output Clock 7 negative. 36 OUT7 O Output Clock 7 positive. 37 VDDO3 Power Power supply for output bank 3 and FOD 1. See Table 8 for supported voltages. 38 OUT8b O Output Clock 8 negative. 39 OUT8 O Output Clock 8 positive. 40 OUT9b O Output Clock 9 negative. 41 OUT9 O Output Clock 9 positive. 42 VDDO4 Power Power supply for output bank 4 and FOD 2. See Table 8 for supported voltages. 43 VDDO5 Power Power supply for output bank 5 and IOD 2. See Table 8 for supported voltages. 44 OUT10b O Output Clock 10 negative. 45 OUT10 O Output Clock 10 positive. 46 OUT11b O Output Clock 11 negative. 47 OUT11 O Output Clock 11 positive. Table 1. RCxxx12B Pin Descriptions (Cont.)

1.3 Pin Assignments – RCxxx12BQ (Top View)

1.4 Pin Descriptions – RCxxx12BQ

48 VDDO6 Power Supply voltage for output bank 6 and IOD 3. See Table 8 for supported voltages. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied. Table 2. RCxxx12B Pin Descriptions 1 VDDA Power Analog power supply. See Table 8 for supported voltages. 2 DNC N/A Do not connect. This pin should have no stubs. 3 DNC N/A Do not connect. This pin should have no stubs. 4 VDDX Power Crystal oscillator power supply. See Table 8 for supported voltages. 7 VDDR Power CLKIN (receiver) power supply. See Table 8 for supported voltages.

I2C Mode: I2C interface bi-directional clock. programming the OTP, this supply must be 2.5V or 3.3V. 13 GPIO0 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 14 GPIO1 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 15 GPIO2 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 16 GPIO3 I/O General purpose input/output. 17 GPIO4 I/O General purpose input/output. 18 OUT0b O Output Clock 0 negative. 19 OUT0 O Output Clock 0 positive. 20 VDDO0 Power Power supply for output bank 0 and IOD 0. See Table 8 for supported voltages. 21 VDDO1 Power Power supply for output bank 1 and IOD 1. See Table 8 for supported voltages. 22 OUT1b O Output Clock 1 negative. 23 OUT1 O Output Clock 1 positive. 24 VDDO2 Power Power supply for output bank 2 and FOD 0. See Table 8 for supported voltages. 25 OUT2b O Output Clock 2 negative. 26 OUT2 O Output Clock 2 positive. 27 OUT3b O Output Clock 3 negative. 28 OUT3 O Output Clock 3 positive. 29 OUT4b O Output Clock 4 negative. 30 OUT4 O Output Clock 4 positive. 31 OUT5b O Output Clock 5 negative. 32 OUT5 O Output Clock 5 positive. 33 OUT6b O Output Clock 6 negative. 34 OUT6 O Output Clock 6 positive. 35 OUT7b O Output Clock 7 negative. 36 OUT7 O Output Clock 7 positive. 37 VDDO3 Power Power supply for output bank 3 and FOD 1. See Table 8 for supported voltages. 38 OUT8b O Output Clock 8 negative. 39 OUT8 O Output Clock 8 positive. 40 OUT9b O Output Clock 9 negative. 41 OUT9 O Output Clock 9 positive. 42 VDDO4 Power Power supply for output bank 4 and FOD 2. See Table 8 for supported voltages. 43 VDDO5 Power Power supply for output bank 5 and IOD 2. See Table 8 for supported voltages. 44 OUT10b O Output Clock 10 negative. 45 OUT10 O Output Clock 10 positive. 46 OUT11b O Output Clock 11 negative. 47 OUT11 O Output Clock 11 positive. Table 2. RCxxx12B Pin Descriptions (Cont.)

1.5 Pin Assignments – RCxxx08B (Top View)

1.6 Pin Descriptions – RCxxx08B

48 VDDO6 Power Supply voltage for output bank 6 and IOD 3. See Table 8 for supported voltages. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied. Table 3. RCxxx08B Pin Descriptions

2 XOUT_REFINb I/O

Crystal Output or differential reference clock negative input. this pin must be left unconnected. 3 VDDX Power Crystal oscillator power supply. See Table 8 for supported voltages.

4 CLKIN0_GPI0 I differential clock positive input / CMOS single-ended reference clock input or general

5 CLKIN0b_GPI1 I differential clock negative input / CMOS single-ended reference clock input or general

6 VDDR Power CLKIN (receiver) power supply. See Table 8 for supported voltages.

7 CLKIN1_GPI2 I Differential clock positive input / CMOS single-ended reference clock input or general

8 CLKIN1b_GPI3 I Differential clock negative input / CMOS single-ended reference clock input or general

9 SCL_SCLK I

I2C Mode: I2C interface bi-directional clock.

10 SDA_nCS I/O

I2C Mode: I2C interface bi-directional data in open-drain mode. programming the OTP, this supply must be 2.5V or 3.3V. 12 GPIO0 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 13 GPIO1 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 14 GPIO2 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 15 GPIO3 I/O General purpose input/output. 16 GPIO4 I/O General purpose input/output. 18 VDDO1 Power Power supply for output bank 1 and IOD 1. See Table 8 for supported voltages. 19 OUT1b O Output Clock 1 negative.

20 OUT1 O Output Clock 1 positive

21 VDDO2 Power Power supply for output bank 2 and FOD 0. See Table 8 for supported voltages. 22 OUT2b O Output Clock 2 negative. 23 OUT2 O Output Clock 2 positive. 24 OUT3b O Output Clock 3 negative. 25 OUT3 O Output Clock 3 positive. 26 OUT6b O Output Clock 6 negative. 27 OUT6 O Output Clock 6 positive. 28 OUT7b O Output Clock 7 negative. 29 OUT7 O Output Clock 7 positive. 30 VDDO3 Power Power supply for output bank 3 and FOD 1. See Table 8 for supported voltages. 31 OUT8b O Output Clock 8 negative. 32 OUT8 O Output Clock 8 positive. 33 VDDO4 Power Power supply for output bank 4 and FOD 2. See Table 8 for supported voltages. 34 VDDO5 Power Power supply for output bank 5 and IOD 2. See Table 8 for supported voltages. 35 OUT10b O Output Clock 10 negative. 36 OUT10 O Output Clock 10 positive. 37 OUT11b O Output Clock 11 negative. 38 OUT11 O Output Clock 11 positive. 39 VDDO6 Power Supply voltage for output bank 6 and IOD 3. See Table 8 for supported voltages. 40 VDDA Power Analog power supply. See Table 8 for supported voltages. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied. Table 3. RCxxx08B Pin Descriptions (Cont.)

1.7 Pin Assignments – RCxxx08BQ (Top View)

1.8 Pin Descriptions – RCxxx08BQ

Table 4. RCxxx08BQ Pin Descriptions 1 DNC N/A Do not connect. This pin should have no stubs. 2 DNC N/A Do not connect. This pin should have no stubs. 3 VDDX Power Crystal oscillator power supply. See Table 8 for supported voltages. 6 VDDR Power CLKIN (receiver) power supply. See Table 8 for supported voltages. I2C Mode: I2C interface bi-directional clock. I2C Mode: I2C interface bi-directional data in open-drain mode. programming the OTP, this supply must be 2.5V or 3.3V.

12 GPIO0 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 13 GPIO1 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 14 GPIO2 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 15 GPIO3 I/O General purpose input/output. 16 GPIO4 I/O General purpose input/output. 18 VDDO1 Power Power supply for output bank 1 and IOD 1. See Table 8 for supported voltages. 19 OUT1b O Output Clock 1 negative. 21 VDDO2 Power Power supply for output bank 2 and FOD 0. See Table 8 for supported voltages. 22 OUT2b O Output Clock 2 negative. 23 OUT2 O Output Clock 2 positive. 24 OUT3b O Output Clock 3 negative. 25 OUT3 O Output Clock 3 positive. 26 OUT6b O Output Clock 6 negative. 27 OUT6 O Output Clock 6 positive. 28 OUT7b O Output Clock 7 negative. 29 OUT7 O Output Clock 7 positive. 30 VDDO3 Power Power supply for output bank 3 and FOD 1. See Table 8 for supported voltages. 31 OUT8b O Output Clock 8 negative. 32 OUT8 O Output Clock 8 positive. 33 VDDO4 Power Power supply for output bank 4 and FOD 2. See Table 8 for supported voltages. 34 VDDO5 Power Power supply for output bank 5 and IOD 2. See Table 8 for supported voltages. 35 OUT10b O Output Clock 10 negative. 36 OUT10 O Output Clock 10 positive. 37 OUT11b O Output Clock 11 negative. 38 OUT11 O Output Clock 11 positive. 39 VDDO6 Power Supply voltage for output bank 6 and IOD 3. See Table 8 for supported voltages. 40 VDDA Power Analog power supply. See Table 8 for supported voltages. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied. Table 4. RCxxx08BQ Pin Descriptions (Cont.)

1.9 Pin Assignments – RCxxx05BQ (Top View)

1.10 Pin Descriptions – RCxxx05BQ

Table 5. RCxxx05BQ Pin Descriptions

1 SDA_nCS I/O

I2C Mode: I2C interface bi-directional data in open-drain mode.

2 SCL_SCLK I

I2C Mode: I2C interface bi-directional clock. 3 VDDR Power CLKIN (receiver) power supply. See Table 8 for supported voltages.

4 CLKIN0b_GPI1 I Differential clock negative input / CMOS single-ended reference clock input or general

6 VDDX Power Crystal oscillator power supply. See Table 8 for supported voltages. 7 DNC NA Do not connect. This pin should have no stubs. 8 DNC NA Do not connect. This pin should have no stubs. 9 VDDA Power Analog power supply. See Table 8 for supported voltages. 10 VDDO6 Power Supply voltage for output bank 6 and IOD 3. See Table 8 for supported voltages. 11 OUT10 O Output Clock 10 positive. 12 OUT10b O Output Clock 10 negative. 13 VDDO5 Power Power supply for output bank 5 and IOD 2. See Table 8 for supported voltages.

33 GND

1.11 Pin Characteristics

14 VDDO4 Power Power supply for output bank 4 and FOD 2. See Table 8 for supported voltages. 15 OUT8 O Output Clock 8 positive. 16 OUT8b O Output Clock 8 negative. 17 VDDO3 Power Power supply for output bank 3 and FOD 1. See Table 8 for supported voltages. 18 OUT6 O Output Clock 6 positive. 19 OUT6b O Output Clock 6 negative.

20 GND Power Ground

21 OUT3 O Output Clock 3 positive. 22 OUT3b O Output Clock 3 negative. 23 VDDO2 Power Power supply for output bank 2 and FOD 0. See Table 8 for supported voltages. 24 VDDO1 Power Power supply for output bank 1 and IOD 1. See Table 8 for supported voltages.

25 OUT1 O Output Clock 1 positive

26 OUT1b O Output Clock 1 negative.

27 GPIO4 I/O General purpose input/output

28 GPIO3 I/O General purpose input/output

29 GPIO2 I/O

3-level logic input during power-up and CMOS level logic after unless set to 3-level.

30 GPIO1 I/O

3-level logic input during power-up and CMOS level logic after unless set to 3-level.

31 GPIO0 I/O

3-level logic input during power-up and CMOS level logic after unless set to 3-level. programming the OTP, this supply must be 2.5V or 3.3V. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied. Table 6. Pin Characteristics

1. When used as clock input.

Table 5. RCxxx05BQ Pin Descriptions (Cont.)

R31DS0179EU0124 Rev.1.24 Page 18 Feb 3, 2026 RC310xxB Datasheet

implied. Exposure to absolute maximum rating conditions may affect device reliability.

2.1 Absolute Maximum Ratings

2.2 Recommended Operating Conditions

Table 7. Absolute Maximum Ratings

1. VDD refers to the VDD pin that supplies the particular input. To determine to which VDD pin the specification applies, see Table 46.
2. This limit only applies when XIN_REFIN/XOUT_REFINb are configured as an “Input Buffer” for use with an external oscillator. No limit is implied

when connected directly to a crystal. Table 8. Recommended Operating Conditions[1][2]

1. All electrical characteristics are specified over Recommended Operating Conditions unless noted otherwise.
2. All conditions in this table must be met to guarantee device functionality and performance.

2.3 Electrical Characteristics

Table 9. PCIe Refclk Phase Jitter, Clock Generator Mode, VDDO = 1.8V/2.5V/3.3V [1][2]

1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

1. Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83.

1. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
2. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
5. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
6. The PCI Express Base Specification 7.0 provides the filters necessary to calculate IR jitter values; it does not provide specification limits,

placed next to the PCIe device in an IR system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

Table 10. PCIe Refclk Additive Phase Jitter, Fanout Mode, VDDO = 1.8V/2,5V/3.3V[1][2]

1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

1. Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83.

1. The sum of the input jitter and the RC310xxB additive jitter must be less than these values. Peak to peak values are calculated with an arithmetic
2. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
3. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
5. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
6. Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
7. The PCI Express Base Specification 7.0 provides the filters necessary to calculate IR jitter values; it does not provide specification limits, therefore,

for the jitter added by the channel. Using 32GT/s, the Refclk output jitter budget is 150fs RMS. One half of the Refclk jitter budget is 106fs RMS. to the PCIe device in an IR system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit. Table 11. Phase Jitter and Phase Noise – 1.8V VDDO[1][2]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. Characterized using a Rohde and Schwarz SMA100 overdriving the XTAL interface.

Table 11. Phase Jitter and Phase Noise – 1.8V VDDO[1][2] (Cont.)

Table 12. Phase Jitter and Phase Noise – 2.5V VDDO[1][2]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. Characterized using a Rohde and Schwarz SMA100 overdriving the XTAL interface.

Table 13. Phase Jitter and Phase Noise – 3.3V VDDO[1][2] Table 12. Phase Jitter and Phase Noise – 2.5V VDDO[1][2] (Cont.)

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. Characterized using a Rohde and Schwarz SMA100 overdriving the XTAL interface.

Table 14. Jitter Attenuator and Network Synchronization[1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. This parameter will vary with the quality of the TDC and system DPLL references. The typical value shown assumes an ideal reference is used

as input to the TDC and system DPLL. Table 13. Phase Jitter and Phase Noise – 3.3V VDDO[1][2] (Cont.)

Table 15. Clock Input Frequencies[1]

1. For crystal characteristics, see Table 16.

Table 16. External Crystal Characteristics

1. These parameters are required, regardless of crystal used.
2. These parameters are customer/application dependent. Common maximum values are F TOL = ±20ppm, FSTAB = ±20ppm, and Aging =

±5ppm/10years. The customer is free to adjust these parameters to their particular requirements. Table 17. Internal Crystal Characteristics (Q Versions Only)

Table 18. Output Enable/Disable Timing[1]

1. The enable/disable circuit incurs a 1 or 2 clock period delay to insure glitch-free start and stop of the outputs. The clock period specified is the

period of the output clock. If an OE is used to control different output frequencies, the period of the lowest output frequency should be used. Asynchronous Non-Glitch-Free Mode. OE or global OE, any output type.

1. Asynchronous Non-Glitch-Free Mode is sometimes referred to as Squelch Mode. This mode does not synchronize the enable/disable signal to the

output and may result is glitches or runt pulses on the outputs. Table 19. Output Frequencies and Startup Times[1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output. A stable clock is

defined as one generated from a locked PLL (as appropriate for the configuration listed) with no further perturbations in frequency expected.

1. Start-up time will depend on the actual configuration used. For more information, please contact Renesas technical support.

Table 20. Output-to-Output, Input-to-Output Skew – LP-HCSL Outputs 1.8V/2.5V/3.3V VDDO[1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
2. This parameter is defined in accordance with JEDEC Standard 65
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 21. Output-to-Output, Input-to-Output Skew – LVDS Outputs 1.8V/2.5V/3.3V VDDO[1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
2. This parameter is defined in accordance with JEDEC Standard 65
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 22. Output-to-Output, Input-to-Output Skew – LVCMOS Outputs 1.8V/2.5V/3.3V VDDO[1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
2. This parameter is defined in accordance with JEDEC Standard 65
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 23. Static Phase Offset - Zero Delay Buffer Mode

1. This parameter is defined in accordance with JEDEC Standard 65B, which defines static phase offset as the time interval between similar points

3.3V. CLKIN0 used as feedback in. frequency = 50MHz. VDDR = VDDOx = 1.8V. 3.3V. CLKIN1 used as feedback in. frequency = 50MHz. VDDR = VDDOx = 1.8V. Table 24. LVCMOS AC/DC Output Characteristics – 1.8V VDDO[1]

1. See Test Loads for additional information.
2. These values are compliant with JESD8-7A.

Table 25. LVCMOS AC/DC Output Characteristics – 2.5V VDDO[1]

1. See Test Loads for additional information.
2. These values are compliant with JESD8-5A.01.

Table 26. LVCMOS AC/DC Output Characteristics – 3.3V VDDO[1]

1. See Test Loads for additional information.
2. These values are compliant with JESD8C.01.

Table 27. LVDS AC/DC Output Characteristics – 1.8V VDDO [1]

1. See Test Loads for additional test conditions.
2. Measured from differential waveform.

Table 28. LVDS AC/DC Output Characteristics – 2.5V/3.3V VDDO [1]

1. See Test Loads for additional test conditions.
2. Measured from differential waveform.

Table 29. LP-HCSL AC/DC Characteristics, Non-PCIe Frequencies – 1.8V VDDO [1]

1. Standard high impedance load with C L= 2pF. See Test Loads
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum variance in VCROSS for any particular
6. Measured from differential waveform.

Table 30. LP-HCSL AC/DC Characteristics, Non-PCIe Frequencies – 2.5V/3.3V VDDO [1]

1. Standard high impedance load with C L= 2pF. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in V CROSS for any
6. Measured from differential waveform.

Table 31. LP-HCSL AC/DC Characteristics, 100MHz PCIe – 1.8V VDDO [1] ΔTR/F Rise/fall matching [3][11] VHIGH set to 800mV. ΔTR/F Rise/fall matching [3][11] VHIGH set to 900mV.

1. Standard high impedance load with C L= 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 7.0 or from relevant x86 processor specifications, whichever
3. Measured from single-ended waveform.
4. Defined as the maximum instantaneous voltage including overshoot.
5. Defined as the minimum instantaneous voltage including undershoot.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
9. Measured from differential waveform.
10. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic

through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 32. LP-HCSL AC/DC Characteristics, 100MHz PCIe – 2.5V/3.3V VDDO [1] ΔTR/F Rise/fall matching [3][11] VHIGH set to 800mV. ΔTR/F Rise/fall matching [3][11] VHIGH set to 900mV.

1. Standard high impedance load with C L= 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 7.0 or from relevant x86 processor specifications, whichever
3. Measured from single-ended waveform.
4. Defined as the maximum instantaneous voltage including overshoot.
5. Defined as the minimum instantaneous voltage including undershoot.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
9. Measured from differential waveform.
10. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic

through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 33. 100MHz PCIe Output Clock Accuracy and SSC

1. The specification limits are taken from either the PCIe Base Specification, Revision 7.0 or from relevant x86 processor specifications, whichever

64GT/s CC mode at any speed.

1. Measured from differential waveform.
2. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000MHz exactly or 100Hz.

to +2800ppm tolerances for data rates ≤16GT/s. Refer to Section 8.6 of the PCIe Base Specification, Revision 7.0.

1. Defined as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread-

100.01 MHz

in SRIS mode, at any speeds.

1. Measurement is made over a 0.5us time interval with a 1st order LPF with an fC of 60x the SSC modulation frequency (1.89MHz for 31.5kHz
2. This is the default value used for all PCIe Common Clock architecture jitter calculations. There are form factors (for example topologies including

long cables) that may exceed this limit. Contact Renesas for assistance calculating jitter if your topology exceeds 12ns.

Table 34. Spread-Spectrum Programmability Table 35. CLKIN Differential Electrical Characteristics[1]

1. This table applies when CLKIN0 or CLKIN1 are used as differential input clocks. If used as single-ended input clocks, the values in the GPO/GPIO
2. This value is 2 x the single-ended amplitude of the CLKIN signal.
3. The correct setting is automatically selected by the RICBox design software.

Table 36. GPI/GPIO Electrical Characteristics – 1.8V VDDD, VDDR, or VDDX[1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer to signals

assignments in Pin Information. For SCL_SCLK, SDA_SDI, see the I2C/SMBus electrical characteristics Table 41 and Table 42.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.
2. These values are compliant with JESD8-7A. These values only apply to XIN_REFIN and XOUT_REFINB when “Input Buffer” mode is selected.

See the Applications section for more details.

Table 37. GPI/GPIO Electrical Characteristics – 2.5V VDDD, VDDR, or VDDX[1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer to signals

assignments in Pin Information. For SCL_SCLK, SDA_SDI, see the I2C/SMBus electrical characteristics Table 41 and Table 42.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.
2. These values are compliant with JESD8-5A.01. These values only apply to XIN_REFIN and XOUT_REFINB when “Input Buffer” mode is selected.

See the Applications section for more details. Table 38. GPI/GPIO Electrical Characteristics – 3.3V VDDD, VDDR, or VDDX[1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer to signals

assignments in Pin Information. For SCL_SCLK, SDA_SDI, see the I2C/SMBus electrical characteristics Table 41 and Table 42.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.
2. These values are compliant with JESD8-5A.01. These values only apply to XIN_REFIN and XOUT_REFINB when “Input Buffer” mode is selected.

See the Applications section for more details. Table 39. CMOS GPI/GPIO Common Electrical Characteristics[1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer to

signals GPIO[4:0], when acting as outputs. For VDD pin mapping, see GPI and GPIO VDD pin assignments in Pin Information.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.

Table 40. Power Supply Current[1]

1. Current consumption figures represent a worst-case consumption with all functions associated with the particular voltage supply enabled and all

see Power Considerations. Outputs are not terminated. Values apply to all voltage levels unless noted.

1. Voltage of the input signal must be appropriate for the V DDR voltage supply level when using a DC-coupled connection. For example, when
2. There are two possible input clock pairs. If both are used, the current for each type must be added together. If the external clock(s) is/are AC-

coupled, the internal DC-bias must be enabled and also added to the total IDDR current.

1. LVPECL and CML input clocks are not supported when V DDR = 1.8V.

OUT[x] and OUT[x]b enabled).

1. I DDO_x denotes the current consumed by each output driver and does not include output divider current. These values are measured at maximum

output frequency, unless otherwise stated (200MHz for LVCMOS outputs and 650MHz for differential outputs).

1. Please refer to the Output Driver and Output Divider VDDO Pin Assignments Table to determine the allocation of IDDO_IOD, IDDO_FOD and IDDO_x

Figure 3. I2C/SMBus Target Timing Diagram Table 41. I2C/SMBus Bus DC Electrical Characteristics [1]

1. V OH is governed by the VPUP, the voltage rail to which the pull up resistors are connected.

Table 42. I2C/SMBus Bus AC Electrical Characteristics device) [6] - N/A, the RC310xxB do not extend the clock low. (controller device) [7] - N/A, the RC310xxB are not bus controllers.

Figure 4. SPI Bus Timing

1. A controller should not drive the clock at a frequency below the minimum fSMB. Further, the operating clock frequency should not be reduced below

that extends the SMBCLK low for data processing of a received byte, data buffering and so forth for longer than 100µs in a non-periodic way.

1. A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the V IH:MIN of the SMBCLK signal) to bridge the

undefined region of the falling edge of SMBCLK.

1. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of
2. The device has the option of detecting a timeout if the SDA_nCS pin is also low for this time.
3. t HIGH:MAX provides a simple guaranteed method for controllers to detect bus idle conditions. A controller can assume that the bus is free if it detects

that the clock and data signals have been high for greater than tHIGH:MAX.

1. t HIGH:MAX provides a simple guaranteed method for controllers to detect bus idle conditions. A controller can assume that the bus is free if it detects

that the clock and data signals have been high for greater than tHIGH:MAX.

1. t LOW:SEXT is the cumulative time a given target device is allowed to extend the clock cycles in one message from the initial START to the STOP.

tLOW:SEXT. Therefore, this parameter is measured with the target device as the sole target of a full-speed controller.

1. The rise and fall time measurement limits are defined as follows:
2. Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

Table 43. SPI Target Interface Electrical Characteristics

1. Adding the extra half period of delay is a register programming option to emulate read data being clocked out on the opposite edge of the SCLK
2. This is the time until the device releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength and PCB trace

Table 44. Power Supply Noise Rejection

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

reached under these conditions.

1. 50mV peak-to-peak sine wave applied injected on indicated power supply pin(s).
2. Noise spur amplitude measured relative to 156.25MHz carrier frequency.
3. Excluding VDDOx of the output being measured.

R31DS0179EU0124 Rev.1.24 Page 43 Feb 3, 2026 RC310xxB Datasheet 3. Functional Description The RC310xxB is a small-form factor, fully integrated, low-power, high performance frequency synthesizer with jitter attenuation and network synchronization capabilities. The device is optimized to deliver excellent phase noise as required for driving Ethernet PHYs/switch, ASICs, or FPGAs. The RC310xxB supports JEDEC JESD204B/C for converter synchronization, JEDEC JESD204B/C converter synchronization, IEEE1588, and SyncE for network-based synchronization. The following sections provide an overview of the RC310xxB.

3.1 Power-Up, Configuration, and Serial Interfaces

The RC310xxB can be powered up and configured in three ways: 1. From 1 of 27 internal non-volatile memory using OTP user configurations (UserCfgs) 2. From its target serial interface 3. From an external I2C EEPROM The RC310xxB supports three target serial interfaces (I2C, SPI, and SMBUS), and one serial host interface (I2C). These interfaces share the same pins, so only one is available at a time.

3.2 Input Clocks

The RC310xxB supports one crystal/reference input that is used as a reference to the analog PLL (APLL) and up to two differential or four single-ended clock inputs that are used as a reference to the digital PLL (DPLL) and support hitless reference switching.

3.2.1 Crystal/Reference Input

The crystal input supports crystal frequencies of 8MHz to 80MHz. It has programmable internal load capacitors to support crystals with CL = 6pF to 12pF. The crystal input may being over-driven with differential or single-ended inputs with proper external terminations. It also supports being over-driven with a clipped sine-wave TCXO with a 0.8VPP signal. The supported frequency range is same as reference clock inputs: 1kHz to 650MHz in differential mode, and 1kHz to 200MHz in single-ended mode. An available LOS monitor detects the loss of signal on crystal input.

3.2.2 Clock Inputs

There are two differential clock inputs that support LVDS, HCSL, or single-ended CMOS logic levels without external terminations. LVPECL or CML clock inputs may be supported with external terminations and/or AC coupling. Internal terminations are available for both HCSL and LVDS logic levels. Additionally, HCSL input terminations support both 100ohm and 85ohm operating environments. If set to single-ended type, the differential inputs turn into two single-ended inputs. CLKIN0 drives clkin0 internally, CLKIN0b drives clkin1 internally. CLKIN1 drives clkin2 internally, and CLKIN1b drives clkin3 internally. If set to differential type, CLKIN0/CLKIN0b pair drives clkin0 while CLKIN1/CLKIN1b pair drives clkin2. Internal biasing is available for AC-coupled applications. The two clock inputs can be left floating when unused. An available LOS monitor detects the loss of signal on crystal input. Frequency monitoring is also available on the clock inputs.

3.3 Clock Input Monitors

There are two types of reference clock monitors. The APLL input is monitored for Loss of Signal (LOS). While the DPLL clock inputs (CLKIN0, CLKIN0B, CLKIN1, CLKIN1B) each have LOS, activity and frequency monitoring. ▪ The LOS monitor detects missing edges over a window of several reference clock periods. For the best accuracy, it is recommended to program the window to be equal to at least 8 times that of the measuring clock period.

R31DS0179EU0124 Rev.1.24 Page 44 Feb 3, 2026 RC310xxB Datasheet ▪ The frequency monitor may be configured to measure the reference over a nominal 5ms time window in order to achieve ~1ppm granularity. ▪ The frequency monitor may be configured to measure the reference over a nominal 0.4s time window in order to achieve ~12ppb granularity.

3.4 APLL

The APLL is fractional LC-VCO based PLL with an operating range from 9.5GHz to 10.7GHz. Any of the available input clocks can be selected to drive the APLL, and the input clock can be frequency doubled for increased performance. The APLL is temperature compensated for the utmost frequency stability. For synchronous, deterministic requirements, the APLL also supports ZDB mode where CLKIN0 is used for the feedback input.

3.4.1 APLL Lock Detector

The APLL lock detector indicates whether the APLL is locked to a functioning crystal or reference input by monitoring the phase errors. Lock status can be sent on to a GPIO pin or in the register map.

3.5 DPLL

To operate as a network synchronizer or jitter attenuator, the DPLL and APLL are nested and form a fractional-N DPLL architecture. The System APLL locks to an input clock from a crystal or a crystal oscillator and generates an output clock of approximately 10GHz. The APLL uses a fractional feedback divider with 26-b numerator and fixed 26-b denominator to generate its feedback clock. The fractional feedback divide ratio is dynamically controlled by the DPLL. The DPLL also uses the APLL’s VCO clock to generate the fractional divided DPLL feedback clock. The DPLL fractional feedback divider, which is comprised of 48-b numerator and 48-b denominator, is static during normal operation. The DPLL can also be optionally disabled to operate the RC31008/31012A in synthesizer/DCO mode.

3.6 DPLL Reference Selection

The DPLL can lock to one of either the two differential or the four single ended input clocks. The reference selection can be either automatic or manual and when enabled, hitless switching results in negligible (< 100ps) output clock initial phase hit during reference switching or the DPLL exiting from holdover.

3.6.1 Manual Reference Selection

In manual mode, the selection is set either by GPIO or GPI pins or in the register map.

3.6.2 Automatic Reference Selection

In automatic mode, the selection is based on clock quality statuses and priorities. The quality statuses are from clock monitors. If two clock inputs are programmed to the same priority, the one with lower index number takes precedence (e.g., clkin0 takes precedence over clkin1). The automatic reference selection can either be revertive or non-revertive. In revertive mode, the reference clock that is qualified and of the highest priority is always selected. If a reference clock of higher priority than the currently selected one becomes qualified, the DPLL will switch to that reference clock; if a reference clock of equal or lower priority than the currently selected one becomes qualified, the DPLL will keep the current reference clock. In non-revertive mode, if there is a higher priority reference clock is coming back (from disqualified to qualified), the current selected reference clock remains selected unless it gets disqualified.

3.6.3 Hitless Reference Switching

If hitless switching is enabled, the output clock initial phase hit will be minimized (< 100ps) during reference switching or the DPLL exiting from holdover, while the input clock and output clock may no longer be aligned. If hitless switching is disabled, the output clock phase change slope is determined by DPLL loop characteristics and phase slope limit.

R31DS0179EU0124 Rev.1.24 Page 45 Feb 3, 2026 RC310xxB Datasheet Minimal initial phase hit of < 100ps can only be met during reference switching when the reference clocks are of same fractional frequency offset. If they are of different fractional frequency offset (up to 200ppm), the output clock phase will track to the new reference clock.

3.7 DPLL Operating Modes

The DPLL can operate in six different states: Free-run, Acquire, Normal, Holdover, Hitless-switch, and Write- frequency. The state transitions can either be manual or automatic.

3.7.1 Free-run

During power-on reset or VCO calibration or in synthesizer mode, the DPLL is in the free-run state. In this state, no reference clock is used and the output clocks are tracking the APLL reference clock.

3.7.2 Acquire

When there is at least one qualified reference, the DPLL will be tracking the selected qualified reference at the acquisition bandwidth and damping factor settings. If the reference clock is disqualified and no other qualified reference clock is available, the DPLL transitions to either the free-run state or the holdover state. When lock- detector detects a lock, DPLL transitions to the normal state.

3.7.3 Normal

In the normal state, the DPLL is tracking the selected reference clock with the normal locking bandwidth and damping factor settings. If the selected reference clock is disqualified, the state machine goes to either the holdover or the free-run state. At a reference switch, the state machine goes via the Holdover state to the Hitless Switch state or the Acquire state.

3.7.4 Holdover

In the holdover state, the DPLL output frequency will be held at the instantaneous value or a value that is low pass filtered and/or restored from the holdover history registers. The initial holdover accuracy is less than 50ppb.

3.7.5 Hitless Switch

At a hitless reference switch or a hitless transition from the holdover state, the DPLL’s TDC will measure the phase offset between the (newly) selected reference clock and the feedback clock, both of which are averaged. This offset is stored in an internal phase offset register. As a result, the output clocks will experience a minimal phase transient due to the reference switch or coming out of holdover. After the hitless switch procedure has finished, the state machine transitions to the Acquire state unless the reference clock fails.

3.7.6 Write Frequency

In the write-frequency mode the DPLL is not tracking any reference clock. The DPLL output frequency offset is directly controlled by preset value in the register map.

3.7.7 Manual Mode

The DPLL operation can be forced to the free-run, holdover, and write-frequency states.

3.8 DPLL Lock Detector

The DPLL lock detector declares lock when the phase from the phase detector remains within a programmable range for a programmable time interval both of which are set in the register map. This indicates that the DPLL is locked to the reference clock input. Once the phase output from the phase detector has been below the lock threshold for half of the programmed lock interval, the internal lock signal is asserted and the normal loop filter bandwidth and damping applied to the DPLL’s loop filter instead of the acquire filter settings.

R31DS0179EU0124 Rev.1.24 Page 46 Feb 3, 2026 RC310xxB Datasheet

3.9 Output Dividers

The RC310xxB provides four integer and three fractional output dividers.

3.9.1 Integer Output Dividers

All four Integer Output Dividers (IOD) are identical. They use a 25-bit divider to provide output frequencies of 1kHz to 650MHz from the VCO clock. Changing IOD values results in an immediate change to the new frequency. Glitch-less squelch and release of the IOD clock is supported. When enabled, this mimics a gapped clock behavior when an IOD frequency is changed.

3.9.1.1 SYSREF Generation

The RC310xxB supports pulse mode SYSREF generation within each IOD and the number of pulses is programmable. Partial SYSREF (generating SYSREF pulses on a subset of the outputs configured for SYSREF) is also supported. The phase of each IOD in the group can be independently adjusted if skew is intended.

3.9.2 Fractional Output Dividers

There are three Fractional Output Dividers (FOD). Each FOD can divide down the VCO clock to provide frequencies from 1kHz to 650MHz. Each FOD is implemented in two stages. The first stage is an 8-bit fractional divider with Digital Control Delay (DCD) correction. The DCD FOD allows a divide down of the VCO clock to 30MHz to 650MHz. A 17-bit second-stage integer divider with minimum divide ratio of 4 and a maximum ratio of 2*(217-1) allows output frequencies lower than 30MHz. For output frequencies above 30MHz, this second-stage divider may be bypassed.

3.9.2.1 Spread-Spectrum Clocking

FOD0 and FOD1 support Spread-Spectrum Clocking (SSC). When SSC is enabled, the spread spectrum engine modulates the FOD divider ratio with a triangular modulation pattern. The modulation can be programmed for either down-spread or center-spread. The SSC modulation frequency can be programmed to a value between 30kHz to 63kHz. The SSC amplitude can be programmed in 0.05% steps to -1.5% for down spread, or ±1.5% for center spread. When turning off SSC, the current modulation cycle completes, returning the output to the non-spreading frequency before the SSC stops.

3.9.2.2 Sync and Phase Adjustment

Each FOD can adjust its output clock phase with a step size of 1/4 VCO period up to about ±20ns. The adjustment can be of either positive or negative directions. IOD phase adjustment is same as FOD phase adjustment but with a step size of one VCO period.

3.9.2.3 Digital Controlled Oscillator (DCO) Mode

In DCO mode, a frequency control word is passed directly from an external processor or FPGA to the DPLL with a step size of 1/240 or 0.91 parts per trillion (ppt) and a full-range of ±244 parts per million (ppm) from the nominal DPLL output frequency. The frequency control word (FCW) is written to a 29-b wide register in two’s-complement and then applied to the DPLL feedback divider. The reference clock inputs are unused in this mode.

3.9.2.4 Numerically Controlled Oscillator (NCO) Mode

In NCO mode, each FOD can adjust its output clock frequency with a step size of 1/234 or 58.21 ppt and is based on incrementing the numerator while holding the 34-b denominator at a fixed value. This frequency change at the output clock is gradual without glitches. The APLL can be in either clock synthesizer/DCO or in jitter attenuator mode.

3.10 Clock Outputs

The RC310xxB supports up to 12 differential or 24 single-ended clock outputs or any combination of differential and single-ended clock outputs. Every differential clock output can be programmed as two single-ended clock outputs.

3.10.1 Output Types

HCSL outputs provide LVPECL and CML-compatible output swing levels by using external AC coupling.

3.10.2 Output Banks

register out_bank_src, according to Table 45. There are up to 12 clock outputs arranged in seven output banks. Each bank sits on its own VDDO (each VDDO also supplies an IOD or FOD according to Table 46). Table 45. Output Bank Source Mapping Table 46. VDD Pin Assignments for Outputs, Integer Output Dividers, and Fractional Output Dividers

4.1 Recommendations for Unused Pins

4.1.1 XIN_REFIN/XOUT_REFINB

XOUT_REFINB are unused, the pins should be left floating with no trace attached.

4.1.2 CLKIN/CLKINb [1:0] Inputs

and CLKINb be connected to static signals, not active signals.

4.1.3 GPIO/GPI Pins

recommended to enable the internal pull-down and add an external 10k resistor to GND.

4.1.4 LVCMOS Outputs

buffer should be set to high impedance state to avoid unnecessary noise generation.

4.1.5 Differential Outputs

output pair should be treated the same, either left floating or terminated.

4.2 CLKIN/CLKINb Clock Inputs Interface

components at the receiver end of the transmission line. Figure 5. Programmable Input Buffer Logical Diagram transmission line environments and this input buffer supports both with no external terminations required.

Figure 6. Input Buffer Behavior by Protocol

4.3 Overdriving the XTAL Interface

4.3.1 XTAL Interface Set to Input Buffer Mode

4.3.2 XTAL Interface in XO Mode, Input Buffer Mode Not Selected

XIN_REFIN/XOUT_REFINb pins. Input buffer mode is preferred as described in section 4.3.1. Table 47. Input Buffer Programming Options for Specific Signaling Protocols

1. In this mode of operation, AC-coupling capacitors must be used to isolate the voltage level of the transmitter from the receiver. The signal must

4.4 Differential Output Terminations

4.4.1 Direct-Coupled LP-HCSL Termination

lines. No external components are needed. Figure 10. Standard HCSL Termination

4.4.2 Direct-Coupled LVDS Termination

as close to the receiver as possible. Figure 11. Standard LVDS Termination

4.4.3 AC-Coupled Differential Terminations for Other Protocols

environment. The RC310xxB supports a differential swing of 1.6V or 1.8V in LP-HCSL mode. Figure 12. AC-Coupling Termination

any or all of the indicated external components in Figure 12 are needed. (AN-891) on the RC310xxB product page for additional information on both re-biasing and amplitude attenuation. Terminations (AN-953) located on the RC310xxB product page. Please contact Renesas for additional support, if necessary.

4.5 Crystal Recommendations

For the latest vendor / frequency recommendations, please contact Renesas.

4.5.1 Choosing Crystals

A crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. oscillator load capacitance with the crystal load capacitance.

4.5.2 Tuning the Crystal Load Capacitor

Figure 13. Crystal Load Capacity Ci1 and Ci2 are on-chip capacitors that are programmable. capacitance values beyond the range of the on-chip programmability. crystal tuning capacitors allows maximum flexibility to accommodate crystals from various manufacturers. with setting 0x00, and can be increased up to 26.8pF with setting 0x3F. The step per bit is 0.42pF. Table 48. XTAL[5:0] Tuning Capacitor

R31DS0179EU0124 Rev.1.24 Page 53 Feb 3, 2026 RC310xxB Datasheet The following equation can be written for this capacitance: CXIN = Ci1 + Cs1 + Ce1 CXOUT = Ci2 + Cs2 + Ce2 The final load capacitance of the crystal: CL = CXIN × CXOUT / (CXIN + CXOUT) It is recommended to set the capacitors to the same value at each crystal pin, meaning: CXIN = CXOUT. Example 1: The crystal load capacitance is specified as 8pF and the stray capacitance at each crystal pin is Cs = 1.5pF and package stray capacitance is Ce = 7pF. Assuming equal capacitance value at XIN and XOUT = 6.72pF. The equation follows: CL = (6.72pF + 7.5pF + 1.5pF)/2 = 7.86pF XTAL[5:0] = 10000

4.6 External I 2C Serial EEPROM Recommendations

An external I2C EEPROM can be used to store configuration data, please contact Renesas for specific recommendations. A specific configuration code is required for the devices to access an external I2C serial EEPROM at power up. See the ordering information.

4.7 Power Considerations

The electrical characteristics tables provide current consumption values for various blocks and output configurations, and can be used to estimate total current consumption for a particular design. The Renesas IC Toolbox, available on the Renesas website, can also be used to estimate current consumption. A quick note on terms used in this section: “power rail” refers to the power connection to a particular VDD pin. This means that different VDD pins might be connected to the same voltage, yet may also be connected to different power rails. We will use “power rail” when discussing power sequencing considerations.

4.7.1 Power Sequencing Considerations

The RC310xxB has no specific power sequencing requirements. The design software may be used to disconnect unused power supply pins in the silicon, which then allows the user to leave these unused supply pins unconnected. These unused pins are then removed from power sequencing considerations. The RC310xxB also has two GPIO functions (PWRGD/PWRDN# or PWRGD/RESTART#) which give the user more control over power up timing in applications environments such as data centers. These environments often need to hold clocks in reset until the devices receiving the clocks have completed their power-up housekeeping and are ready to receive clocks. We discuss operation without this GPIO function first, followed by a discussion with this GPIO function.

4.7.1.1 Power-Up Operation without PWRGD/PWRDN# or PWRGD/RESTART# Function

When PWRGD/PWRDN# or PWRGD/RESTART# is not used, the RC310xxB outputs are gated by the last VDD pin to become valid. See Table 19 for details.

4.7.1.2 Power-Up Using PWRGD/PWRDN# or PWRGD/RESTART#

Using the PWRGD/PWRDN# or PWRGD/RESTART# GPIO configuration gives the user more control over power- up behavior. Holding the pin low, pauses the RC310xxB start-up sequence until the pin is asserted high. This pin should be held low from the very beginning of the power up sequence. The pin function is defined as follows: ▪ PWRGD means Power is Good (active high). Asserting PWRGD/PWRDN# or PWRGD/RESTART# high after all power rails are valid, tells the RC310xxB that power is good, power up completely and begin operation. The first high assertion of PWRGD/PWRDN# loads a new configuration into the device (selected by external pins if there are multiple configurations). Subsequent high assertions of PWRGD/PWRDN# return to the previously loaded configuration.

5.1 VFQFPN ePad Thermal Release Path

between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. Figure 15. P.C. Assembly for Exposed Pad Thermal Release Path – Side View recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. Electrically Enhance Lead frame Base Package, Amkor Technology.

5.2 Thermal Characteristics

Table 49. Thermal Characteristics (48-pin with External Crystal)[1]

1. Assumes ePad is connected to a ground plane using a grid of 25 thermal vias.

Table 50. Thermal Characteristics (40-pin with External Crystal)[1]

1. Assumes ePad is connected to a ground plane using a grid of 16 thermal vias.

Table 51. Thermal Characteristics (48-pin with Internal Crystal)[1]

1. Assumes ePad is connected to a ground plane using a grid of 25 thermal vias.

Table 52. Thermal Characteristics (40-pin with Internal Crystal)[1]

1. Assumes ePad is connected to a ground plane using a grid of 16 thermal vias.

Table 53. Thermal Characteristics (32-pin with Internal Crystal)[1]

1. Assumes ePad is connected to a ground plane using a grid of 4 thermal vias.

R31DS0179EU0124 Rev.1.24 Page 58 Feb 3, 2026 RC310xxB Datasheet 6. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 7. Marking Diagrams ▪ Lines 1 and 2: part number.

• “ddd” indicates preprogrammed device custom configuration dash code. ▪ Line 3:
• “#” indicates the stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. RC31008Bddd RC31012Bddd ▪ Lines 1 and 2: part number.
• “ddd” indicates preprogrammed device custom configuration dash code. ▪ Line 3:
• “#” indicates the stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. RC31005BQdd ddYW** Due to package construction, the marking of the RC31005BQdd is that of the integrated crystal. The “dd” dash-code is encoded in a unique digital register “marking” that is documented in the addendum. The crystal marking is defined as follows: ▪ Line 1: Indicates 68.0MHz crystal frequency. ▪ Line 2: “S” is crystal vendor. “DC” is the date code which is encoded as follows: Last Digit of Year D (Year Code) Month C (Month Code)

1 A 1 A

2 B 2 B

3 C 3 C

4 D 4 D

5 E 5 E

6 F 6 F

7 G 7 G

8 H 8 H

9 J 9 J

0 K 10 K

• - 11 L - - 12 M

Figure 16. Pin 1 Orientation in Tape and Reel Packaging ▪ Lines 1 and 2: part number.

• “dd” indicates preprogrammed device custom configuration dash code. ▪ Line 3:
• “#” indicates the stepping number.
• “YWW” indicates the last digit of the year and work week the part was assembled.
• “**” indicates the lot sequence number
• “$” indicates the mark code. RC31008BQdd RC31008 BQddGL2 #YWW**$ RC31012BQdd ▪ Lines 1 and 2: part number.
• “dd” indicates preprogrammed device custom configuration dash code. ▪ Line 3:
• “#” indicates the stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. RC31012B QddGL3 #YYWW***

Table 54. Ordering Information

1. Tape and Reel pin 1 orientation follows EIA-481-D unless noted.
2. Replace “ddd” or “dd” with the preprogrammed configuration code provided by Renesas in response to a custom configuration request.

R31DS0179EU0124 Rev.1.24 Page 61 Feb 3, 2026 RC310xxB Datasheet 9. Revision History Revision Date Description 1.24 Feb 3, 2026 ▪ Corrected the 100kHz class maximum values for T F and TR in Table 42. In previous releases of this document, the values were incorrectly swapped. 1.23 Nov 3, 2025 ▪ Changed all references to PCIe Base Specification, Revision 6.0 to PCIe Base Specification, Revision 7.0

1.22 Sep 24, 2025 ▪ Added XIN_REFIN/XOUT_REFINB

▪ Updated GPIO/GPI Pins

1.21 Jul 23, 2025 ▪ Fixed some typos in Table 9 and Table 10

▪ Added Choosing Crystals and Tuning the Crystal Load Capacitor

1.20 Jun 4, 2025 ▪ Updated the 11th bullet in Features to “400kHz I2C / SMBus or 20MHz SPI support”

▪ Completed other minor changes

1.19 Feb 11, 2025

▪ Updated front page text to indicate PCIe Gen7 compliance ▪ Changed nOUT0b to OUT0b in Table 1 and Table 2 ▪ Added Table 18 ▪ Updated PCIe Refclk phase jitter tables as follows:

• Added PCIe Gen7 CC and Gen7 IR to the tables
• Listed IR with no SSC (SRNS) separately from IR with SSC (SRIS)
• Separated SSC for the IR parameters according to the PCIe SIG specification
• Separated Clock Generator and Fanout mode additive jitter into separate tables
• Merged VDDO = 1.8V/2.5V/3.3V into single table ▪ Updated t HD:DAT in I2C/SMBus Bus AC Electrical Characteristics from 300ns to 0ns to be compatible with SMBus Specification Version 3.2. Updated footnotes accordingly ▪ Updated Table 42 as follows:
• Changed “master/slave” references to “host/target”
• Removed maximum values of t HIGH
• Corrected Clock/Data Fall Time and Clock/Data Rise Time values

1.18 Jun 24, 2024 ▪ Updated the output duty cycle in Table 27 and Table 28

1.17 Jun 4, 2024 ▪ Updated the packaging information for the 32-LGA package in Ordering Information

1.16 May 1, 2024 ▪ Added Table 35 (CLKIN Differential Electrical Characteristics)

1.15 Apr 5, 2024 ▪ Updated the Configuration and OTP bullets in Features

▪ Added cross-references in Table 1, Table 2, Table 3, Table 4, and Table 5 to Table 8

1.14 Mar 13, 2024 ▪ Updated several part numbers in Ordering Information (RC31012BQ00GL3#BB0,

RC31012BQ00GL3#KB0, RC31012BQ01GL3#BB0, and RC31012BQ01GL3#KB0)

1.13 Feb 15, 2024

▪ Added the internal crystal RC31005BQ, RC31008BQ, and RC31012BQ information to the datasheet ▪ Added BQ orderable part numbers to Ordering Information ▪ Rearranged Ordering Information for readability ▪ Completed other minor changes

1.12 Jan 11, 2024 ▪ Updated the typical and maximum values for t APLL in Table 23

▪ Updated the document to the latest template

1.11 Dec 21, 2023 ▪ Updated Static Phase Offset - Zero Delay Buffer Mode table with characterized values

▪ Moved to final data sheet for RC31012B and RC31008B

1.10 Nov 10, 2023 ▪ Corrected two package links in Ordering Information

1.09 Oct 30, 2023 ▪ Updated the down-spread maximum value in Table 34

▪ Introduced a new document number for the datasheet

1.08 May 31, 2023 ▪ Changed t HOLD to 200uS from 200mS in Figure 14

1.07 May 8, 2023 ▪ Updated the device block diagram in Figure 2

1.06 Apr 14, 2023 ▪ Corrected an RC31005BQ part number in Ordering Information

R31DS0179EU0124 Rev.1.24 Page 62 Feb 3, 2026 RC310xxB Datasheet

1.05 Mar 29, 2023

▪ Updated document for B-rev as follows:

• Updated front page references to B-rev and simplified the block diagram.
• Added RC31012BQ pin out and pin descriptions.
• Added RC11005BQ pin out and pin descriptions.
• Updated ordering information with new devices and revisions.
• Changed ePad outline and ePad text in the Pin Diagrams to grey color to highlight that the view is Top View and the ePad is on the bottom of the package.
• Added thermal data for 005BQ and 012BQ package.
• Corrected all theta ja descriptions from 0, 1, 3, and 5 m/s airflow to 0, 1, 2, and 3 m/s airflow. ▪ Updated Power Considerations for the B-rev silicon. ▪ Added Static Phase Offset - Zero Delay Buffer Mode specification.

1.04 Nov 23, 2022

▪ Added LVCMOS AC/DC characteristics tables (see Table 24 to Table 26). ▪ Completed an extensive update to Power Considerations, specifically power sequencing considerations. ▪ Clarified Overdriving the XTAL Interface.

1.03 Oct 7, 2022

▪ Changed the minimum value for t PU in Table 8. ▪ Revised the condition for t HS in Table 14. ▪ Updated Power Sequencing Considerations. ▪ Updated the Marking Diagrams and Ordering Information, added 01 and 001 dash codes to indicate configurations that load from external I2C EEPROMs. Also updated the table footnotes accordingly. ▪ Removed references to RC31005A pending final qualification. For the latest documentation on this device, please contact Renesas. ▪ Completed other minor changes. 1.02 Sep 6, 2022 ▪ Completed minor updates to various Electrical Characteristics values.

1.01 Aug 9, 2022

▪ Corrected a typo in Pin Assignments. ▪ Completed minor updates to various values in Electrical Characteristics. ▪ Completed other minor changes. 1.00 Jul 25, 2022 Initial release. Revision Date Description

3031 400.35 5.00 ±0.10 5.00 ±0.10 Pin 1 ID TOP VIEW 3.60 ±0.10 3.60 ±0.10 0.40 0.20 (0.30) 0.35 0.200.40 3.60 3.60 4.20 5.30 5.30 (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN PackageOutline 0.40 ±0.10 (0.55 ) BOTTOM VIEW SIDE VIEW © Renesas Electronics Corporation

4.50 ±0.05 BOTTOM VIEW 6.300.200.40 0.55 4.50 4.50 5.20 0.200.406.30 5.20 (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN 0.40 Package Outline 6.00 ±0.10 6.00 ±0.100.20 4.50 ±0.05 CSIDE VIEW 0.35 0.35 0.40 ±0.1012 363748 132425 (0.35) © Renesas Electronics Corporation

RECOMMENDED LAND PATTERN(PCB Top View, NSMD Design) 891617 2425 32 SIDE VIEW 4.00 ±0.10(3.20) (2.50) Pin1 Index (0.37) 1.00 ±0.15C 1.20 0.201.10 8X 0.258X 0.3524X 0.4024X 0.20 0.50 0.45 Seating Plane 3.004.10 1.10 1.200.500.55 0.40 0.25 0.20 0.50 0.45 SoldermaskPackage edge Exposed metalSoldermask openingSoldermask opening A Detail A 0.08C 4.00±0.10 8X 0.125 0.425 0.125 0.20 0.425 0.40 PackageOutline 0.125 © Renesas Electronics Corporation

(PCB Top View, NSMD Design) 5.00 ±0.10 TOP VIEWBOTTOM VIEW SIDE VIEWDetail A RECOMMENDED LAND PATTERN SoldermaskPackage EdgeSoldermask OpeningExposed Metal Pin 1 ID 1.70 ±0.10Seating Plane0.08CC 10112021 303140 0.30 (0.10) A3.03 ±0.101.17 PackageOutline3.03 3.030.20 4.205.100.27 1.17 0.691.17 0.273.03 ±0.10 1.170.400.20 0.450.400.69 5.00 ±0.100.690.69 © Renesas Electronics Corporation

(PCB Top View, Lead pad - NSMD Design; Thermal pad - SMD Design) SIDE VIEWDetail ASoldermaskPackage EdgeSoldermask OpeningExposed Metal 0.3250.200.40A12132325 364837 1.151.15Package Outline 0.20 1.55 0.40 BOTTOM VIEWTOP VIEW RECOMMENDED LAND PATTERN© Renesas Electronics Corporation

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