RC31008A001GNDBB0

RC310XXA RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 Pin Assignments – RCxx012A
• 1.2 Pin Descriptions – RCxx012A
• 1.3 Pin Assignments – RCxx008A
• 1.4 Pin Descriptions – RCxx008A
• 1.5 Pin Assignments – RCxx008AQ
• 1.6 Pin Descriptions – RCxx008AQ
• 1.7 Pin Characteristics
• 2.1 Absolute Maximum Ratings
• 2.2 ESD Ratings
• 2.3 Recommended Operating Conditions
• 2.4 Electrical Characteristics
• 3.1 Power-Up, Configuration, and Serial Interfaces
• 3.2 Input Clocks
• 3.2.1 Crystal/Reference Input
• 3.2.2 Clock Inputs
• 3.3 Clock Input Monitors
• 3.4 APLL
• 3.4.1 APLL Lock Detector
• 3.5 DPLL
• 3.6 DPLL Reference Selection
• 3.6.1 Manual Reference Selection
• 3.6.2 Automatic Reference Selection
• 3.6.3 Hitless Reference Switching
• 3.7 DPLL Operating Modes
• 3.7.1 Free-run
• 3.7.2 Acquire
• 3.7.3 Normal
• 3.7.4 Holdover
• 3.7.5 Hitless Switch
• 3.7.6 Write Frequency
• 3.7.7 Manual Mode
• 3.8 DPLL Lock Detector
• 3.9 Output Dividers
• 3.9.1 Integer Output Dividers
• 3.9.2 Fractional Output Dividers
• 3.10 Clock Outputs
• 3.10.1 Output Types
• 3.10.2 Output Banks
• 4.1 Recommendations for Unused Input and Output Pins
• 4.1.1 CLKIN/CLKINb [1:0] Inputs
• 4.1.2 LVCMOS Control Pins
• 4.1.3 LVCMOS Outputs
• 4.1.4 Differential Outputs

Features

▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ Integrated 100 and 85 LP-HCSL terminations ▪ JESD204B/C support on differential or single- ended outputs with DC-coupling or AC-coupling ▪ Up to four single-ended or two differential clock inputs; one crystal/TCXO/OCXO input ▪ Programmable General Purpose Inputs (GPI × 4) and General Purpose Input/Outputs (GPIO × 5) ▪ 1MHz I2C, 400kHz SMBus, or 20MHz SPI support Configuration via internal One-Time Programmable (OTP) memory (up to 27 different configurations), serial interface, or external I2C EEPROM. ▪ Factory programmable internal OTP ▪ 1.8V, 2.5V, 3.3V, -40° to +85°C operation ▪ RC31012A – 12 differential/24 single-ended outputs

• 6 × 6 × 0.9 mm 48-QFN package ▪ RC31008A – 8 differential/16 single-ended outputs
• 5 × 5 × 0.9 mm 40-QFN package with optional integrated crystal

Figure 1. Typical Wire-line Infrastructure Use Case

Figure 2. RC310xxA Block Diagram

R31DS0010EU0104 Rev.1.04 Page 4 Nov 23, 2022 RC310xxA Datasheet

1.1 Pin Assignments – RCxx012A

1.2 Pin Descriptions – RCxx012A

Table 1. RCxx012A Pin Descriptions 1 VDDA Power Power supply for analog, 1.8/2.5/3.3V supported.

2 XIN_REFIN I Crystal Input or differential reference clock positive input / CMOS single-ended

3 XOUT_REFINb I/O

Crystal Output or differential reference clock negative input. then this pin must be left unconnected.

5 CLKIN0_GPI0 I Differential clock positive input / CMOS single-ended reference clock input or general

6 CLKIN0b_GPI1 I Differential clock negative input / CMOS single-ended reference clock input or general

8 CLKIN1_GPI2 I Differential clock positive input / CMOS single-ended reference clock input or general

9 CLKIN1b_GPI3 I Differential clock negative input / CMOS single-ended reference clock input or general

10 SCL_SCLK I

I2C Mode: I2C interface bi-directional clock.

11 SDA_nCS I

this supply must be 2.5V or 3.3V. 13 GPIO0 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 14 GPIO1 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 15 GPIO2 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 16 GPIO3 I/O General purpose input/output. 17 GPIO4 I/O General purpose input/output. 18 nOUT0b O Output Clock 0 negative. 19 OUT0 O Output Clock 0 positive. 22 OUT1b O Output Clock 1 negative. 23 OUT1 O Output Clock 1 positive. 25 OUT2b O Output Clock 2 negative. 26 OUT2 O Output Clock 2 positive. 27 OUT3b O Output Clock 3 negative. 28 OUT3 O Output Clock 3 positive. 29 OUT4b O Output Clock 4 negative. 30 OUT4 O Output Clock 4 positive. 31 OUT5b O Output Clock 5 negative. 32 OUT5 O Output Clock 5 positive. 33 OUT6b O Output Clock 6 negative. 34 OUT6 O Output Clock 6 positive. 35 OUT7b O Output Clock 7 negative. Table 1. RCxx012A Pin Descriptions (Cont.)

36 OUT7 O Output Clock 7 positive. 38 OUT8b O Output Clock 8 negative. 39 OUT8 O Output Clock 8 positive. 40 OUT9b O Output Clock 9 negative. 41 OUT9 O Output Clock 9 positive. 44 OUT10b O Output Clock 10 negative. 45 OUT10 O Output Clock 10 positive. 46 OUT11b O Output Clock 11 negative. 47 OUT11 O Output Clock 11 positive. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied.

1.3 Pin Assignments – RCxx008A

1.4 Pin Descriptions – RCxx008A

Table 2. RCxx008A Pin Descriptions

1 XIN_REFIN I Crystal Input or differential reference clock positive input / CMOS single-ended

2 XOUT_REFINb I/O

Crystal Output or differential reference clock negative input. then this pin must be left unconnected.

4 CLKIN0_GPI0 I differential clock positive input / CMOS single-ended reference clock input or general

5 CLKIN0b_GPI1 I differential clock negative input / CMOS single-ended reference clock input or

general purpose input pin GPI1.

7 CLKIN1_GPI2 I Differential clock positive input / CMOS single-ended reference clock input or general

8 CLKIN1b_GPI3 I Differential clock negative input / CMOS single-ended reference clock input or

general purpose input pin GPI3.

9 SCL_SCLK I

I2C Mode: I2C interface bi-directional clock.

10 SDA_nCS I/O

I2C Mode: I2C interface bi-directional data in open-drain mode. this supply must be 2.5V or 3.3V. 12 GPIO0 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 13 GPIO1 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 14 GPIO2 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 15 GPIO3 I/O General purpose input/output. 16 GPIO4 I/O General purpose input/output. 19 OUT1b O Output Clock 1 negative.

20 OUT1 O Output Clock 1 positive

22 OUT2b O Output Clock 2 negative. 23 OUT2 O Output Clock 2 positive. 24 OUT3b O Output Clock 3 negative. 25 OUT3 O Output Clock 3 positive. 26 OUT6b O Output Clock 6 negative. 27 OUT6 O Output Clock 6 positive. 28 OUT7b O Output Clock 7 negative. 29 OUT7 O Output Clock 7 positive. 31 OUT8b O Output Clock 8 negative. 32 OUT8 O Output Clock 8 positive. 35 OUT10b O Output Clock 10 negative. 36 OUT10 O Output Clock 10 positive. 37 OUT11b O Output Clock 11 negative. 38 OUT11 O Output Clock 11 positive. 40 VDDA Power Power supply for analog, 1.8/2.5/3.3V supported. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied. Table 2. RCxx008A Pin Descriptions (Cont.)

1.5 Pin Assignments – RCxx008AQ

1.6 Pin Descriptions – RCxx008AQ

Table 3. RCxx008AQ Pin Descriptions 1 DNC N/A Do not connect. This pin should have no stubs. 2 DNC N/A Do not connect. This pin should have no stubs. general purpose input pin GPI1. general purpose input pin GPI3. I2C Mode: I2C interface bi-directional clock.

I2C Mode: I2C interface bi-directional data in open-drain mode. this supply must be 2.5V or 3.3V. 12 GPIO0 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 13 GPIO1 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 14 GPIO2 I/O General purpose input/output. 3-level logic input during power-up and CMOS level logic after unless set to 3-level. 15 GPIO3 I/O General purpose input/output. 16 GPIO4 I/O General purpose input/output. 19 OUT1b O Output Clock 1 negative. 22 OUT2b O Output Clock 2 negative. 23 OUT2 O Output Clock 2 positive. 24 OUT3b O Output Clock 3 negative. 25 OUT3 O Output Clock 3 positive. 26 OUT6b O Output Clock 6 negative. 27 OUT6 O Output Clock 6 positive. 28 OUT7b O Output Clock 7 negative. 29 OUT7 O Output Clock 7 positive. 31 OUT8b O Output Clock 8 negative. 32 OUT8 O Output Clock 8 positive. 35 OUT10b O Output Clock 10 negative. 36 OUT10 O Output Clock 10 positive. 37 OUT11b O Output Clock 11 negative. 38 OUT11 O Output Clock 11 positive. 40 VDDA Power Power supply for analog, 1.8/2.5/3.3V supported. EPAD GND Power Ground. ePad must be connected to ground before any VDD is applied. Table 3. RCxx008AQ Pin Descriptions (Cont.)

1.7 Pin Characteristics

Table 4. Pin Characteristics

1. When used as clock input.

implied. Exposure to absolute maximum rating conditions may affect device reliability.

2.1 Absolute Maximum Ratings

2.2 ESD Ratings

Table 5. Absolute Maximum Ratings

1. VDD refers to the VDD pin that supplies the particular input. To determine to which VDD pin the specification applies, see Table43.
2. This limit only applies when XIN_REFIN/XOUT_REFINb are configured as an “Input Buffer” for use with an external oscillator. No limit

is implied when connected directly to a crystal. Table 6. ESD Ratings

2.3 Recommended Operating Conditions

2.4 Electrical Characteristics

Table 7. Recommended Operating Conditions [1][2]

1. All electrical characteristics are specified over Recommended Operating Conditions unless noted otherwise.
2. All conditions in this table must be met to guarantee device functionality and performance.

reach minimum specified voltage. Table 8. PCIe Refclk Jitter for VDDO = 1.8V [1][2]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 6.0, Revision 0.9. See the Test

table. Equipment noise is removed from all measurements.

1. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a

to peak-to-peak jitter using a multiplication factor of 8.83.

1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 MHz taking care to minimize removal of any
2. Note that 0.7 ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.25 ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. Note that 0.15 ps RMS is to be used in channel simulations to account for additional noise in a real system.
5. The PCI Express Base Specification 6.0, Revision 0.9 provides the filters necessary to calculate SRIS and SRNS jitter values; it does

jitter budget is 150fs RMS. One half of the Refclk jitter budget is 106fs RMS. At the clock input, the system must deliver 250fs RMS. user may choose to use this more relaxed value as the jitter limit.

1. The RMS sum of the source jitter and the additive jitter must be less than the jitter specification listed for the clock generator operating

Table 8. PCIe Refclk Jitter for VDDO = 1.8V [1][2] (Cont.)

Table 9. PCIe Refclk Jitter for VDDO = 2.5V [1][2]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 6.0, Revision 0.9. See the Test

table. Equipment noise is removed from all measurements.

1. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a

to peak-to-peak jitter using a multiplication factor of 8.83.

1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 MHz taking care to minimize removal of any
2. Note that 0.7 ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.25 ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. Note that 0.15 ps RMS is to be used in channel simulations to account for additional noise in a real system.
5. The PCI Express Base Specification 6.0, Revision 0.9 provides the filters necessary to calculate SRIS and SRNS jitter values; it does

jitter budget is 150fs RMS. One half of the Refclk jitter budget is 106fs RMS. At the clock input, the system must deliver 250fs RMS. user may choose to use this more relaxed value as the jitter limit.

1. The RMS sum of the source jitter and the additive jitter must be less than the jitter specification listed for the clock generator operating

Table 10. PCIe Refclk Jitter for VDDO = 3.3V [1][2] Table 9. PCIe Refclk Jitter for VDDO = 2.5V [1][2] (Cont.)

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 6.0, Revision 0.9. See the “Test

table. Equipment noise is removed from all measurements.

1. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a

converted to peak-to-peak jitter using a multiplication factor of 8.83. Table 10. PCIe Refclk Jitter for VDDO = 3.3V [1][2] (Cont.)

1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any
2. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
5. The PCI Express Base Specification 6.0, Revision 0.9 provides the filters necessary to calculate SRIS and SRNS jitter values; it does

jitter budget is 150fs RMS. One half of the Refclk jitter budget is 106fs RMS. At the clock input, the system must deliver 250fs RMS. user may choose to use this more relaxed value as the jitter limit.

1. The RMS sum of the source jitter and the additive jitter must be less than the jitter specification listed for the clock generator operating

Table 11. Phase Jitter and Phase Noise – 1.8V VDDO [1][2]

2 Outputs

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Characterized using a Rohde and Schwarz SMA100 overdriving the XTAL interface.

Table 12. Phase Jitter and Phase Noise – 2.5V VDDO [1][2] Table 11. Phase Jitter and Phase Noise – 1.8V VDDO [1][2] (Cont.)

Table 12. Phase Jitter and Phase Noise – 2.5V VDDO [1][2] (Cont.)

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Characterized using a Rohde and Schwarz SMA100 overdriving the XTAL interface.

Table 13. Phase Jitter and Phase Noise – 3.3V VDDO [1][2]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Characterized using a Rohde and Schwarz SMA100 overdriving the XTAL interface.

Table 14. Jitter Attenuator and Network Synchronization [1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. This parameter will vary with the quality of the TDC and system DPLL references. The typical value shown assumes an ideal reference

is used as input to the TDC and system DPLL. Table 13. Phase Jitter and Phase Noise – 3.3V VDDO [1][2] (Cont.)

Table 15. Clock Input Frequencies [1]

1. For crystal characteristics, see Table 16.

Table 16. External Crystal Characteristics

1. These parameters are required, regardless of crystal used.
2. These parameters are customer/application dependent. Common maximum values are FTOL = ±20ppm, FSTAB = ±20ppm, and Aging

= ±5ppm/10years. The customer is free to adjust these parameters to their particular requirements. Table 17. Internal Crystal Characteristics (AQ Versions Only)

Table 18. Output Frequencies and Startup Times [1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output. A stable

considerations, see Power Considerations.

1. Start-up time will depend on the actual configuration used. For more information, please contact Renesas technical support.

Table 19. Output-to-Output, Input-to-Output Skew – LP-HCSL Outputs 1.8V/2.5V/3.3V VDDO [1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
2. This parameter is defined in accordance with JEDEC Standard 65
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 20. Output-to-Output, Input-to-Output Skew – LVDS Outputs 1.8V/2.5V/3.3V VDDO [1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
2. This parameter is defined in accordance with JEDEC Standard 65
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 21. Output-to-Output, Input-to-Output Skew – LVCMOS Outputs 1.8V/2.5V/3.3V VDDO [1]

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. Defined as the time between the rising edges of two outputs of the same frequency, configuration, loading, and supply voltage.
2. This parameter is defined in accordance with JEDEC Standard 65
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 22. LVCMOS AC/DC Output Characteristics - 1.8V VDDO[1]

1. See Test Loads for additional information.
2. These values are compliant with JESD8-7A.

Table 23. LVCMOS AC/DC Output Characteristics - 2.5V VDDO[1]

1. See Test Loads for additional information.
2. These values are compliant with JESD8-5A.01.

Table 24. LVCMOS AC/DC Output Characteristics - 3.3V VDDO[1]

1. See Test Loads for additional information.
2. These values are compliant with JESD8C.01.

Table 25. LVDS AC/DC Output Characteristics – 1.8V VDDO [1]

1. See Test Loads for additional test conditions.

Table 24. LVCMOS AC/DC Output Characteristics - 3.3V VDDO[1] (Cont.)

Table 26. LVDS AC/DC Output Characteristics – 2.5V/3.3V VDDO [1]

1. See Test Loads for additional test conditions.

Table 27. LP-HCSL AC/DC Characteristics, Non-PCIe Frequencies – 1.8V VDDO [1]

1. Standard high impedance load with CL= 2pF. See Test Loads
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum variance in VCROSS for any
2. Measured from differential waveform.

Table 28. LP-HCSL AC/DC Characteristics, Non-PCIe Frequencies – 2.5V/3.3V VDDO [1]

1. Standard high impedance load with CL= 2pF. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS
2. Measured from differential waveform.

Table 29. LP-HCSL AC/DC Characteristics, 100MHz PCIe – 1.8V VDDO [1]

1. Standard high impedance load with CL= 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 6.0 or from relevant x86 processor specifications,

whichever is more stringent.

1. Measured from single-ended waveform.
2. Defined as the maximum instantaneous voltage including overshoot.
3. Defined as the minimum instantaneous voltage including undershoot.
4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance

in VCROSS for any particular system.

1. Measured from differential waveform.
2. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be
3. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered

Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 30. LP-HCSL AC/DC Characteristics, 100MHz PCIe – 2.5V/3.3V VDDO [1] ΔTR/F Rise/fall matching [3][11] VHIGH set to 800mV. ΔTR/F Rise/fall matching [3][11] VHIGH set to 900mV.

1. Standard high impedance load with CL= 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 6.0 or from relevant x86 processor specifications,

whichever is more stringent.

1. Measured from single-ended waveform.

1. Defined as the maximum instantaneous voltage including overshoot.
2. Defined as the minimum instantaneous voltage including undershoot.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance

in VCROSS for any particular system.

1. Measured from differential waveform.
2. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be
3. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered

Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 31. 100MHz PCIe Output Clock Accuracy and SSC

100.01 MHz

1. The specification limits are taken from either the PCIe Base Specification Revision 6.0 or from relevant x86 processor specifications,

whichever is more stringent.

1. Measured from differential waveform.
2. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000MHz exactly

PCI Express Base Specification, Revision 6.0.

1. Defined as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and

tolerances for data rates ≤16GT/s.

1. Measurement is made over a 0.5us time interval with a 1st order LPF with an fC of 60x the SSC modulation frequency (1.89MHz for

31.5kHz modulation frequency).

1. This is the default value used for all PCIe Common Clock architecture jitter calculations. There are form factors (for example topologies

including long cables) that may exceed this limit. Contact Renesas for assistance calculating jitter if your topology exceeds 12ns. Table 32. Spread-Spectrum Programmability Table 31. 100MHz PCIe Output Clock Accuracy and SSC (Cont.)

Table 33. GPI/GPIO Electrical Characteristics – 1.8V VDDD, VDDR, or VDDX [1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer

VDD pin assignments in Pin Information. For SCL_SCLK, SDA_SDI, see the I2C/SMBus electrical characteristics Table 38 and Table 39.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.
2. These values are compliant with JESD8-7A. These values only apply to XIN_REFIN and XOUT_REFINB when “Input Buffer” mode is

selected. See the Applications section for more details. Table 34. GPI/GPIO Electrical Characteristics – 2.5V VDDD, VDDR, or VDDX [1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer

VDD pin assignments in Pin Information. For SCL_SCLK, SDA_SDI, see the I2C/SMBus electrical characteristics Table 38 and Table 39.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.
2. These values are compliant with JESD8-5A.01. These values only apply to XIN_REFIN and XOUT_REFINB when “Input Buffer” mode

is selected. See the Applications section for more details.

Table 35. GPI/GPIO Electrical Characteristics – 3.3V VDDD, VDDR, or VDDX [1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer

VDD pin assignments in Pin Information. For SCL_SCLK, SDA_SDI, see the I2C/SMBus electrical characteristics Table 38 and Table 39.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.
2. These values are compliant with JESD8-5A.01. These values only apply to XIN_REFIN and XOUT_REFINB when “Input Buffer” mode

is selected. See the Applications section for more details. Table 36. CMOS GPI/GPIO Common Electrical Characteristics [1][2]

1. Input specifications refer to signals XIN_REFIN, XOUT_REFINb, GPI[3:0], GPIO[4:0], when acting as inputs. Output specifications refer

to signals GPIO[4:0], when acting as outputs. For VDD pin mapping, see GPI and GPIO VDD pin assignments in Pin Information.

1. CLKIN[1:0]/CLKIN[1:0]b used as two single-ended clocks rather than as a differential clock.

Table 37. Power Supply Current [1]

1. Current consumption figures represent a worst-case consumption with all functions associated with the particular voltage supply
2. Voltage of the input signal must be appropriate for the VDDR voltage supply level when using a DC-coupled connection. For example,
3. There are two possible input clock pairs. If both are used, the current for each type must be added together. If the external clock(s) is/are

AC-coupled, the internal DC-bias must be enabled and also added to the total IDDR current.

1. LVPECL and CML input clocks are not supported when VDDR = 1.8V.
2. IDDO_x denotes the current consumed by each output driver and does not include output divider current. These values are measured at

maximum output frequency, unless otherwise stated (200MHz for LVCMOS outputs and 650MHz for differential outputs).

1. Please refer to the Output Driver and Output Divider VDDO Pin Assignments Table to determine the allocation of IDDO_IOD, IDDO_FOD

and IDDO_x to each VDDO pin. Table 37. Power Supply Current [1] (Cont.)

Figure 3. I2C/SMBus Slave Timing Diagram Table 38. I2C/SMBus Bus DC Electrical Characteristics [1]

1. VOH is governed by the VPUP, the voltage rail to which the pull up resistors are connected.

Table 39. I2C/SMBus Bus AC Electrical Characteristics

(slave device) [7] - N/A, the RC310xxA do not extend the clock low. (master device) [8] - N/A, the RC310xxA are not bus masters.

1. A master shall not drive the clock at a frequency below the minimum fSMB. Further, the operating clock frequency shall not be reduced

Specification. This limit does not apply to the bus idle condition, and this limit is independent from the tLOW:SEXT and tLOW:MEXT limits. forth for longer than 100µs in a non-periodic way.

1. A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the VIH:MIN of the SMBCLK signal) to bridge

the undefined region of the falling edge of SMBCLK.

1. Slave devices may have caused other slave devices to hold SDA low. The maximum time that a device can hold SMBDAT low after the
2. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the

timeout holds the SMBCLK low for tTIMEOUT:MAX or longer.

1. The device has the option of detecting a timeout if the SDA_nCS pin is also low for this time.
2. tHIGH:MAX provides a simple guaranteed method for masters to detect bus idle conditions. A master can assume that the bus is free if it

detects that the clock and data signals have been high for greater than tHIGH:MAX.

1. tHIGH:MAX provides a simple guaranteed method for masters to detect bus idle conditions. A master can assume that the bus is free if it

detects that the clock and data signals have been high for greater than tHIGH:MAX.

1. tLOW:SEXT is the cumulative time a given slave device is allowed to extend the clock cycles in one message from the initial START to the

greater than tLOW:SEXT. Therefore, this parameter is measured with the slave device as the sole target of a full-speed master.

1. The rise and fall time measurement limits are defined as follows:
2. Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

Table 39. I2C/SMBus Bus AC Electrical Characteristics (Cont.)

Figure 4. SPI Bus Timing Table 40. SPI Slave Interface Electrical Characteristics

1. Adding the extra half period of delay is a register programming option to emulate read data being clocked out on the opposite edge of
2. This is the time until the device releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength and PCB

Table 41. Power Supply Noise Rejection

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

equilibrium has been reached under these conditions.

1. 50mV peak-to-peak sine wave applied injected on indicated power supply pin(s).
2. Noise spur amplitude measured relative to 156.25MHz carrier frequency.
3. Excluding VDDOx of the output being measured.

R31DS0010EU0104 Rev.1.04 Page 45 Nov 23, 2022 RC310xxA Datasheet 3. Functional Description The RC310xxA is a small-form factor, fully integrated, low-power, high performance frequency synthesizer with jitter attenuation and network synchronization capabilities. The device is optimized to deliver excellent phase noise as required for driving Ethernet PHYs/switch, ASICs, or FPGAs. The RC310xxA supports JEDEC JESD204B/C for converter synchronization, JEDEC JESD204B/C converter synchronization, IEEE1588, and SyncE for network-based synchronization. The following sections provide an overview of the RC310xxA.

3.1 Power-Up, Configuration, and Serial Interfaces

The RC310xxA can be powered up and configured in three ways: 1. From 1 of 27 internal non-volatile memory using OTP user configurations (UserCfgs) 2. From its slave serial interface 3. From an external I2C EEPROM The RC310xxA supports three slave serial interfaces (I2C, SPI, and SMBUS), and one serial master interface (I2C). These interfaces share the same pins, so only one is available at a time.

3.2 Input Clocks

The RC310xxA supports one crystal/reference input that is used as a reference to the analog PLL (APLL) and up to two differential or four single-ended clock inputs that are used as a reference to the digital PLL (DPLL) and support hitless reference switching.

3.2.1 Crystal/Reference Input

The crystal input supports crystal frequencies of 8MHz to 80MHz. It has programmable internal load capacitors to support crystals with CL = 6pF to 12pF. The crystal input may being over-driven with differential or single-ended inputs with proper external terminations. It also supports being over-driven with a clipped sine-wave TCXO with a 0.8VPP signal. The supported frequency range is same as reference clock inputs: 1kHz to 650MHz in differential mode, and 1kHz to 200MHz in single-ended mode. An available LOS monitor detects the loss of signal on crystal input.

3.2.2 Clock Inputs

There are two differential clock inputs that support LVDS, HCSL, or single-ended CMOS logic levels without external terminations. LVPECL or CML clock inputs may be supported with external terminations and/or AC coupling. Internal terminations are available for both HCSL and LVDS logic levels. Additionally, HCSL input terminations support both 100ohm and 85ohm operating environments. If set to single-ended type, the differential inputs turn into two single-ended inputs. CLKIN0 drives clkin0 internally, CLKIN0b drives clkin1 internally. CLKIN1 drives clkin2 internally, and CLKIN1b drives clkin3 internally. If set to differential type, CLKIN0/CLKIN0b pair drives clkin0 while CLKIN1/CLKIN1b pair drives clkin2. Internal biasing is available for AC-coupled applications. The two clock inputs can be left floating when unused. An available LOS monitor detects the loss of signal on crystal input. Frequency monitoring is also available on the clock inputs.

R31DS0010EU0104 Rev.1.04 Page 46 Nov 23, 2022 RC310xxA Datasheet

3.3 Clock Input Monitors

There are two types of reference clock monitors. The APLL input is monitored for Loss of Signal (LOS). While the DPLL clock inputs (CLKIN0, CLKIN0B, CLKIN1, CLKIN1B) each have LOS, activity and frequency monitoring. ▪ The LOS monitor detects missing edges over a window of several reference clock periods. For the best accuracy, it is recommended to program the window to be equal to at least 8 times that of the measuring clock period. ▪ The frequency monitor may be configured to measure the reference over a nominal 5ms time window in order to achieve ~1ppm granularity. ▪ The frequency monitor may be configured to measure the reference over a nominal 0.4s time window in order to achieve ~12ppb granularity.

3.4 APLL

The APLL is fractional LC-VCO based PLL with an operating range from 9.5GHz to 10.7GHz. Any of the available input clocks can be selected to drive the APLL, and the input clock can be frequency doubled for increased performance. The APLL is temperature compensated for the utmost frequency stability. For synchronous, deterministic requirements, the APLL also supports ZDB mode where CLKIN0 is used for the feedback input.

3.4.1 APLL Lock Detector

The APLL lock detector indicates whether the APLL is locked to a functioning crystal or reference input by monitoring the phase errors. Lock status can be sent on to a GPIO pin or in the register map.

3.5 DPLL

To operate as a network synchronizer or jitter attenuator, the DPLL and APLL are nested and form a fractional-N DPLL architecture. The System APLL locks to an input clock from a crystal or a crystal oscillator and generates an output clock of approximately 10GHz. The APLL uses a fractional feedback divider with 26-b numerator and fixed 26-b denominator to generate its feedback clock. The fractional feedback divide ratio is dynamically controlled by the DPLL. The DPLL also uses the APLL’s VCO clock to generate the fractional divided DPLL feedback clock. The DPLL fractional feedback divider, which is comprised of 48-b numerator and 48-b denominator, is static during normal operation. The DPLL can also be optionally disabled to operate the RC31008/31012A in synthesizer/DCO mode.

3.6 DPLL Reference Selection

The DPLL can lock to one of either the two differential or the four single ended input clocks. The reference selection can be either automatic or manual and when enabled, hitless switching results in negligible (< 100ps) output clock initial phase hit during reference switching or the DPLL exiting from holdover.

3.6.1 Manual Reference Selection

In manual mode, the selection is set either by GPIO or GPI pins or in the register map.

3.6.2 Automatic Reference Selection

In automatic mode, the selection is based on clock quality statuses and priorities. The quality statuses are from clock monitors. If two clock inputs are programmed to the same priority, the one with lower index number takes precedence (e.g., clkin0 takes precedence over clkin1). The automatic reference selection can either be revertive or non-revertive. In revertive mode, the reference clock that is qualified and of the highest priority is always selected. If a reference clock of higher priority than the currently selected one becomes qualified, the DPLL will switch to that reference clock; if a reference clock of equal or lower priority than the currently selected one becomes qualified, the DPLL will keep the current reference clock.

R31DS0010EU0104 Rev.1.04 Page 47 Nov 23, 2022 RC310xxA Datasheet In non-revertive mode, if there is a higher priority reference clock is coming back (from disqualified to qualified), the current selected reference clock remains selected unless it gets disqualified.

3.6.3 Hitless Reference Switching

If hitless switching is enabled, the output clock initial phase hit will be minimized (< 100ps) during reference switching or the DPLL exiting from holdover, while the input clock and output clock may no longer be aligned. If hitless switching is disabled, the output clock phase change slope is determined by DPLL loop characteristics and phase slope limit. Minimal initial phase hit of < 100ps can only be met during reference switching when the reference clocks are of same fractional frequency offset. If they are of different fractional frequency offset (up to 200ppm), the output clock phase will track to the new reference clock.

3.7 DPLL Operating Modes

The DPLL can operate in six different states: Free-run, Acquire, Normal, Holdover, Hitless-switch, and Write- frequency. The state transitions can either be manual or automatic.

3.7.1 Free-run

During power-on reset or VCO calibration or in synthesizer mode, the DPLL is in the free-run state. In this state, no reference clock is used and the output clocks are tracking the APLL reference clock.

3.7.2 Acquire

When there is at least one qualified reference, the DPLL will be tracking the selected qualified reference at the acquisition bandwidth and damping factor settings. If the reference clock is disqualified and no other qualified reference clock is available, the DPLL transitions to either the free-run state or the holdover state. When lock- detector detects a lock, DPLL transitions to the normal state.

3.7.3 Normal

In the normal state, the DPLL is tracking the selected reference clock with the normal locking bandwidth and damping factor settings. If the selected reference clock is disqualified, the state machine goes to either the holdover or the free-run state. At a reference switch, the state machine goes via the Holdover state to the Hitless Switch state or the Acquire state.

3.7.4 Holdover

In the holdover state, the DPLL output frequency will be held at the instantaneous value or a value that is low pass filtered and/or restored from the holdover history registers. The initial holdover accuracy is less than 50ppb.

3.7.5 Hitless Switch

At a hitless reference switch or a hitless transition from the holdover state, the DPLL’s TDC will measure the phase offset between the (newly) selected reference clock and the feedback clock, both of which are averaged. This offset is stored in an internal phase offset register. As a result, the output clocks will experience a minimal phase transient due to the reference switch or coming out of holdover. After the hitless switch procedure has finished, the state machine transitions to the Acquire state unless the reference clock fails.

3.7.6 Write Frequency

In the write-frequency mode the DPLL is not tracking any reference clock. The DPLL output frequency offset is directly controlled by preset value in the register map.

3.7.7 Manual Mode

The DPLL operation can be forced to the free-run, holdover, and write-frequency states.

R31DS0010EU0104 Rev.1.04 Page 48 Nov 23, 2022 RC310xxA Datasheet

3.8 DPLL Lock Detector

The DPLL lock detector declares lock when the phase from the phase detector remains within a programmable range for a programmable time interval both of which are set in the register map. This indicates that the DPLL is locked to the reference clock input. Once the phase output from the phase detector has been below the lock threshold for half of the programmed lock interval, the internal lock signal is asserted and the normal loop filter bandwidth and damping applied to the DPLL’s loop filter instead of the acquire filter settings.

3.9 Output Dividers

The RC310xxA provides four integer and three fractional output dividers.

3.9.1 Integer Output Dividers

All four Integer Output Dividers (IOD) are identical. They use a 25-bit divider to provide output frequencies of 1kHz to 650MHz from the VCO clock. Changing IOD values results in an immediate change to the new frequency. Glitch-less squelch and release of the IOD clock is supported. When enabled, this mimics a gapped clock behavior when an IOD frequency is changed.

3.9.1.1 SYSREF Generation

The RC310xxA supports pulse mode SYSREF generation within each IOD and the number of pulses is programmable. Partial SYSREF (generating SYSREF pulses on a subset of the outputs configured for SYSREF) is also supported. The phase of each IOD in the group can be independently adjusted if skew is intended.

3.9.2 Fractional Output Dividers

There are three Fractional Output Dividers (FOD). Each FOD can divide down the VCO clock to provide frequencies from 1kHz to 650MHz. Each FOD is implemented in two stages. The first stage is an 8-bit fractional divider with Digital Control Delay (DCD) correction. The DCD FOD allows a divide down of the VCO clock to 30MHz to 650MHz. A 17-bit second-stage integer divider with minimum divide ratio of 4 and a maximum ratio of 2*(217-1) allows output frequencies lower than 30MHz. For output frequencies above 30MHz, this second-stage divider may be bypassed.

3.9.2.1 Spread-Spectrum Clocking

FOD0 and FOD1 support Spread-Spectrum Clocking (SSC). When SSC is enabled, the spread spectrum engine modulates the FOD divider ratio with a triangular modulation pattern. The modulation can be programmed for either down-spread or center-spread. The SSC modulation frequency can be programmed to a value between 30kHz to 63kHz. The SSC amplitude can be programmed in 0.05% steps to -1.5% for down spread, or ±1.5% for center spread. When turning off SSC, the current modulation cycle completes, returning the output to the non-spreading frequency before the SSC stops.

3.9.2.2 Sync and Phase Adjustment

Each FOD can adjust its output clock phase with a step size of 1/4 VCO period up to about ±20ns. The adjustment can be of either positive or negative directions. IOD phase adjustment is same as FOD phase adjustment but with a step size of one VCO period.

3.9.2.3 Digital Controlled Oscillator (DCO) Mode

In DCO mode, a frequency control word is passed directly from an external processor or FPGA to the DPLL with a step size of 1/240 or 0.91 parts per trillion (ppt) and a full-range of ±244 parts per million (ppm) from the nominal DPLL output frequency. The frequency control word (FCW) is written to a 29-b wide register in two’s-complement and then applied to the DPLL feedback divider. The reference clock inputs are unused in this mode.

3.9.2.4 Numerically Controlled Oscillator (NCO) Mode

3.10 Clock Outputs

3.10.1 Output Types

HCSL outputs provide LVPECL and CML-compatible output swing levels by using external AC coupling.

3.10.2 Output Banks

register out_bank_src, according to Table 42. There are up to 12 clock outputs arranged in seven output banks. Each bank sits on its own VDDO (each VDDO also supplies an IOD or FOD according to Table 43). Table 42. Output Bank Source Mapping Table 43. VDD Pin Assignments for Outputs, Integer Output Dividers, and Fractional Output Dividers

4.1 Recommendations for Unused Input and Output Pins

4.1.1 CLKIN/CLKINb [1:0] Inputs

and CLKINb be connected to static signals, not active signals.

4.1.2 LVCMOS Control Pins

may be added for additional protection. A 10k resistor can be used.

4.1.3 LVCMOS Outputs

buffer should be set to high impedance state to avoid unnecessary noise generation.

4.1.4 Differential Outputs

output pair should be treated the same, either left floating or terminated.

4.2 CLKIN/CLKINb Clock Input Interface

components at the receiver end of the transmission line. Figure 5. Programmable Input Buffer Logical Diagram transmission line environments and this input buffer supports both with no external terminations required.

Figure 6. Input Buffer Behavior by Protocol

4.3 Overdriving the XTAL Interface

4.3.1 XTAL Interface Set to Input Buffer Mode

4.3.2 XTAL Interface in XO Mode, Input Buffer Mode Not Selected

XIN_REFIN/XOUT_REFINb pins. Input buffer mode is preferred as described in section 4.3.1. Table 44. Input Buffer Programming Options for Specific Signaling Protocols

1. In this mode of operation, AC-coupling capacitors must be used to isolate the voltage level of the transmitter from the receiver. The signal

coupling capacitors and the RC310xxA.

4.4 Differential Output Terminations

4.4.1 Direct-Coupled LP-HCSL Termination

lines. No external components are needed. Figure 10. Standard HCSL Termination

4.4.2 Direct-Coupled LVDS Termination

as close to the receiver as possible. Figure 11. Standard LVDS Termination

4.4.3 AC-Coupled Differential Terminations for Other Protocols

environment. The RC310xxA supports a differential swing of 1.6V or 1.8V in LP-HCSL mode. any or all of the indicated external components in Figure 12 are needed. (AN-891) on the RC310xxA product page for additional information on both re-biasing and amplitude attenuation. Terminations (AN-953) located on the RC310xxA product page. Please contact Renesas for additional support, if necessary.

Figure 12. AC-Coupling Termination

4.5 Crystal Recommendations

For the latest vendor / frequency recommendations, please contact Renesas.

4.6 External I2C Serial EEPROM Recommendations

EEPROM at power up. See the ordering information.

4.7 Power Considerations

Toolbox, available on the Renesas website, can also be used to estimate current consumption. power rails. We will use “power rail” when discussing power sequencing considerations.

4.7.1 Power Sequencing Considerations

where multiple supply rails are used, meeting these considerations requires a bit of planning. PWRGD/PWRDN# or PWRGD/RESTART# function. Both scenarios are discussed in the following sections.

4.7.1.1 Power-Up Operation without PWRGD/PWRDN# or PWRGD/RESTART# Function

operating from the same voltage. Logic powered by the VDDA/VDDD pins controls the internal reset sequencer. means the VDDO rails may ramp at the same time as the VDDA/VDDD rails, or may be delayed as much as 4ms. power supply timing requirements without the PWRGD/PWRDN# or PWRGD/RESTART# function.

Figure 13. Power Supply Sequencing without PWRGD/PWRDN# or PWRGD/RESTART#

4.7.1.2 Power-Up Using PWRGD/PWRDN# or PWRGD/RESTART#

high resumes the previous operating state. not be different from the one used before RESTART# asserted low. the power-up sequence for any VDDO that cannot be valid within the MAX tVDDODLY requirement of Figure 13.

Figure 14. Power Supply Sequencing Recommendations Using PWRGD/PWRDN# or PWRGD/RESTART#

5.1 VFQFPN ePad Thermal Release Path

between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. Figure 15. P.C. Assembly for Exposed Pad Thermal Release Path – Side View recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. Electrically Enhance Lead frame Base Package, Amkor Technology.

5.2 Thermal Characteristics

Table 45. Thermal Characteristics (48-pin) [1]

1. Multi-Layer PCB with two ground and two voltage planes.
2. Assumes ePad is connected to a ground plane using a grid of 25 thermal vias.

Table 46. Thermal Characteristics (40-pin with External Crystal) [1]

1. Multi-Layer PCB with two ground and two voltage planes.
2. Assumes ePad is connected to a ground plane using a grid of 16 thermal vias.

Table 47. Thermal Characteristics (40-pin with Internal Crystal) [1]

1. Multi-Layer PCB with two ground and two voltage planes.
2. Assumes ePad is connected to a ground plane using a grid of 16 thermal vias.

R31DS0010EU0104 Rev.1.04 Page 59 Nov 23, 2022 RC310xxA Datasheet 6. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 7. Marking Diagrams [1] 1. The use of “000” / “001” or “00” / “01” for “ddd” and “dd” in the marking diagrams denotes unprogrammed parts. ▪ Lines 1 and 2: part number.

• “ddd” indicates preprogrammed device custom configuration dash code. ▪ Line 3:
• “#” indicates the stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. RC31008Addd RC31012Addd ▪ Lines 1 and 2: part number.
• “ddd” indicates preprogrammed device custom configuration dash code. ▪ Line 3:
• “#” indicates the stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. RC31008 AdddGND #YYWW$ LOT RC31012A dddGNA #YYWW$ LOT ▪ Lines 1 and 2: part number.
• “dd” indicates preprogrammed device custom configuration dash code. ▪ Line 3:
• “#” indicates the stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. RC31008AQdd RC31008 AQddGL2 #YYWW$ LOT

Figure 16. Pin 1 Orientation in Tape and Reel Packaging

R31DS0010EU0104 Rev.1.04 Page 61 Nov 23, 2022 RC310xxA Datasheet 9. Revision History RC31012A000GNA#BB0 12-output un-programmed part with external crystal. I2C address is 0x09. Tray 6 × 6 × 0.9 mm, 48-VFQFPN -40° to +85°C RC31012A000GNA#KB0 Tape and Reel, Pin 1 Orientation: EIA-481-D RC31012AdddGNA#BB0 [2] 12-output pre-programmed part with external crystal Tray RC31012AdddGNA#KB0 [2] Tape and Reel, Pin 1 Orientation: EIA-481-D supplies, please contact Renesas. 2. Replace “ddd” or “dd” with the pre-programmed configuration code provided by Renesas in response to a custom configuration request. Revision Date Description

1.04 Nov 23, 2022

▪ Added LVCMOS AC/DC characteristics tables (see Table 22 to Table 24). ▪ Completed an extensive update to Power Considerations, specifically power sequencing considerations ▪ Clarified Overdriving the XTAL Interface

1.03 Oct 7, 2022

▪ Changed the minimum value for tPU in Table 7 ▪ Revised the condition for tHS in Table 14 ▪ Updated Power Sequencing Considerations ▪ Updated the Marking Diagrams and Ordering Information, added 01 and 001 dash codes to indicate configurations that load from external I2C EEPROMs. Also updated the table footnotes accordingly. ▪ Removed references to RC31005A pending final qualification. For the latest documentation on this device, please contact Renesas. ▪ Completed other minor changes

1.02 Sep 6, 2022 ▪ Completed minor updates to various Electrical Characteristics values

1.01 Aug 9, 2022

▪ Corrected a typo in Pin Assignments – RCxx012A ▪ Completed minor updates to various values in Electrical Characteristics ▪ Completed other minor changes 1.00 Jul 25, 2022 Initial release. Part Number [1] Description Carrier Type Pkg. Description Temp. Range

3031 400.35 5.00 ±0.10 5.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW0.40 3.60 ±0.10 3.60 ±0.10 0.40 SIDE VIEW 0.20 (0.30) 0.35 0.200.40 3.60 3.60 4.20 5.30 5.30 (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN PackageOutline © Renesas Electronics Corporation

(PCB Top View, NSMD Design) 5.00 ±0.10 TOP VIEWBOTTOM VIEW SIDE VIEWDetail A RECOMMENDED LAND PATTERN SoldermaskPackage EdgeSoldermask OpeningExposed Metal Pin 1 ID 1.70 ±0.10Seating Plane0.08CC 10112021 3031 39 0.30 (0.10) A 3.03 ±0.10 1.17 PackageOutline3.03 3.03 0.20 4.205.100.27 1.17 0.691.17 0.273.03 ±0.10 1.17 0.400.20 0.45 0.40 0.69 5.00 ±0.10 0.69 0.69 © Renesas Electronics Corporation

4.50 ±0.05 BOTTOM VIEW 6.300.200.40 0.55 4.50 4.50 5.20 0.200.406.30 5.20 (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN 0.40 Package Outline 6.00 ±0.10 6.00 ±0.100.20 4.50 ±0.05 CSIDE VIEW 0.35 0.35 0.4012 363748 132425 (0.35) © Renesas Electronics Corporation

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