RC19304A001GNL#KB0

Renesas Technology Corp

PCIe Gen7 1.8V 2-Input Clock Mux Family with LOS Rev.1.06 May 11, 2026

Manufacturer: Renesas Technology Corp

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RC193XX_V01 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 62

Technical content

Datasheet sections

1.1 Signal Types
1.2 Detailed Block Diagram
1.3 RC19308 Pin Information
1.3.1 RC19308 Pin Information
1.3.2 RC19308 Pin Descriptions
1.4 RC19304 Pin Information
1.4.1 RC19304 Pin Assignments
1.4.2 RC19304 Pin Descriptions
1.5 RC19302 Pin Information
1.5.1 RC19302 Pin Assignments
1.5.2 RC19302 Pin Descriptions
2.1 Absolute Maximum Ratings
2.2 Recommended Operation Conditions
2.3 Thermal Specifications
2.4 Electrical Characteristics
2.4.1 Additive Phase Jitter
2.4.2 Other Phase Jitter
2.4.3 Output Frequencies, Startup Time, and LOS Timing
2.4.4 CLK (LP-HCSL) AC/DC Output Characteristics
2.4.5 CLKIN AC/DC Characteristics
2.4.6 Skew
2.4.7 I/O Electrical Characteristics
2.4.8 Power Supply Current
2.4.9 SMBus Electrical Characteristics
4.1 How to Write
4.2 How to Read
4.3 Write Lock Functionality (RC19308)
4.4 SMBus Address Selection (RC19308)
4.5 SMBus Registers
4.5.1 OUTPUT_ENABLE
4.5.2 OEB_PIN_READBACK
4.5.3 LOS_CONFIG
4.5.4 VENDOR_REVISION_ID
4.5.5 DEVICE_ID
4.5.6 BYTE_COUNT
4.5.7 SLEW_AMP_SELECT
4.5.8 INPUT_PULLUP_PULLDOWN_4
4.5.9 AMP_CTRL_ALT
4.5.10 AMP_CTRL_DEF
4.5.11 PD_RESTORE_LOSb_CONFIG
4.5.12 OUTPUT_IMPEDANCE_7_0
4.5.13 OUTPUT_REC_SEL_7_0
4.5.14 OUTPUT_SLEW_RATE_7_0
4.5.15 LOW_LOW_DETECT
4.5.16 RECEIVER_CONTROL
4.5.17 WRITE_LOCK
4.5.18 WRITE_LOCK_LOS_EVT

Features

▪ Very Low Additive Phase Jitter:

PCIe Gen5 CC: 6.9fs RMS (typ.)
PCIe Gen6 CC: 4.1fs RMS (typ.)
PCIe Gen7 CC: 2.9fs RMS (typ.)
DB2000Q: 11.5fs RMS (typ.)
12kHz - 20MHz (156.25MHz): 42.8fs RMS (typ.) ▪ 2:N or dual x 1:N/2 modes (N is number of outputs) ▪ Power Down Tolerant (PDT) inputs ▪ Flexible Startup Sequencing (FSS) ▪ Automatic Clock Parking (ACP) upon loss of selected CLKIN ▪ Spread-spectrum tolerant ▪ CLKIN accepts HCSL or LVDS signal levels ▪ Dedicated OEb pin per output ▪ -40 to +105°C, 1.8V ± 5% operation ▪ Devices provide:
Pin or SMBus selectable 34Ω, 85Ω, or 100Ω differential output impedance
Pin or SMBus selectable output slew rate
Pin or SMBus selectable output amplitude
9 SMBus addresses plus write protection

Figure 1. Simplified Block Diagram and Mux Logic

R31DS0210EU0106 Rev.1.06 Page 3 May 11, 2026 RC193xx Datasheet

1.1 Signal Types

1.2 Detailed Block Diagram

Figure 2. RC1930x Detailed Block Diagram is powered down (VDD is not present). Note 1: RC19302 does not have these pins. Note 2: RC19304, RC19304A100 do not have these pins.

1.3 RC19308 Pin Information

1.3.1 RC19308 Pin Information

Figure 3. RC19308A Pin Assignments Figure 4. RC19308A001 Pin Assignments

48 47 46 45 44 43 42 41 40 39 38 37 ZOUTSEL_tri 1 36 SADR_tri1 VDDDIG 2 35 OEb2 PWRGD_PWRDNb 3 34 OEb3 CLKIN0 4 33 CLKb3 CLKINb0 5 32 CLK3 V DDIN0 6 31 V DDA SADR_tri0 7 30 V DDCLK_0 CLKIN1 8 29 LOSb CLKINb1 9 28 V DDCLK_1 SDATA 10 27 CLKb4 SCLK 11 26 CLK4 VDDIN1 12 25 OEb4 13 14 15 16 17 18 19 20 21 22 23 24 VDDCLK_1 CLK7 CLKb7 OEb7 CLKSEL_tri OEb6 CLK6 CLKb6 VDDCLK_1 CLK5 CLKb5 OEb5 RC19308A 48-VFQFPN Connect to E PAD to GN D Top View GNDSUB VDDCLK_0 CLKb0 CLK0 OEb0 OEb1 AMPLITUDE_SEL CLKb1 CLK1 VDDCLK_0 CLKb2 CLK2
48 47 46 45 44 43 42 41 40 39 38 37 ZOUTSEL_tri 1 36 SADR_tri1 VD DD I G 2 35 OE b2 PWRGD_PWRDNb 3 34 OEb3 CLKIN0 4 33 CLKb3 CLKINb0 5 32 CLK3 VDDIN0 6 31 VDDA SADR_tri0 7 30 VDDCLK_0 CLKIN1 8 29 LOSb CLKINb1 9 28 VDDCLK_1 SDATA 10 27 CLKb4 SCLK 11 26 CLK4 VDDIN1 12 25 OEb4 13 14 15 16 17 18 19 20 21 22 23 24 VDDCLK_1 CLK7 CLKb7 OEb7 CLKSEL_tri OEb6 CLK6 CLKb6 VDDCLK_1 CLK5 CLKb5 OEb5 RC19308A001 48-VFQF PN Connect to EPAD to GND Top View

1.3.2 RC19308 Pin Descriptions

Table 1. RC19308A/A001 Pin Descriptions

1 ZOUTSEL_tri I, SE, PD,

Input to select differential output impedance. which results in a default output impedance of 85Ω when left floating. is pin is tri-level on the RC19308 with both internal pull-up and pull-down resistors. the RC19308, this results in a default output impedance of 34Ω when left floating.

3 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 4 CLKIN0 I, DIF True clock input. 5 CLKINb0 I, DIF Complementary clock input. 6 VDDIN0 PWR Power supply for clock input 0.

7 SADR_tri0 I, SE, PD,

(RC19308) table and refer to the tri-level input thresholds in the electrical tables. 8 CLKIN1 I, DIF True clock input. 9 CLKINb1 I, DIF Complementary clock input.

10 SDATA I/O, SE,

OD, PDT Data pin for SMBus interface. 11 SCLK I, SE, PDT Clock pin of SMBus interface. 12 VDDIN1 PWR Power supply for clock input 1. 13 VDDCLK_1 PWR Power supply for clock output bank 1. 14 CLK7 O, DIF True clock output. 15 CLKb7 O, DIF Complementary clock output.

16 OEb7 I, SE, PU,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output.

17 CLKSEL_tri I, SE, PD,

18 OEb6 I, SE, PU,

Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 19 CLK6 O, DIF True clock output. 20 CLKb6 O, DIF Complementary clock output. 21 VDDCLK_1 PWR Power supply for clock output bank 1. 22 CLK5 O, DIF True clock output. 23 CLKb5 O, DIF Complementary clock output.

24 OEb5 I, SE, PU,

Active low input for enabling output 5. 0 = Enable output, 1 = Disable output.

25 OEb4 I, SE, PU,

Active low input for enabling output 4. 0 = Enable output, 1 = Disable output. 26 CLK4 O, DIF True clock output. 27 CLKb4 O, DIF Complementary clock output. 28 VDDCLK_1 PWR Power supply for clock output bank 1.

29 LOSb O, OD,

30 VDDCLK_0 PWR Power supply for clock output bank 0. 31 VDDA PWR Power supply for core multiplexer circuitry. 32 CLK3 O, DIF True clock output. 33 CLKb3 O, DIF Complementary clock output.

34 OEb3 I, SE, PU,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

35 OEb2 I, SE, PU,

Active low input for enabling output 2. 0 = Enable output, 1 = Disable output.

36 SADR_tri1 I, SE, PD,

(RC19308) table and refer to the tri-level input thresholds in the electrical tables. 37 CLK2 O, DIF True clock output. 38 CLKb2 O, DIF Complementary clock output. 39 VDDCLK_0 PWR Power supply for clock output bank 0. 40 CLK1 O, DIF True clock output. 41 CLKb1 O, DIF Complementary clock output. Input to select default output slew rate. Input to select output amplitude. The values are programmable with defaults listed below.

43 OEb1 I, SE, PU,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output.

44 OEb0 I, SE, PU,

Active low input for enabling output 0. 0 = Enable output, 1 = Disable output. 45 CLK0 O, DIF True clock output. 46 CLKb0 O, DIF Complementary clock output. 47 VDDCLK_0 PWR Power supply for clock output bank 0. 48 GNDSUB GND Ground pin for substrate. Table 1. RC19308A/A001 Pin Descriptions (Cont.)

1.4 RC19304 Pin Information

1.4.1 RC19304 Pin Assignments

Figure 5. RC19304A Pin Assignments Figure 6. RC19304A001 Pin Assignments

1.4.2 RC19304 Pin Descriptions

Table 2. RC19304A/A001 Pin Descriptions

1 PWRGD_PWRDNb I, SE,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 2 CLKIN0 I, DIF True clock input. 3 CLKINb0 I, DIF Complementary clock input. 4 VDDIN0 PWR Power supply for clock input 0. 5 CLKIN1 I, DIF True clock input. 6 CLKINb1 I, DIF Complementary clock input.

2 82 72 62 52 42 32 2 PWRGD_PWRDNb 1 21 CLKb2 CLKIN0 2 20 CLK2 CLKINb0 3 19 OEb2 VDDIN0 4 18 VDD A CLKIN1 5 17 LOSb CLKINb1 6 16 OEb5 VDDIN1 7 15 SLEWRA TE_SEL 8 9 10 11 12 13 14CLKSEL_tri OEb6 CLK6 CLKb6 VDDCLK_1 CLK5 CLKb5 RC19304A 28-VFQFPN Connect to E PAD to GND Top View ZOUTSEL_tri GNDSUB VDDDIG OEb1 CLKb1 CLK1 VDDCLK_0
2 82 72 62 52 42 32 2 PWRGD_PWRDNb 1 21 CLKb2 CLKIN0 2 20 CLK2 CLKINb0 3 19 OEb2 VDDIN0 4 18 VDD A CLKIN1 5 17 LOSb CLKINb1 6 16 OEb5 VDDIN1 7 15 AM P LI T UD E _SE L 8 9 10 11 12 13 14CLKSEL_tri OEb6 CLK6 CLKb6 VDDCLK_1 CLK5 CLKb5 RC19304A001 28-VFQFPN Connect to E PAD to GND Top View

7 VDDIN1 PWR Power supply for clock input 1.

8 CLKSEL_tri I, SE, PD,

9 OEb6 I, SE, PU,

Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 10 CLK6 O, DIF True clock output. 11 CLKb6 O, DIF Complementary clock output. 12 VDDCLK_1 PWR Power supply for clock output bank 1. 13 CLK5 O, DIF True clock output. 14 CLKb5 O, DIF Complementary clock output. Input to select default output slew rate. Input to select output amplitude. The values are programmable with defaults listed below.

16 OEb5 I, SE, PU,

Active low input for enabling output 5. 0 = Enable output, 1 = Disable output.

17 LOSb O, OD,

18 VDDA PWR Power supply for analog circuitry.

19 OEb2 I, SE, PU,

Active low input for enabling output 2. 0 = Enable output, 1 = Disable output. 20 CLK2 O, DIF True clock output. 21 CLKb2 O, DIF Complementary clock output. 22 VDDCLK_0 PWR Power supply for clock output bank 0. 23 CLK1 O, DIF True clock output. 24 CLKb1 O, DIF Complementary clock output.

25 OEb1 I, SE, PU,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 26 VDDDIG PWR Digital power. 27 GNDSUB GND Ground pin for substrate.

28 ZOUTSEL_tri I, SE, PD,

Input to select differential output impedance. which results in a default output impedance of 85Ω when left floating. is pin is tri-level on the RC19304 with both internal pull-up and pull-down resistors. the RC19304, this results in a default output impedance of 34Ω when left floating. 29 EPAD GND Connect to ground. Table 2. RC19304A/A001 Pin Descriptions (Cont.)

1.5 RC19302 Pin Information

1.5.1 RC19302 Pin Assignments

Figure 7. RC19302A Pin Assignments

1.5.2 RC19302 Pin Descriptions

Table 3. RC19302A Pin Descriptions 1 CLKIN0 I, DIF True clock input. 2 CLKINb0 I, DIF Complementary clock input. 3 VDDIN0 PWR Power supply for clock input 0. 4 CLKIN1 I, DIF True clock input. 5 CLKINb1 I, DIF Complementary clock input. 6 VDDIN1 PWR Power supply for clock input 1.

7 CLKSEL_tri I, SE, PD,

internal pull-up and pull-down resistor to bias a floating pin to the mid-point. 0 = CLKIN0 selected for all outputs. 1 = CLKIN1 selected for all outputs. M = CLKIN0 goes to bank 0 and CLKIN1 goes to bank 1. 8 VDDCLK_1 PWR Power supply for clock output bank 1. 9 CLK5 O, DIF True clock output. 10 CLKb5 O, DIF Complementary clock output.

11 ZOUTSEL_tri I, SE, PD,

Input to select differential output impedance. which results in a default output impedance of 85Ω when left floating. is pin is tri-level on the RC19302 with both internal pull-up and pull-down resistors. the RC19302, this results in a default output impedance of 34Ω when left floating.

12 OEb5 I, SE, PU,

Active low input for enabling output 5. 0 = Enable output, 1 = Disable output.

13 LOSb O, OD,

14 VDDA PWR Power supply for analog circuitry.

15 OEb2 I, SE, PU,

Active low input for enabling output 2. 0 = Enable output, 1 = Disable output.

20 19 18 17 16 CLKIN0 1 15 OEb2 CLKINb0 2 14 VD D A VD D I N 0 3 13 LOSb CLKIN1 4 12 OEb5 CLKINb15 11 ZOUTSEL_tri 6789 1 0VDDIN1 CLKSEL_tri VDDCLK_1 CLK5 CLKb5 RC19302A 20-VFQFPN Connect to EP AD to GND. Top V iew .

2.1 Absolute Maximum Ratings

conditions can adversely impact product reliability and result in failures not covered by warranty. 16 CLK2 O, DIF True clock output. 17 CLKb2 O, DIF Complementary clock output. 18 VDDCLK_0 PWR Power supply for clock output bank 0. 19 VDDDIG PWR Digital power. 20 GNDSUB GND Ground pin for substrate. 21 EPAD GND Connect to ground. Table 4. Absolute Maximum Ratings

Inputs not designated Power Down Tolerant (PDT) in the pin description tables.
Inputs designated Power Down Tolerant (PDT) in the pin description tables.
The V PUP voltage may be applied before main VDD is applied. The LOSb pin is PDT to this voltage, not to 3.6V.

Table 3. RC19302A Pin Descriptions (Cont.)

2.2 Recommended Operation Conditions

conditions in this table must be met to guarantee device functionality and performance.

2.3 Thermal Specifications

Table 5. Recommended Operating Conditions (power ramps must be monotonic). Table 6. Thermal Specifications

2.4 Electrical Characteristics

2.4.1 Additive Phase Jitter

Table 7. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Unselected CLKIN Off) – Normal Conditions [1][2][3]

The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83.

Differential input swing ≥ 1600mV and input slew rate ≥ 3.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

Table 8. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Unselected CLKIN Off) – Degraded Conditions [1][2][3]

The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

Differential input swing ≥ 800mV and input slew rate ≥ 1.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe

Gen1) must be less than the jitter specification listed.

SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

Table 9. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Both CLKIN Running at Different Frequencies) – Normal

The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

Differential input swing ≥ 1600mV and input slew rate ≥ 3.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe

Gen1) must be less than the jitter specification listed.

One input clock at 100MHz, the other input clock at 99.75MHz, 100MHz clock measured.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

Table 10. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Both CLKIN Running at Different Frequencies) – Degraded

The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

Differential input swing ≥ 800mV and input slew rate ≥ 1.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe

Gen1) must be less than the jitter specification listed.

One input clock at 100MHz, the other input clock at 99.75MHz, 100MHz clock measured.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

Table 11. PCIe Refclk Phase Jitter (CLKSEL_tri = M, Both CLKIN Running at Different Frequencies) – Normal

The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0 For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

Differential input swing ≥ 1600mV and input slew rate ≥ 3.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe

Gen1) must be less than the jitter specification listed.

One input clock at 100MHz, the other input clock at 99.75MHz, 100MHz clock measured.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

Table 12. PCIe Refclk Phase Jitter (CLKSEL_tri = M, Both CLKIN Running at Different Frequencies) – Degraded

The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

Differential input swing ≥ 800mV and input slew rate ≥ 1.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe

Gen1) must be less than the jitter specification listed.

One input clock at 100MHz, the other input clock at 99.75MHz, 100MHz clock measured.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

2.4.2 Other Phase Jitter

Note: Dual-mode operation (CLKSEL_tri = M, both CLKIN running) is recommended only for PCIe applications.

2.4.3 Output Frequencies, Startup Time, and LOS Timing

Table 13. Non-PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Unselected CLKIN Off) [1][2][3]

See Test Loads for test configuration. Measured with one input at 100MHz and the other at 156.25MHz.
SMA100B used as signal source.
RC19xxx devices meet all legacy QPI/UPI specifications by meeting the PCIe and DB2000Q specifications listed in this document.
Differential input swing = 1600mV and input slew rate = 3.5V/ns.
The rms sum of the source jitter and the additive jitter must be less than the jitter specification listed.
Differential input swing = 800mV and input slew rate = 1.5V/ns.

Table 14. Output Frequencies, Startup Time, and LOS Timing

Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output. PWRGD_PGWRDNb
VDD stable, measured from de-assertion of PWRGD_PWRDNb.
The clock detect circuit does not qualify the accuracy of the input clock.
PWRGD_PWRDNb high. The clock detect circuit will park the outputs in a low/low state within this time.
PWRGD_PWRDNb high. The clock detect circuit will drive the outputs to a high/low state within this time and then begin clocking the outputs.

2.4.4 CLK (LP-HCSL) AC/DC Output Characteristics

Table 15. 85Ω CLK AC/DC Characteristics – Source-Terminated 100MHz PCIe Applications [1]

Standard high impedance load with C L = 2pF. See Test Loads.
The specification limits are taken from either the PCI Express Base Specification 7.0 or from relevant x86 processor specifications, whichever is
Measured from single-ended waveform.
Defined as the maximum instantaneous voltage including overshoot.
Defined as the minimum instantaneous voltage including undershoot.
Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
Measured from differential waveform.
Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 16. 100 ohm CLK AC/DC Characteristics – Source-Terminated, PCIe Applications [1]

Standard high impedance load with C L = 2pF. See Test Loads.
The specification limits are taken from either the PCI Express Base Specification 7.0 or from relevant x86 processor specifications, whichever is
Measured from single-ended waveform.
Defined as the maximum instantaneous voltage including overshoot.
Defined as the minimum instantaneous voltage including undershoot.
Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
Measured from differential waveform.
Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 17. 85 ohm CLK AC/DC Characteristics – Source-Terminated, Non-PCIe Applications[1]

Standard high impedance load with C L = 2pF. See Test Loads.
Measured from single-ended waveform.
Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
Measured from differential waveform.

Table 18. 100 ohm CLK AC/DC Characteristics - Source-Terminated, Non-PCIe Applications [1]

Standard high impedance load with C L = 2pF. See Test Loads.
Measured from single-ended waveform.

Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
Measured from differential waveform.

Table 19. 85 ohm CLK AC/DC Characteristics – Double-Terminated, Non-PCIe Applications [1]

Both Tx and Rx are terminated (double-terminated) with CL= 2pF. This reduces amplitude by 50%. See Test Loads.
Measured from single-ended waveform.
Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
Measured from differential waveform.

Table 20. 100 ohm CLK AC/DC Characteristics – Double-Terminated, Non-PCIe Applications [1]

Both Tx and Rx are terminated (double-terminated) with CL= 2pF. This reduces amplitude by 50%. See Test Loads.
Measured from single-ended waveform.
Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
Measured from differential waveform.

Table 21. 34ohm CLK AC/DC Characteristics – Rx-Terminated, Non-PCIe Applications [1]

ZOUTSEL_tri = M. This setting turns off the source termination, provided approximately 75% of the source-terminated amplitude at the receiver
Measured from single-ended waveform.

reduced by ~50% due to double termination.

Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any

reduced by ~50% due to double termination.

Measured from differential waveform.

2.4.5 CLKIN AC/DC Characteristics

Figure 8. Clock Input Bias Network

2.4.6 Skew

Table 22. CLKIN AC/DC Characteristics for DC-Coupled Operation[1]

See the Additive Phase Jitter tables for values required for performance. The CLKIN is designed for a ground-referenced differential input where
Low/Low is an invalid differential state. LOW_LOW_DETECT allows the receiver turn itself off when such a condition is detected
Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero-crossing. Table 23. Output-to-Output and Input-to-Output Skew [1]

This parameter is defined in accordance with JEDEC Standard 65.
Output banks sourced from the same input. CLKSEL_tri = 0 or 1.
Defined as the time between to output rising edge and the input rising edge that caused it.

2.4.7 I/O Electrical Characteristics

2.4.8 Power Supply Current

Table 24. I/O Electrical Characteristics

For SCLK and SDATA, see Table 26.
These values are compliant with JESD8-7A 1.8V Normal Range.

Single-ended inputs, unless otherwise listed. Table 25. Power Supply Current [1][2][3]

Deselected input channel, per VDDIN pin. Selected input channel, per VDDIN pin. IDDA VDDA Current Core logic supply, independent of either bank.

Output voltage set to 800mV. Slew rate has negligible effect on current consumption, so only fast is listed.
Total operating current is obtained by adding (I DDCLK x number of outputs used) + IDDCLK_CORE_0 + IDDCLK_CORE_1 + IDDIN0 + IDDIN1 + IDDA +

CLK[7:4]. Total power down current is obtained by adding IDDCLK_0PD + IDDCLK_1PD + IDDIN0PD + IDDIN1PD + IDDDIG_PD + IDDA.

The value specified is for one output pair. Multiply this value by the number of outputs in use.
On the RC19308, bank 0 is powered by 3 VDDCLK_0 pins and bank 1 is powered by 3 VDDCLK_1 pins. This value is the total current per output

bank, not per VDDCLK pin. This parameter needs to be counted only twice. Table 25. Power Supply Current [1][2][3] (Cont.)

2.4.9 SMBus Electrical Characteristics

Figure 9. SMBus Target Timing Diagram Table 26. SMBus DC Electrical Characteristics [1]

V OH is governed by the VPUP, the voltage rail to which the pull-up resistors are connected. The maximum VPUP voltage is 3.6V.
See I/O Electrical Characteristics.

Table 27. SMBus AC Electrical Characteristics

Power must be applied and PWRGD_PWRDNb must be a 1 for the SMBus to be active.

R31DS0210EU0106 Rev.1.06 Page 29 May 11, 2026 RC193xx Datasheet 2. A host should not drive the clock at a frequency below the minimum f SMB. Further, the operating clock frequency should not be reduced below the minimum value of fSMB due to periodic clock extending by target devices as defined in Section 5.3.3 of System Management Bus (SMBus) Specification, Version 3.2, dated 12 Jan, 2022. This limit does not apply to the bus idle condition, and this limit is independent from the tLOW: SEXT and tLOW: MEXT limits. For example, if the SCLK is high for tHIGH,MAX, the clock must not be periodically stretched longer than 1/fSMB,MIN – tHIGH,MAX. This requirement does not pertain to a device that extends the SCLK low for data processing of a received byte, data buffering and so forth for longer than 100 µs in a non-periodic way. 3. A device must internally provide sufficient hold time for the SDATA signal (with respect to the VIH,MIN of the SCLK signal) to bridge the undefined region of the falling edge of SCLK. 4. Target devices may have caused other target devices to hold SDA low. This is the maximum time that a device can hold SDATA low after the host raises SCLK after the last bit of a transaction. A target device may detect how long SDA is held low and release SDA after the time out period. 5. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of tTIMEOUT,MIN. After the host in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than tTIMEOUT,MAX. Typical device examples include the host controller, and embedded controller, and most devices that can host the SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or a stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds the SCLK low for tTIMEOUT,MAX or longer. 6. The device has the option of detecting a timeout if the SDATAA pin is also low for this time. 7. t HIGH,MAX provides a simple guaranteed method for hosts to detect bus idle conditions. A host can assume that the bus is free if it detects that the clock and data signals have been high for greater than tHIGH,MAX. 8. t LOW:MEXT is the cumulative time a host device is allowed to extend its clock cycles within each byte of a message as defined from START-to- ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a target device or another host will also extend the clock causing the combined clock low time to be greater than tLOW:MEXT on a given byte. This parameter is measured with a full speed target device as the sole target of the host. 9. The rise and fall time measurement limits are defined as follows: ▪ Rise Time Limits: (V IL:MAX - 0.15 V) to (VIH:MIN + 0.15 V) ▪ Fall Time Limits: (V IH:MIN + 0.15 V) to (VIL:MAX - 0.15 V) 10. Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

Figure 12. Test Load for PCIe Phase Jitter Measurements Table 30. Parameters for PCIe Jitter Measurement

PCIe Gen5-7 specify L = 0cm for 32, 64 and 128GT/s. L = 25.4cm is more conservative.

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4.1 How to Write

▪ Controller (host) sends a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) sends the byte count = X ▪ Renesas clock will acknowledge ▪ Controller (host) starts sending Byte N through Byte N+X-1 ▪ Renesas clock will acknowledge each byte one at a time ▪ Controller (host) sends a stop bit

4.2 How to Read

▪ Controller (host) will send a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) will send a separate start bit ▪ Controller (host) sends the read address ▪ Renesas clock will acknowledge ▪ Renesas clock will send the data byte count = X ▪ Renesas clock sends Byte N+X-1 ▪ Renesas clock sends Byte L through Byte X (if X(H) was written to Byte 7) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit Index Block Write Operation Controller (Host) Renesas T starT bit Target Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK P stoP bit Index Block Read Operation Controller (Host) Renesas T starT bit Target Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Target Address RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not P stoP bit

4.3 Write Lock Functionality (RC19308)

4.4 SMBus Address Selection (RC19308)

4.5 SMBus Registers

Table 31. Register Index

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4.5.1 OUTPUT_ENABLE

Output Enable Register.

4.5.2 OEB_PIN_READBACK

OEb Pin Read-back Register. OUTPUT_ENABLE Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 clk7_en RW 0x1 CLK7 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 6 clk6_en RW 0x1 CLK6 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 5 clk5_en RW 0x1 CLK5 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 4 clk4_en RW 0x1 CLK4 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 3 clk3_en RW 0x1 CLK3 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 2 clk2_en RW 0x1 CLK2 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 1 clk1_en RW 0x1 CLK1 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 0 clk0_en RW 0x1 CLK0 enable. 0 = Output is disabled (low/low) 1 = Output is enabled OEB_PIN_READBACK Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 rb_oeb_7 RO 0x0 State of OEb7 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 6 rb_oeb_6 RO 0x0 State of OEb6 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 5 rb_oeb_5 RO 0x0 State of OEb5 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 4 rb_oeb_4 RO 0x0 State of OEb4 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 3 rb_oeb_3 RO 0x0 State of OEb3 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 2 rb_oeb_2 RO 0x0 State of OEb2 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high

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4.5.3 LOS_CONFIG

Loss of Signal and Async Mode Configuration Register. 1 rb_oeb_1 RO 0x0 State of OEb1 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 0 rb_oeb_0 RO 0x0 State of OEb0 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high LOS_CONFIG Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 los1b_rw1c_en RW 0x1 LOS sticky bit enable for CLKIN1. Enables the CLKIN1 LOS sticky bit (B0x27[1]). This bit must be set to 1 if B0x4[2] is set to 0. 0 = Disable 1 = Enable 6 los0b_rw1c_en RW 0x1 LOS sticky bit enable for CLKIN0. Enables the CLKIN0 LOS sticky bit (B0x27[1]). This bit must be set to 1 if B0x4[2] is set to 0. 0 = Disable 1 = Enable 5 los1b_acp1_enable RW 0x1 Automatic clock parking enable for bank 1. Enables Automatic Clock Parking of bank 1 (CLK[7:4]) outputs to a low/low state when LOS condition occurs. 0 = Disable 1 = Enable 4 los0b_acp0_enable RW 0x1 Automatic clock parking enable for bank 0. Enables Automatic Clock Parking of bank 0 (CLK[3:0]) outputs to a low/low state when LOS condition occurs. 0 = Disable 1 = Enable 3 los1b_config RW 0x1 Configure LOSb pin operating mode for CLKIN1. Determines if the LOSb pin is real-time or sticky. If sticky, the LOSb pin is driven by the LOS1b RW1C sticky bit. 0 = LOSb from bank 1 RW1C sticky bit 1 = LOSb real-time 2 los0b_config RW 0x1 Configure LOSb pin operating mode for CLKIN0. Determines if the LOSb pin is real-time or sticky. If sticky, the LOSb pin is driven by the LOS0b RW1C sticky bit. 0 = LOSb from bank 0 RW1C sticky bit 1 = LOSb real-time 1 reserved RW 0x0 Reserved 0 async_mode RW 0x0 Enable asynchronous operating mode. SYNC mode is the normal mode of operation, where the input clock is continuous. Outputs stop and start in a glitch free manner. ASYNC mode is used when the input is a pulse instead of a clock. All glitch-free synchronization circuits are bypassed, minimizing the latency through the device. ASYNC mode cannot be used with LOS or ACP. B0x4[6] and B0x4[4] must be set to 0 if ASYNC mode is used. 0 = SYNC mode, glitch-free outputs 1 = ASYNC mode, non-glitch-free outputs OEB_PIN_READBACK Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.5.4 VENDOR_REVISION_ID

Vendor ID, Revision ID Register.

4.5.5 DEVICE_ID

Device ID Register.

4.5.6 BYTE_COUNT

Number of Bytes Returned on an SMBus Block Read.

4.5.7 SLEW_AMP_SELECT

Multifunction Pin Configuration Register. VENDOR_REVISION_ID Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 rid RO 0x0 Revision ID. Silicon revision. 0x0 = A revision 3:0 vid RO 0x1 Vendor ID. Vendor ID. 0x1 = Renesas DEVICE_ID Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:0 device_id RO 0x38 Device ID. RC19308 listed as default. 0x38 = RC19308 0x34 = RC19304 0x32 = RC19302 BYTE_COUNT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:5 reserved RW 0x0 Reserved 4:0 byte_count RW 0x7 Writing to this register configures how many bytes will be returned on an SMBus block read. SLEW_AMP_SELECT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 slew_amp_sel RW 0x0 Multifunction pin selection. The pin is defined as either Slew Rate Select or Amplitude Select. If Amplitude Select is chosen, refer to registers 0x10 and 0x11. 0 = Pin is Slew Rate Select pin (RC193xxA) 1 = Pin is Amplitude Select pin (RC193xxA001) 6 reserved RW 0x0 Reserved 5:4 clksel_1_0 RW 0x0 Clock mux select. These bits allow software control of the input clock mux. 0 = Both bank from CLKIN0 1 = Bank0 from CLKIN0, bank1 from CLKIN1 2 = Invalid 3 = Both bank from CLKIN1 3:1 reserved RW 0x0 Reserved 0 clksel_cntrl RW 0x0 Select pin or software control of the clock mux. Pin control is the power up default. 0 = Use CLKSEL pin control 1 = Use software control (B0xA [5:4]

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4.5.8 INPUT_PULLUP_PULLDOWN_4

Internal Pull-up / Pull-down Configuration Register.

4.5.9 AMP_CTRL_ALT

Alternate Amplitude Selection Register. INPUT_PULLUP_PULLDOWN_4 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 reserved RW 0xb Reserved 3 sdata_pullup RW 0x0 Enable/disable internal pull-up. The default pin state is high when the internal pull-up is enabled. If the SMBus is not used, this bit may be set to hold the SDATA pin in an inactive state. It should not be set if the SMBus is used in the system. RC19308 and RC19304 only. 0 = Disable internal pull-up 1 = Enable internal pull-up 2 reserved RW 0x0 Reserved 1 sclk_pullup RW 0x0 Enable/disable internal pull-up. The default pin state is high when the internal pull-up is enabled. If the SMBus is not used, this bit may be set to hold the SDATA pin in an inactive state. It should not be set if the SMBus is used in the system. RC19308 and RC19304 only. 0 = Disable internal pull-up 1 = Enable internal pull-up 0 reserved RW 0x0 Reserved AMP_CTRL_ALT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 amp_cntrl_alt_bnk1 RW 0xB Alternate amplitude control for bank 1. When the multifunction pin is configured as Amplitude Select, this field defines the single-ended output amplitude of Bank 1 (CLK[7:4]) when the pin = 1. When the multifunction pin is configured as Slew Rate Selection, this field has no impact. 0x0 = 625mV 0x1 = 650mV 0x2 = 675mV 0x3 = 700mV 0x4 = 725mV 0x5 = 750mV 0x6 = 775mV 0x7 = 800mV 0x8 = 825mV 0x9 = 850mV amp_cntrl_alt_bnk1 (continued) 0xA = 875mV 0xB = 900mV 0xC = 925mV 0xD = 950mV 0xE = 975mV 0xF = 1000mV

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4.5.10 AMP_CTRL_DEF

Default Amplitude Selection Register. 3:0 amp_cntrl_alt_bnk0 RW 0xB Alternate amplitude control for bank 0. When the multifunction pin is configured as Amplitude Select, this field defines the single-ended output amplitude of the Bank 0 (CLK[3:0]) when the pin = 1. When the multifunction pin is configured as Slew Rate Selection, this field has no impact. 0x0 = 625mV 0x1 = 650mV 0x2 = 675mV 0x3 = 700mV 0x4 = 725mV 0x5 = 750mV 0x6 = 775mV 0x7 = 800mV 0x8 = 825mV 0x9 = 850mV amp_cntrl_alt_bnk0 (continued) 0xA = 875mV 0xB = 900mV 0xC = 925mV 0xD = 950mV 0xE = 975mV 0xF = 1000mV AMP_CTRL_DEF Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 amp_cntrl_def_bnk1 RW 0x7 Default amplitude control for bank 1. When the multifunction pin is configured as Amplitude Select, this field defines the single-ended output amplitude of the Bank 1 (CLK[7:4]) when the pin = 0. When the multifunction pin is configured as Slew Rate Selection, this field determines the amplitude of bank 1 (CLK[7:4]). 0x0 = 625mV 0x1 = 650mV 0x2 = 675mV 0x3 = 700mV 0x4 = 725mV 0x5 = 750mV 0x6 = 775mV 0x7 = 800mV 0x8 = 825mV 0x9 = 850mV amp_cntrl_def_bnk1 (continued) 0xA = 875mV 0xB = 900mV 0xC = 925mV 0xD = 950mV 0xE = 975mV 0xF = 1000mV AMP_CTRL_ALT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.5.11 PD_RESTORE_LOSb_CONFIG

Configuration and Status Register. 3:0 amp_cntrl_def_bnk0 RW 0x7 Default amplitude control for bank 0. When the multifunction pin is configured as Amplitude Select, this field defines the single-ended output amplitude of the Bank 0 (CLK[3:0]) when the pin = 0. When the multifunction pin is configured as Slew Rate Selection, this field determines the amplitude of bank 0 (CLK[3:0]). 0x0 = 625mV 0x1 = 650mV 0x2 = 675mV 0x3 = 700mV 0x4 = 725mV 0x5 = 750mV 0x6 = 775mV 0x7 = 800mV 0x8 = 825mV 0x9 = 850mV amp_cntrl_def_bnk0 (continued) 0xA = 875mV 0xB = 900mV 0xC = 925mV 0xD = 950mV 0xE = 975mV 0xF = 1000mV PD_RESTORE_LOSb_CONFIG Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:5 reserved RW 0x0 Reserved 4 ck_acquire_rb RO 0x0 Clock acquired read-back. This bit indicates if a clock was ever detected (LOSb de-asserted) for the current power cycle. 0 = Clock never acquired 1 = Clock acquired once before 3 pd_restoreb RW 0x1 Save configuration in power-down. This bit determines the behavior of the device when the PWRGD_PWRDNb pin is asserted low. This bit is automatically returned to 1 after PWRGD_PWRDNb is toggled 1-0-1 with the bit set to 0. 0 = Config Cleared 1 = Config Saved 2 sdata_time_out_enable RW 0x1 Enable SMB time out monitoring SDATA. This bit enables a timeout for the SMBus data path. This timeout monitor is in addition to the mandatory SCLK timeout monitor. These monitors release a hung SMBus. 0 = Disable SDATA time out 1 = Enable SDATA time out 1 los1b_rb RO 0x0 Real-time read back of CLKIN1 clock detect. This bit provides a real-time status of the CLKIN1 input. The default value assumes CLKIN1 is not present. 0 = LOS event detected (no CLKIN1 detected) 1 = No LOS event detected (CLKIN1 detected) 0 los0b_rb RO 0x0 Real-time read back of CLKIN0 clock detect. This bit provides a real-time status of the CLKIN0 input. The default value assumes CLKIN0 is not present. 0 = LOS event detected (no CLKIN0 detected) 1 = No LOS event detected (CLKIN0 detected) AMP_CTRL_DEF Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.5.12 OUTPUT_IMPEDANCE_7_0

Output Impedance Select Register 0. OUTPUT_IMPEDANCE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 clk7_impedance0 RW 0x0 CLK7 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When the pin is 0, this bit and B0x15[7] are set to 0. When the pin is M, this bit is set to 0 and B0x15[7] is set to 1. When the pin is 1, this bit is set to 1 and B0x15[7] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 6 clk6_impedance0 RW 0x0 CLK6 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When this pin is 0, this bit and B0x15[6] are set to 0. When this pin is M, this bit is set to 0, ignored, and B0x15[6] is set to 1. When this pin is 1, this bit is set to 1 and B0x15[6] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 5 clk5_impedance0 RW 0x0 CLK5 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When this pin is 0, this bit and B0x15[5] are set to 0. When this pin is M, this bit is set to 0, ignored, and B0x15[5] is set to 1. When this pin is 1, this bit is set to 1 and B0x15[5] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 4 clk4_impedance0 RW 0x0 CLK4 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When this pin is 0, this bit and B0x15[4] are set to 0. When this pin is M, this bit is set to 0, ignored, and B0x15[4] is set to 1. When this pin is 1, this bit is set to 1 and B0x15[4] is set to 0. 0 = 85 ohm differential or 42.5 ohm single-ended 1 = 100 ohm differential or 50 ohm single-ended 3 clk3_impedance0 RW 0x0 CLK3 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When this pin is 0, this bit and B0x15[3] are set to 0. When this pin is M, this bit is set to 0, ignored, and B0x15[3] is set to 1. When this pin is 1, this bit is set to 1 and B0x15[3] is set to 0. 0 = 85 ohm differential or 42.5 ohm single-ended 1 = 100 ohm differential or 50 ohm single-ended 2 clk2_impedance0 RW 0x0 CLK2 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When this pin is 0, this bit and B0x15[2] are set to 0. When this pin is M, this bit is set to 0, ignored, and B0x15[2] is set to 1. When this pin is 1, this bit is set to 1 and B0x15[2] is set to 0. 0 = 85 ohm differential or 42.5 ohm single-ended 1 = 100 ohm differential or 50 ohm single-ended

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4.5.13 OUTPUT_REC_SEL_7_0

Output Impedance Select Register 1. 1 clk1_impedance0 RW 0x0 CLK1 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When this pin is 0, this bit and B0x15[1] are set to 0. When this pin is M, this bit is set to 0, ignored, and B0x15[1] is set to 1. When this pin is 1, this bit is set to 1 and B0x15[1] is set to 0. 0 = 85 ohm differential or 42.5 ohm single-ended 1 = 100 ohm differential or 50 ohm single-ended 0 clk0_impedance0 RW 0x0 CLK0 impedance select bit 0. The default value of this bit is set by the ZOUTSEL_tri pin. When this pin is 0, this bit and B0x15[0] are set to 0. When this pin is M, this bit is set to 0, ignored, and B0x15[0] is set to 1. When this pin is 1, this bit is set to 1 and B0x15[0] is set to 0. 0 = 85 ohm differential or 42.5 ohm single-ended 1 = 100 ohm differential or 50 ohm single-ended OUTPUT_REC_SEL_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 clk7_impedance1 RW 0x1 CLK7 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, this bit is set to 0 at power up and the appropriate value is set in B0x14[7]. When this pin is M, this bit is set to 1 at power up, B0x14[7] is set to 0 and ignored. 0 = See B0x14[7] 1 = 34 ohm differential or 17 ohm single-ended 6 clk6_impedance1 RW 0x1 CLK6 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, this bit is set to 0 at power up and the appropriate value is set in B0x14[6]. When this pin is M, this bit is set to 1 at power up, B0x14[6] is set to 0 and ignored. 0 = Source, see B0x14[6] 1 = 34 ohm differential or 17 ohm single-ended 5 clk5_impedance1 RW 0x1 CLK5 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, this bit is set to 0 at power up and the appropriate value is set in B0x14[5]. When this pin is M, this bit is set to 1 at power up, B0x14[5] is set to 0 and ignored. 0 = Source, see B0x14[5] 1 = 34 ohm differential or 17 ohm single-ended 4 clk4_impedance1 RW 0x1 CLK4 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, this bit is set to 0 at power up and the appropriate value is set in B0x14[4]. When this pin is M, this bit is set to 1 at power up, B0x14[4] is set to 0 and ignored. 0 = Source, see B0x14[4] 1 = 34 ohm differential or 17 ohm single-ended OUTPUT_IMPEDANCE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

R31DS0210EU0106 Rev.1.06 Page 42 May 11, 2026 RC193xx Datasheet

4.5.14 OUTPUT_SLEW_RATE_7_0

Output Slew Rate Select Register. 3 clk3_impedance1 RW 0x1 CLK3 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, this bit is set to 0 at power up and the appropriate value is set in B0x14[3]. When this pin is M, this bit is set to 1 at power up, B0x14[3] is set to 0 and ignored. 0 = Source, see B0x14[3] 1 = 34 ohm differential or 17 ohm single-ended 2 clk2_impedance1 RW 0x1 CLK2 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, this bit is set to 0 at power up and the appropriate value is set in B0x14[2]. When this pin is M, this bit is set to 1 at power up, B0x14[2] is set to 0 and ignored. 0 = Source, see B0x14[2] 1 = 34 ohm differential or 17 ohm single-ended 1 clk1_impedance1 RW 0x1 CLK1 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, this bit is set to 0 at power up and the appropriate value is set in B0x14[1]. When this pin is M, this bit is set to 1 at power up, B0x14[1] is set to 0 and ignored. 0 = Source, see B0x14[1] 1 = 34 ohm differential or 17 ohm single-ended 0 clk0_impedance1 RW 0x1 CLK0 impedance select bit 1. The default state of this bit is set by the ZOUTSEL_tri pin. When this pin is 0 or 1, This bit is set to 0 at power up and the appropriate value is set in B0x14[0]. When this pin is M, This bit is set to 1 at power up, B0x14[0] is set to 0 and ignored. 0 = Source, see B0x14[0] 1 = 34 ohm differential or 17 ohm single-ended OUTPUT_SLEW_RATE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 clk7_slewrate RW 0x1 CLK7 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 6 clk6_slewrate RW 0x1 CLK6 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 5 clk5_slewrate RW 0x1 CLK5 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate OUTPUT_REC_SEL_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

R31DS0210EU0106 Rev.1.06 Page 43 May 11, 2026 RC193xx Datasheet

4.5.15 LOW_LOW_DETECT

CLKIN Low-Low Detect Enable Register.

4.5.16 RECEIVER_CONTROL

CLKIN Configuration Register. 4 clk4_slewrate RW 0x1 CLK4 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 3 clk3_slewrate RW 0x1 CLK3 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 2 clk2_slewrate RW 0x1 CLK2 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 1 clk1_slewrate RW 0x1 CLK1 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 0 clk0_slewrate RW 0x1 CLK0 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate LOW_LOW_DETECT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:3 reserved RW 0x12 Reserved 2 low_low_det_enable RW 0x1 Enable low-low detect circuit on CLKIN0 and CLKIN1. Allows the device to detect a low-low condition on each CLKIN input and turn off the receiver. (Low- low is not a valid differential state). 0 = Disable 1 = Enable 1:0 reserved RW 0x0 Reserved RECEIVER_CONTROL Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 reserved RW 0x0 Reserved 3 ac_in1 RW 0x0 AC-couple CLKIN1. When AC-coupling the input clock, set this bit to enable internal bias circuitry on the CLKIN1. This eliminates the need for external bias components on the CLKIN1 side of the AC-coupling capacitor. 0 = Disable internal bias (DC-coupled) 1 = Enable internal bias (AC-coupled) OUTPUT_SLEW_RATE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

R31DS0210EU0106 Rev.1.06 Page 44 May 11, 2026 RC193xx Datasheet

4.5.17 WRITE_LOCK

Non-clearable SMBus Write Lock Register.

4.5.18 WRITE_LOCK_LOS_EVT

Clearable SMBus Write Lock and LOS Event Register. 2 rx_term1 RW 0x0 Enable internal termination for CLKIN1. Applications requiring receiver terminations may set this bit to enable internal termination resistors to ground on both the CLKIN1 and CLKIN1b pins. PCIe applications generally require Rx_TERM to be 0. 0 = Disable internal termination (PCIe) 1 = Enable internal termination 1 ac_in0 RW 0x0 AC-couple CLKIN0. When AC-coupling the input clock, set this bit to enable internal bias circuitry on the CLKIN0. This eliminates the need for external bias components on the CLKIN0 side of the AC-coupling capacitor. 0 = Disable internal bias (DC-coupled) 1 = Enable internal bias (AC-coupled) 0 rx_term0 RW 0x0 Enable internal termination for CLKIN0. Applications requiring receiver terminations may set this bit to enable internal termination resistors to ground on both the CLKIN0 and CLKIN0b pins. PCIe applications generally require Rx_TERM to be 0. 0 = Disable internal termination (PCIe) 1 = Enable internal termination WRITE_LOCK Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:1 reserved RW 0x0 Reserved 0 write_lock RW 0x0 Non-clearable SMBus write lock bit. When written to one, the SMBus control registers cannot be written. They may be read. This bit can only be cleared by cycling power. 0 = SMBus writes are not prohibited by WRITE_LOCK 1 = SMBus locked for writing WRITE_LOCK_LOS_EVT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:3 reserved RW1C 0x0 Reserved 2 los1_evt RW1C 0x0 CLKIN1 LOS event sticky bit. When high, indicates that an LOS event was detected on CLKIN1. Can be cleared by writing a 1 to it. 0 = No LOS1 event detected 1 = LOS1 event detected. 1 los0_evt RW1C 0x0 CLKIN0 LOS event sticky bit. When high, indicates that an LOS event was detected on CLKIN0. Can be cleared by writing a 1 to it. 0 = No LOS event detected 1 = LOS event detected. 0 write_lock_rw1c RW1C 0x0 Clearable SMBus write lock bit. When written to one, the SMBus control registers cannot be written. They may be read. This bit can only be cleared by writing a 1 to it. 0 = SMBus writes are not prohibited by WRITE_LOCK_RW1C 1 = SMBus locked for writing RECEIVER_CONTROL Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

R31DS0210EU0106 Rev.1.06 Page 45 May 11, 2026 RC193xx Datasheet 5. Applications Information

5.1 Inputs, Outputs, and Output Enable Control

The CLKIN/CLKINb inputs of the RC193xx devices have an internal bias network that prevents self-oscillation from a floating input clock condition.

5.1.1 Recommendations for Unused Inputs and Outputs

5.1.1.1 Unused Differential CLKIN Inputs

The CLKIN/CLKINb inputs of the RC19xxx devices have internal bias networks that protect the devices from a floating input clock condition. For RC193xx multiplexers that use only one input clock, the unused input can be left open. Renesas recommends that no trace be attached to unused CLKIN pins.

5.1.1.2 Unused Single-ended Control Inputs

The single-ended control pins have internal pull-up and/or internal pull-down resistors and do not require external resistors. They can be left floating if the default pin state is the desired state. If external resistors are needed to change the pin state or are desired for design robustness, 10kohm is the recommended value. Tri-level inputs are internally biased to VDD/2 and will indicate the mid (M) state if left floating.

5.1.1.3 Unused Differential CLK Outputs

All unused CLK outputs can be left floating. Renesas recommends that no trace be attached to unused CLK outputs. While not required (but highly recommended), the best design practice is to disable unused CLK outputs. This is easily accomplished with the dedicated OEb pin for each output.

5.1.1.4 Unused SMBus Clock and Data Pins

If the SMBus interface is not used, the clock and data pins must be pulled high with an external resistor. The two pins can share a resistor if there is no possibility of using the SMBus interface for debug purposes. If the interface might be used for debug, separate resistors should be used. Lightly loaded buses may use 10kohm pull-up resistors. Heavily loaded buses will require smaller pull-up resistor values. The SMBus pins are 3.3V tolerant and may be used with a 3.3V pull-up voltage

5.2 Differential CLKIN Configurations

The RC193xx input clock buffer supports four configurations: ▪ Direct connection to HCSL-level inputs ▪ Direct connection to LVDS-level inputs with external termination resistor ▪ Internal self-bias circuit for applications that externally AC-couple the input clock This feature is enabled by the AC_IN bit. ▪ Internal pull-down resistors (Rp) to terminate the clock input at the receiver. This feature is enabled by the Rx_TERM bit. Devices with multiple input clocks have individual AC_IN and Rx_TERM configuration bits for each input. The internal input clock terminations prevent reflections and are useful for non-PCIe applications, where the frequency and transmission line length vary from the 100MHz PCIe standard. The following table summarizes the CLKIN configuration bit settings for the various configurations that are displayed in Figure 13 to Figure 16.

5.3 Differential CLK Output Configurations

5.3.1 Internal CLK Source Termination Enabled (ZOUT_SEL_tri = 0 or 1)

when double-terminated, the CLK output swing will be half of the source-terminated values. Figure 17. Direct-Coupled Source-Terminated HCSL (ZOUT_SEL_tri = 0 or 1) Table 32. CLKIN Configuration Bits Figure 13. HCSL Input Levels (PCIe Standard) Figure 14. LVDS Input Levels Figure 15. External AC-Coupling Figure 16. Receiver Termination

Figure 18. Direct-Coupled Double-Terminated HCSL The RC193xx CLK outputs can directly drive AC-coupling capacitors without any source-termination components. RC193xx to other logic families such as LVDS, LVPECL, or CML. See AN-891 for examples. Figure 19. AC-Coupled Differential Input with Bias Network Table 33 contains values for the items in the above figures.

5.3.2 Internal CLK Source Termination Disabled (ZOUT_SEL_tri = M)

Table 21 for detailed specifications. This setting is intended for ZDIF =100 ohm systems. Figure 20. Direct-Coupled Receiver-Terminated HCSL Figure 21. Alternate Direct-Coupled Receiver-Terminated Input Table 33. Parameters for Internal CLK Source Termination Enabled

Table 34 contains values for the items in Figure 20 and Figure 21.

5.4 Power Down Tolerant Pins

than this may damage the part.

5.5 Flexible Startup Sequencing

CLKIN running before VDD is applied, and can have VDD applied and sit for extended periods with no input clock. RC193xx will not be completely powered down.

5.6 Loss of Signal and Automatic Clock Parking

The RC193xx devices have a Loss of Signal (LOS) circuit to detect the presence or absence of an input clock. Figure 22. LOSb De-assert Timing RC193xx Devices Note: The LOSb pin monitors the selected input clock in the RC193xx multiplexers. Table 34. Parameters for Direct-Coupled Receiver-Terminated Configurations Table 35. Flexible Startup Sequences

see Electrical Characteristics. Figure 23. LOSb Assert Timing

5.7 Output Enable Control

mechanisms indicate “enabled.” The following sections describe the two mechanisms.

5.7.1 SMBus Output Enable Bits

enable and disable states are glitch-free in both directions.

5.7.2 Output Enable (OEb) Pins

controlled outputs in a glitch-free, synchronous manner. outputs with this mechanism.

5.8 PCB Layout Recommendations

Buffer-Mux Layout Recommendations Application Note. is subject to change without revision of this document.

R31DS0210EU0106 Rev.1.06 Page 50 May 11, 2026 RC193xx Datasheet 7. Marking Diagrams RC19308A ▪ Lines 1 is the part number ▪ Line 2:

“$” indicates the mark code.
“YWW” indicates the last digit of the year and work week the part was assembled.
“***” indicates the assembly lot number. RC19308A001 ▪ Lines 1 and 2 comprise the part number. ▪ Line 3:
“$” indicates the mark code.
“YWW” indicates the last digit of the year and work week the part was assembled.
“***” indicates the assembly lot number. RC19304A ▪ Line 1 is the part number. ▪ Line 2:
“$” indicates the mark code.
“YWW” indicates the last digit of the year and work week the part was assembled.
“***” indicates the assembly lot number. RC19304A001 ▪ Lines 1 and 2 comprise the part number. ▪ Line 3:
“$” indicates the mark code.
“YWW” indicates the last digit of the year and work week the part was assembled.
“***” indicates the assembly lot number.

▪ Lines 1 and 2 comprise the part number (RC excluded). ▪ Line 2: “***” indicates the assembly lot number.

“$” indicates the mark code.
“YWW” indicates the last digit of the year and work week the part was assembled.

Table 36. Ordering Information

1.06 May 11, 2026 ▪ Added a caution statement to Absolute Maximum Ratings

1.05 Mar 30, 2026

1.04 Dec 17, 2025 ▪ Updated Table 13

1.03 Nov 11, 2025 ▪ Deleted non-applicable parameter description information from Table 7 to Table 12

1.02 Sep 12, 2025 ▪ Added footnote 3 to Table 23

1.01 Jun 28, 2025 Added PCB Layout Recommendations

1.00 Apr 4, 2025 Initial release

R31DS0210EU0106 Rev.1.06 Page 52 May 11, 2026 RC193xx Datasheet A. ECAD Design Information This information supports the development of the PCB ECAD model for this device. It is intended to be used by PCB designers. A.1 Part Number Indexing A.2 Symbol Pin Information A.2.1 48-VFQFPN Orderable Part Number Number of Pins Package Type Package Code/POD Number RC19308AGNA#BB0 48 VFQFPN PSC-4212-02/NDG48P2 RC19308AGNA#KB0 48 VFQFPN PSC-4212-02/NDG48P2 RC19308A001GNA#BB0 48 VFQFPN PSC-4212-02/NDG48P2 RC19308A001GNA#KB0 48 VFQFPN PSC-4212-02/NDG48P2 RC19304AGNL#BB0 28 VFQFPN PSC-4249-01-02/NDG28P1 RC19304AGNL#KB0 28 VFQFPN PSC-4249-01-02/NDG28P1 RC19304A001GNL#BB0 28 VFQFPN PSC-4249-01-02/NDG28P1 RC19304A001GNL#KB0 28 VFQFPN PSC-4249-01-02/NDG28P1 RC19302AGNT#BD0 20 VFQFPN PSC-4179-02/NDG20P2 RC19302AGNT#KD0 20 VFQFPN PSC-4179-02/NDG20P2 Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

1 ZOUTSEL_tri Input -

2 VDDDIG Power -

3 PWRGD_PWRDNb Input -

4 CLKIN0 Input -

5 CLKINb0 Input -

6 VDDIN0 Power -

7 SADR_tri0 Input -

8 CLKIN1 Input -

9 CLKINb1 Input -

10 SDATA I/O -

11 SCLK Input -

12 VDDIN1 Power -

13 VDDCLK_1 Power -

14 CLK7 Output -

15 CLKb7 Output -

16 OEb7 Input -

17 CLKSEL_tri Input -

18 OEb6 Input -

19 CLK6 Output -

20 CLKb6 Output -

21 VDDCLK_1 Power -

22 CLK5 Output -

23 CLKb5 Output -

24 OEb5 Input -

25 OEb4 Input -

26 CLK4 Output -

27 CLKb4 Output -

28 VDDCLK_1 Power -

29 LOSb Output -

30 VDDCLK_0 Power -

31 VDDA Power -

32 CLK3 Output -

33 CLKb3 Output -

34 OEb3 Input -

R31DS0210EU0106 Rev.1.06 Page 53 May 11, 2026 RC193xx Datasheet A.2.2 28-VFQFPN

35 OEb2 Input -

36 SADR_tri1 Input -

37 CLK2 Output -

38 CLKb2 Output -

39 VDDCLK_0 Power -

40 CLK1 Output -

41 CLKb1 Output -

42 SLEWRATE_SEL [1] Input -

43 OEb1 Input -

44 OEb0 Input -

45 CLK0 Output -

46 CLKb0 Output -

47 VDDCLK_0 Power -

48 GNDSUB Power -

This pin is AMPLITUDE_SEL for the RC19308A001. Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

1 PWRGD_PWRDNb Input -

2 CLKIN0 Input -

3 CLKINb0 Input -

4 VDDIN0 Power -

5 CLKIN1 Input -

6 CLKINb1 Input -

7 VDDIN1 Power -

8 CLKSEL_tri Input -

9 OEb6 Input -

10 CLK6 Output -

11 CLKb6 Output -

12 VDDCLK_1 Power -

13 CLK5 Output -

14 CLKb5 Output -

15 SLEWRATE_SEL [1]

This pin is AMPLITUDE_SEL for the RC19304A001. Input -

16 OEb5 Input -

17 LOSb Output -

18 VDDA Power -

19 OEb2 Input -

20 CLK2 Output -

21 CLKb2 Output -

22 VDDCLK_0 Power -

23 CLK1 Output -

24 CLKb1 Output -

25 OEb1 Input -

26 VDDDIG Power -

27 GNDSUB Power -

28 ZOUTSEL_tri Input -

Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

R31DS0210EU0106 Rev.1.06 Page 54 May 11, 2026 RC193xx Datasheet A.2.3 20-VFQFPN Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

1 CLKIN0 Input -

2 CLKINb0 Input -

3 VDDIN0 Power -

4 CLKIN1 Input -

5 CLKINb1 Input -

6 VDDIN1 Power -

7 CLKSEL_tri Input -

8 VDDCLK_1 Power -

9 CLK5 Output -

10 CLKb5 Output -

11 ZOUTSEL_tri Input -

12 OEb5 Input -

13 LOSb Output -

14 VDDA Power -

15 OEb2 Input -

16 CLK2 Output -

17 CLKb2 Output -

18 VDDCLK_0 Power -

19 VDDDIG Power -

20 GNDSUB Power -

R31DS0210EU0106 Rev.1.06Page 55 May 11, 2026 RC193xx Datasheet A.3 Symbol Parameters Orderable Part Number Qualification Mounting Type Min Operating Temperature Max Operating Temperature Min Input Voltage Max Input Voltage RoHS Output Type Number of Outputs Interface Max Output Frequency Phase Jitter Output Select Mode RC19308AGNA#BB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 8 SMBus 400 MHz 42.8 fs Slew Rate RC19308AGNA#KB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 8 SMBus 400 MHz 42.8 fs Slew Rate RC19308A001GNA#BB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 8 SMBus 400 MHz 42.8 fs Amplitude RC19308A001GNA#KB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 8 SMBus 400 MHz 42.8 fs Amplitude RC19304AGNL#BB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 4 SMBus 400 MHz 42.8 fs Slew Rate RC19304AGNL#KB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 4 SMBus 400 MHz 42.8 fs Slew Rate RC19304A001GNL#BB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 4 SMBus 400 MHz 42.8 fs Amplitude RC19304A001GNL#KB0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 4 SMBus 400 MHz 42.8 fs Amplitude RC19302AGNT#BD0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 2 SMBus 400 MHz 42.8 fs - RC19302AGNT#KD0 Industrial SMD -40 °C 105 °C 1.7 V 1.9 V Compliant LP-HCSL 2 SMBus 400 MHz 42.8 fs -

R31DS0210EU0106 Rev.1.06 Page 56 May 11, 2026 RC193xx Datasheet A.4 Footprint Design Information A.4.1 48-VFQFPN IPC Footprint Type Package Code/POD Number Number of Pins QFN PSC-4212-02/NDG48P2 48 Description Dimension Value (mm) Diagram Minimum body span (vertical side) Dmin 5.90 Maximum body span (vertical side) Dmax 6.10 Minimum body span (horizontal side) Emin 5.90 Maximum body span (horizontal side) Emax 6.10 Minimum Lead Width Bmin 0.15 Maximum Lead Width Bmax 0.25 Minimum Lead Length Lmin 0.30 Maximum Lead Length Lmax 0.50 Number of pins (vertical side) PinCountD 12 Number of pins (horizontal side) PinCountE 12 Distance between the center of any two adjacent pins (vertical side) PitchD 0.40 Distance between the center of any two adjacent pins (horizontal side) PitchE 0.40 Location of pin 1; S2 = corner of D side (top left), C1 = center of E side (center). Pin1 S2 Thermal pad Chamfer. If not present give hyphen (-). CH 0.35 Minimum thermal pad size (vertical side) D2min 4.10 Maximum thermal pad size (vertical side) D2max 4.30 Minimum thermal pad size (horizontal side) E2min 4.10 Maximum thermal pad size (horizontal side) E2max 4.30 Maximum Height Amax 1.00 Minimum Standoff Height A1min 0.00 Minimum Lead Thickness cmin 0.15 Maximum Lead Thickness cmax 0.25 Recommended Land Pattern Description Dimension Value (mm) Diagram Distance between left pad toe to right pad toe (horizontal side) ZE 6.30 Distance between top pad toe to bottom pad toe (vertical side) ZD 6.30 Distance between left pad heel to right pad heel (horizontal side) GE 5.20 Distance between top pad heel to bottom pad heel (vertical side) GD 5.20 Pad Width X 0.20 Pad Length Y 0.55

R31DS0210EU0106 Rev.1.06 Page 57 May 11, 2026 RC193xx Datasheet A.4.2 28-VFQFPN IPC Footprint Type Package Code/POD Number Number of Pins QFN PSC-4249-01-02/NDG28P1 28 Description Dimension Value (mm) Diagram Minimum body span (vertical side) Dmin 3.90 Maximum body span (vertical side) Dmax 4.10 Minimum body span (horizontal side) Emin 3.90 Maximum body span (horizontal side) Emax 4.10 Minimum Lead Width Bmin 0.15 Maximum Lead Width Bmax 0.25 Minimum Lead Length Lmin 0.30 Maximum Lead Length Lmax 0.50 Number of pins (vertical side) PinCountD 7 Number of pins (horizontal side) PinCountE 7 Distance between the center of any two adjacent pins (vertical side) PitchD 0.40 Distance between the center of any two adjacent pins (horizontal side) PitchE 0.40 Location of pin 1; S2 = corner of D side (top left), C1 = center of E side (center). Pin1 S2 Thermal pad Chamfer. If not present give hyphen (-). CH 0.35 Minimum thermal pad size (vertical side) D2min 2.50 Maximum thermal pad size (vertical side) D2max 2.70 Minimum thermal pad size (horizontal side) E2min 2.50 Maximum thermal pad size (horizontal side) E2max 2.70 Maximum Height Amax 1.00 Minimum Standoff Height A1min 0.00 Minimum Lead Thickness cmin 0.15 Maximum Lead Thickness cmax 0.25 Recommended Land Pattern Description Dimension Value (mm) Diagram Distance between left pad toe to right pad toe (horizontal side) ZE 4.30 Distance between top pad toe to bottom pad toe (vertical side) ZD 4.30 Distance between left pad heel to right pad heel (horizontal side) GE 3.20 Distance between top pad heel to bottom pad heel (vertical side) GD 3.20 Pad Width X 0.20 Pad Length Y 0.55

R31DS0210EU0106 Rev.1.06 Page 58 May 11, 2026 RC193xx Datasheet A.4.3 20-VFQFPN IPC Footprint Type Package Code/POD Number Number of Pins QFN PSC-4179-02/NDG20P2 20 Description Dimension Value (mm) Diagram Minimum body span (vertical side) Dmin 2.90 Maximum body span (vertical side) Dmax 3.10 Minimum body span (horizontal side) Emin 2.90 Maximum body span (horizontal side) Emax 3.10 Minimum Lead Width Bmin 0.15 Maximum Lead Width Bmax 0.25 Minimum Lead Length Lmin 0.30 Maximum Lead Length Lmax 0.50 Number of pins (vertical side) PinCountD 5 Number of pins (horizontal side) PinCountE 5 Distance between the center of any two adjacent pins (vertical side) PitchD 0.40 Distance between the center of any two adjacent pins (horizontal side) PitchE 0.40 Location of pin 1; S2 = corner of D side (top left), C1 = center of E side (center). Pin1 S2 Thermal pad Chamfer. If not present give hyphen (-). CH 0.35 Minimum thermal pad size (vertical side) D2min 1.55 Maximum thermal pad size (vertical side) D2max 1.75 Minimum thermal pad size (horizontal side) E2min 1.55 Maximum thermal pad size (horizontal side) E2max 1.75 Maximum Height Amax 1.00 Minimum Standoff Height A1min 0.00 Minimum Lead Thickness cmin 0.15 Maximum Lead Thickness cmax 0.25 Recommended Land Pattern Description Dimension Value (mm) Diagram Distance between left pad toe to right pad toe (horizontal side) ZE 3.30 Distance between top pad toe to bottom pad toe (vertical side) ZD 3.30 Distance between left pad heel to right pad heel (horizontal side) GE 2.20 Distance between top pad heel to bottom pad heel (vertical side) GD 2.20 Pad Width X 0.20 Pad Length Y 0.55

Pin 1 ID6.00 ±0.10 4.20 ±0.10 121324 37 480.40 ±0.10 0.20 0.40 0.90 ±0.10 0.05 Max.(0.20)Seating Plane0.08CC 0.354.20 4.20 6.300.200.40 5.206.30 PackageOutline (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN SIDE VIEW TOP VIEWBOTTOM VIEW © Renesas Electronics Corporation

2.60 4.303.20 4.30 2.60 (PCB Top View, NSMD Design) 0.35 Seating Plane Package Outline 4.00 ±0.10 4.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW SIDE VIEW0.08C 0.200.40 RECOMMENDED LAND PATTERN 0.90 ±0.10 C(0.20)0.05 Max 781415 2122 28 0.35 (0.30) 0.40 ±0.10 2.60 ±0.10 2.60 ±0.10 0.40 0.20 © Renesas Electronics Corporation

(PCB Top View, NSMD Design) Seating Plane 3.00 ±0.10 3.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW SIDE VIEW0.08C RECOMMENDED LAND PATTERN 0.90 ±0.10 C(0.20)0.05 Max 561011 1516 20min 0.20 0.40 ±0.10 1.65 ±0.10 1.65 ±0.10 0.40 0.20 Package Outline 1.65 3.302.20 1.65 1.65 0.200.40 A. PIN1 ID OPTION DETAILS A. Pin1 IDOption A. Pin1 IDOption © Renesas Electronics Corporation

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Product Information

RC19304A001GNL#KB0 specifications and overview.

Summary

PCIe Gen7 1.8V 2-Input Clock Mux Family with LOS Rev.1.06 May 11, 2026

Description

PCIe Gen7 1.8V 2-Input Clock Mux Family with LOS Rev.1.06 May 11, 2026

Source title RC19304A001GNL#KB0 Datasheet(PDF) - Renesas Technology Corp

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