RC19208AGNA#BB0

RC192XX_V01 RENESAS | Alldatasheet

Document overview

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• PDF pages: 63

Technical content

Datasheet sections

• 1.1 Signal Types
• 1.2 RC19216/RC19208 Pin Information
• 1.2.1 RC19216 Pin Assignments
• 1.2.2 RC19216 Pin Descriptions
• 1.2.3 RC19208 Pin Assignments
• 1.2.4 RC19208 Pin Descriptions
• 1.3 RC19204/RC19202 Pin Information
• 1.3.1 RC19204 Pin Assignments
• 1.3.2 RC19204 Pin Descriptions
• 1.3.3 RC19202 Pin Assignments
• 1.3.4 RC19202 Pin Descriptions
• 1.4 OEb Pin to CLK Output Mapping
• 2.1 Absolute Maximum Ratings
• 2.2 Recommended Operation Conditions
• 2.3 Thermal Specifications
• 2.4 Electrical Characteristics
• 2.4.1 PCIe Phase Jitter
• 2.4.2 Other Phase Jitter
• 2.4.3 Output Frequencies, Startup Time and LOS Timing
• 2.4.4 CLK (LP-HCSL) AC/DC Output Characteristics
• 2.4.5 CLKIN AC/DC Characteristics
• 2.4.6 Skew
• 2.4.7 I/O Signals
• 2.4.8 Power Supply Current
• 2.4.9 SMBus Electrical Characteristics
• 2.4.10 Side-band Interface
• 4.1 How to Write
• 4.2 How to Read
• 4.3 Write Lock Functionality (RC19208, RC19216)
• 4.4 SMBus Address Selection (RC19208, RC19216)
• 4.5 SMBus Register Set (RC19208, RC19216)
• 5.1 Inputs, Outputs, and Output Enable Control
• 5.1.1 Recommendations for Unused Inputs and Outputs
• 5.1.2 Differential CLKIN Configurations
• 5.1.3 Differential CLK Output Configurations
• 5.2 Power Down Tolerant Pins
• 5.3 Flexible Startup Sequencing
• 5.4 Loss of Signal and Automatic Clock Parking
• 5.5 Output Enable Control
• 5.5.1 SMBus Output Enable Bits
• 5.5.2 Output Enable (OEb) Pins
• 5.6 RC192xx Clock Multiplexer OEb Pins
• 5.6.1 Side-Band Interface (SBI)
• 5.6.2 Output Enable/Disable Priority
• 5.7 PCB Layout Recommendations

Features

▪ 2, 4, 8, or 16 Low-Power (LP) HCSL outputs saves up to 64 resistors ▪ 2:N or 2 x 1:N/2 modes (N is number of outputs) ▪ 85Ω or 100Ω output impedance ▪ Outputs drive both source-terminated and double- terminated loads ▪ Open-drain LOS output ▪ FPS allows inputs and clocks to be applied before power is applied or power to be applied with no input clock ▪ ACP cleanly parks outputs in low/low state when selected input clock is lost ▪ Spread-spectrum tolerant ▪ Up to eight output enable pins ▪ Selectable 4-wire Side-Band-Interface (SBI) for hardware output enable (RC19208, RC19216) ▪ SMBus write protection features (RC19216) ▪ CLKIN pins directly support HCSL or LVDS signaling levels ▪ 3 × 3 mm 20-VFQFPN to 6 × 6 mm 80-VFQFPN packages PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference (IR) with and without spread spectrum Figure 1. Simplified Block Diagram and Mux Logic

R31DS0020EU0116 Rev.1.16 Page 3 May 11, 2026 RC192xx Datasheet

1.1 Signal Types

1.2 RC19216/RC19208 Pin Information

Figure 2. RC19216/RC19208 Block Diagram is powered down (VDD is not present).

1.2.1 RC19216 Pin Assignments

Figure 3. 80-VFQFPN – Top View

1.2.2 RC19216 Pin Descriptions

Table 1. RC19216 Pin Descriptions A 1 GNDSUB GND Ground pin for substrate. A 2 CLKb0 O, DIF Complementary clock output. A 4 CLKb1 O, DIF Complementary clock output. A 5 CLK1 O, DIF True clock output. A 6 CLKb2 O, DIF Complementary clock output. A 7 CLK2 O, DIF True clock output. A 8 CLKb3 O, DIF Complementary clock output. A 9 CLK3 O, DIF True clock output. A 10 CLKb4 O, DIF Complementary clock output.

A 11 CLK4 O, DIF True clock output. A 12 CLKb5 O, DIF Complementary clock output. B 1 ZOUTSEL I, SE, PD Input to select differential output impedance. B 2 VDDCLK_0 PWR Power supply for clock output bank 0. B 3 NC NC No connect. There is no internal connection. Active low input for enabling output group A. See Table 5 for details. B 5 NC NC No connect. There is no internal connection. Active low input for enabling output group B. See Table 5 for details. B 7 NC NC No connect. There is no internal connection. Input that selects function of pins that are multiplexed between OE and SBI functionality. enabled. This pin must be strapped to its desired state. It cannot dynamically change. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins. B 9 VDDCLK_0 PWR Power supply for clock output bank 0. B 10 NC NC No connect. There is no internal connection. B 12 CLK5 O, DIF True clock output. C 1 VDDDIG PWR Digital power. C 2 NC NC No connect. There is no internal connection. Active low input for enabling output group B. See Table 5 for details. 0 = enable output, 1 = disable output. C 12 CLKb6 O, DIF Complementary clock output. D 1 CLKIN0 I, DIF True clock input. enters Power Down Mode, subsequent high assertions exit Power Down Mode. D 11 NC NC No connect. There is no internal connection. D 12 CLK6 O, DIF True clock output. E 1 CLKINb0 I, DIF Complementary clock input. E 2 NC NC No connect. There is no internal connection. Active low input for enabling output group D, or the clock pin for the Side-Band Interface. band Interface section and Table 5 for details. 0 = enable output, 1 = disable output. Side-Band mode: SBI clock input with internal pull-down. E 12 CLKb7 O, DIF Complementary clock output. Table 1. RC19216 Pin Descriptions (Cont.)

F 2 VDDIN0 PWR Power supply for clock input 0. F 11 VDDA PWR Power supply for analog circuitry. F 12 CLK7 O, DIF True clock output. G 1 CLKIN1 I, DIF True clock input. G 2 NC NC No connect. There is no internal connection. G 11 NC NC No connect. There is no internal connection. G 12 VDDCLK_0 PWR Power supply for clock output bank 0. H 1 CLKINb1 I, DIF Complementary clock input. OD, PDT Data pin for SMBus interface. H 11 VDDCLK_1 PWR Power supply for clock output bank 1. of signal on the input clock. J 1 SCLK I, SE, PDT Clock pin of SMBus interface. J 2 VDDIN1 PWR Power supply for clock input 1. J 11 NC NC No connect. There is no internal connection. J 12 CLKb8 O, DIF Complementary clock output. K 1 VDDCLK_1 PWR Power supply for clock output bank 1. K 2 NC NC No connect. There is no internal connection. Active low input for enabling output group E, or the data pin for the Side-Band Interface. band Interface section and Table 5 for details. 0 = enable output, 1 = disable output. SBI shift-register data input. K 12 CLK8 O, DIF True clock output. L 1 CLK15 O, DIF True clock output. band Interface section and Table 5 for details. NOTE: This pin is NOT PDT. 0 = enable output, 1 = disable output. SBI shift register data output. L 3 NC NC No connect. There is no internal connection. internal pull-up and pull-down resistor to bias a floating pin to the mid-point. 0 = CLKIN0 selected for all outputs. 1 = CLKIN1 selected for all outputs. M = CLKIN0 goes to bank 0 and CLKIN1 goes to bank 1. L 5 NC NC No connect. There is no internal connection. the Side-band Interface section and Table 5 for details. 0 = enable output, 1 = disable output. 0 = disable SBI shift register, 1 = enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register.

L 7 VDDCLK_1 PWR Power supply for clock output bank 1. L 8 NC NC No connect. There is no internal connection. L 9 NC NC No connect. There is no internal connection. L 10 NC NC No connect. There is no internal connection. Active low input for enabling output group F. Refer to the Table 5 for details. 0 = enable output, 1 = disable output. L 12 CLKb9 O, DIF Complementary clock output. M 1 CLKb15 O, DIF Complementary clock output. M 2 CLK14 O, DIF True clock output. M 3 CLKb14 O, DIF Complementary clock output. M 4 CLK13 O, DIF True clock output. M 5 CLKb13 O, DIF Complementary clock output. M 6 CLK12 O, DIF True clock output. M 7 CLKb12 O, DIF Complementary clock output. M 8 CLK11 O, DIF True clock output. M 9 CLKb11 O, DIF Complementary clock output. M 10 CLK10 O, DIF True clock output. M 11 CLKb10 O, DIF Complementary clock output. M 12 CLK9 O, DIF True clock output.

1.2.3 RC19208 Pin Assignments

Figure 4. 48-VFQFPN – Top View

1.2.4 RC19208 Pin Descriptions

Table 2. RC19208 Pin Descriptions 1 ZOUTSEL I, SE, PD Input to select differential output impedance.

3 PWRGD_PWRDNb I, SE,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 4 CLKIN0 I, DIF True clock input. 5 CLKINb0 I, DIF Complementary clock input. 6 VDDIN0 PWR Power supply for clock input 0.

7 SADR_tri0 I, SE, PD,

8 CLKIN1 I, DIF True clock input. 9 CLKINb1 I, DIF Complementary clock input.

10 SDATA I/O, SE,

OD, PDT Data pin for SMBus interface. 11 SCLK I, SE, PDT Clock pin of SMBus interface.

• 48 47 46 45 44 43 42 41 40 39 38 37 ZOUTSE L 1 36 SAD R_tri1 V DDDIG 2 35 OEb_C PWRGD_PWRDNb 3 34 OEb_D_SBI_CLK CLKIN0 4 33 CLKb7 CLKINb0 5 32 CLK7 V DDIN0 6 31 V DDA SA DR_tr i0 7 30 V DDCLK_0 CLKIN1 8 29 LOSb CLKINb1 9 28 V DDCLK_1 SDATA 10 27 CLKb8 SCLK 11 26 CLK8 VDDIN1 12 25 OE b_E_SBI_IN 13 14 15 16 17 18 19 20 21 22 23 24 VDDCLK_1 CLK15 CLKb15 OEb_H_SBI_OUT CLKSEL_tri OEb_G_SHFT_LDb CLK12 CLKb12 VDDCLK_1 CLK11 CLKb11 OEb_F RC19208 48-VFQFPN Connect to EPAD to GND Top View

12 VDDIN1 PWR Power supply for clock input 1. 13 VDDCLK_1 PWR Power supply for clock output bank 1. 14 CLK15 O, DIF True clock output. 15 CLKb15 O, DIF Complementary clock output.

16 OEb_H_SBI_OUT I/O, PU,

Interface section for details. Note: This pin is NOT PDT. 0 = enable output, 1 = disable output. SBI shift register data output.

17 CLKSEL_tri I, SE, PD,

internal pull-up and pull-down resistor to bias a floating pin to the mid-point. 0 = CLKIN0 selected for all outputs. 1 = CLKIN1 selected for all outputs. M = CLKIN0 goes to bank 0 and CLKIN1 goes to bank 1.

18 OEb_G_SHFT_LDb

the Side-band Interface section for details. 0 = enable output, 1 = disable output. 0 = disable SBI shift register, 1 = enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 19 CLK12 O, DIF True clock output. 20 CLKb12 O, DIF Complementary clock output. 21 VDDCLK_1 PWR Power supply for clock output bank 1. 22 CLK11 O, DIF True clock output. 23 CLKb11 O, DIF Complementary clock output.

24 OEb_F I, SE,

Table 33 for output control details. 0 = enable output, 1 = disable output.

25 OEb_E_SBI_IN

Active low input for enabling output group E, or the data pin for the Side-Band Interface. band Interface section for details. 0 = enable output, 1 = disable output. SBI shift-register data input. 26 CLK8 O, DIF True clock output. 27 CLKb8 O, DIF Complementary clock output. 28 VDDCLK_1 PWR Power supply for clock output bank 1.

29 LOSb O, OD,

30 VDDCLK_0 PWR Power supply for clock output bank 0. 31 VDDA PWR Power supply for analog circuitry. 32 CLK7 O, DIF True clock output. 33 CLKb7 O, DIF Complementary clock output. Table 2. RC19208 Pin Descriptions (Cont.)

34 OEb_D_SBI_CLK

Active low input for enabling output group D, or the clock pin for the Side-Band Interface. band Interface section for details. 0 = enable output, 1 = disable output. Side-Band mode: SBI clock input with internal pull-down.

35 OEb_C I, SE, PU,

Table 33 for output control details. 0 = enable output, 1 = disable output.

36 SADR_tri1 I, SE, PD,

37 CLK4 O, DIF True clock output. 38 CLKb4 O, DIF Complementary clock output. 39 VDDCLK_0 PWR Power supply for clock output bank 0. 40 CLK3 O, DIF True clock output. 41 CLKb3 O, DIF Complementary clock output.

42 SBI_ENQ I, SE, PD,

Input that selects function of pins that are multiplexed between OE and SBI functionality. enabled. This pin must be strapped to its desired state. It cannot dynamically change. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

43 OEb_B I, SE, PU,

Table 33 for output control details. 0 = enable output, 1 = disable output.

44 OEb_A I, SE, PU,

Table 33 for output control details. 0 = enable output, 1 = disable output. 45 CLK0 O, DIF True clock output. 46 CLKb0 O, DIF Complementary clock output. 47 VDDCLK_0 PWR Power supply for clock output bank 0. 48 GNDSUB GND Ground pin for substrate.

1.3 RC19204/RC19202 Pin Information

Figure 5. RC19204/RC19202 Block Diagram

1.3.1 RC19204 Pin Assignments

Figure 6. 28-VFQFPN – Top View

1.3.2 RC19204 Pin Descriptions

Table 3. RC19204 Pin Descriptions

1 PWRGD_PWRDNb I, SE,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 2 CLKIN0 I, DIF True clock input. 3 CLKINb0 I, DIF Complementary clock input. 4 VDDIN0 PWR Power supply for clock input 0. 5 CLKIN1 I, DIF True clock input. 6 CLKINb1 I, DIF Complementary clock input. 7 VDDIN1 PWR Power supply for clock input 1.

• 2 82 72 62 52 42 32 2 PWRGD_PWRDNb 1 21 CLKb5 CLKIN0 2 20 CLK5 CLKINb0 3 19 OEb_C VDDIN0 4 18 VDDA CLKIN1 5 17 LOSb CLKINb1 6 16 OEb_F VDDIN1 7 15 NC 8 9 10 11 12 13 14CLKSEL_tri OEb_G CLK12 CLKb12 VDDCLK_1 CLK10 CLKB10 RC19204 28-VFQFPN Connect to EPAD to GND Top View

8 CLKSEL_tri I, SE, PD,

internal pull-up and pull-down resistor to bias a floating pin to the mid-point. 0 = CLKIN0 selected for all outputs. 1 = CLKIN1 selected for all outputs. M = CLKIN0 goes to bank 0 and CLKIN1 goes to bank 1.

9 OEb_G I, SE, PU,

Table 5 for details.0 = enable output, 1 = disable output. 10 CLK12 O, DIF True clock output. 11 CLKb12 O, DIF Complementary clock output. 12 VDDCLK_1 PWR Power supply for clock output bank 1. 13 CLK10 O, DIF True clock output. 14 CLKB10 O, DIF Complementary clock output. 15 NC NC No connect. There is no internal connection.

16 OEb_F I, SE, PU,

section and Table 5 for details. 0 = enable output, 1 = disable output.

17 LOSb O, OD,

18 VDDA PWR Power supply for analog circuitry.

19 OEb_C I, SE, PU,

0 = enable output, 1 = disable output. 20 CLK5 O, DIF True clock output. 21 CLKb5 O, DIF Complementary clock output. 22 VDDCLK_0 PWR Power supply for clock output bank 0. 23 CLK3 O, DIF True clock output. 24 CLKb3 O, DIF Complementary clock output.

25 OEb_B I, SE, PU,

0 = enable output, 1 = disable output. 26 VDDDIG PWR Digital power. 27 GNDSUB GND Ground pin for substrate. 28 ZOUTSEL I, SE, PD Input to select differential output impedance. 29 EPAD GND Connect to ground. Table 3. RC19204 Pin Descriptions (Cont.)

1.3.3 RC19202 Pin Assignments

Figure 7. 20-VFQFPN – Top View

1.3.4 RC19202 Pin Descriptions

Table 4. RC19202 Pin Descriptions 1 CLKIN0 I, DIF True clock input. 2 CLKINb0 I, DIF Complementary clock input. 3 VDDIN0 PWR Power supply for clock input 0. 4 CLKIN1 I, DIF True clock input. 5 CLKINb1 I, DIF Complementary clock input. 6 VDDIN1 PWR Power supply for clock input 1.

7 CLKSEL_tri I, SE, PD,

internal pull-up and pull-down resistor to bias a floating pin to the mid-point. 0 = CLKIN0 selected for all outputs. 1 = CLKIN1 selected for all outputs. M = CLKIN0 goes to bank 0 and CLKIN1 goes to bank 1. 8 VDDCLK_1 PWR Power supply for clock output bank 1. 9 CLK10 O, DIF True clock output. 10 CLKb10 O, DIF Complementary clock output.

11 ZOUTSEL I, SE, PD Input to select differential output impedance

12 OEb_F I, SE, PU,

section and Table 5 for details. 0 = enable output, 1 = disable output.

13 LOSb O, OD,

14 VDDA PWR Power supply for analog circuitry.

15 OEb_C I, SE, PU,

0 = enable output, 1 = disable output. 16 CLK5 O, DIF True clock output. 17 CLKb5 O, DIF Complementary clock output. 18 VDDCLK_0 PWR Power supply for clock output bank 0. 19 VDDDIG PWR Digital power.

• 20 19 18 17 16 CLKIN0 1 15 OE b_C CLKINb0 2 14 VD D A V DDIN0 3 13 LOSb CLKIN1 4 12 OE b_F CLKINb15 11 ZOUTSE L 6789 1 0VDDIN1 CLKSEL_tri VDDCLK_1 CLK10 CLKb10 20-VFQFPN Connect to EPAD to GND Top View

1.4 OEb Pin to CLK Output Mapping

20 GNDSUB GND Ground pin for substrate. 21 EPAD GND Connect to ground. Table 5. Output Enable Mapping by Device[1]

1. Assuming Side-Band Interface is not enabled.

Table 4. RC19202 Pin Descriptions (Cont.)

2.1 Absolute Maximum Ratings

conditions can adversely impact product reliability and result in failures not covered by warranty.

2.2 Recommended Operation Conditions

conditions in this table must be met to guarantee device functionality and performance. Table 6. Absolute Maximum Ratings

1. Pins designated Power Down Tolerant (PDT) in the pin description table.
2. Pins not designated Power Down Tolerant (PDT) in the pin description table.

Table 7. Recommended Operating Conditions

2.3 Thermal Specifications

Table 8. Thermal Specifications

2.4 Electrical Characteristics

2.4.1 PCIe Phase Jitter

approximate the impact of SSC. Table 9. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Unselected CLKIN Off) – Normal Conditions[1][2][3][4]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 7.0. See the Test Loads section of the
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample
3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
4. Differential input swing = 1600mV and input slew rate = 3.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
7. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
8. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
9. The PCI Express Base Specification 7.0, Revision 0.7 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

the PCIe device in an SRIS system, the channel is very short and the user may choose to use this more relaxed value as the jitter limit.

Table 10. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Unselected CLKIN Off) – Degraded Conditions[1][2][3][4]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 7.0. See the Test Loads section of the
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample
3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
4. Differential input swing = 800mV and input slew rate = 1.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
7. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
8. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
9. The PCI Express Base Specification 7.0, Revision 0.7 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

the PCIe device in an SRIS system, the channel is very short and the user may choose to use this more relaxed value as the jitter limit.

Table 11. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Both CLKIN Running) – Normal Conditions[1][2][3][4]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 7.0. See the Test Loads section of the
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample
3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
4. Differential input swing = 1600mV and input slew rate = 3.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
7. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
8. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
9. The PCI Express Base Specification 7.0, Revision 0.7 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

the PCIe device in an SRIS system, the channel is very short and the user may choose to use this more relaxed value as the jitter limit.

Table 12. PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Both CLKIN Running) – Degraded Conditions[1][2][3][4]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 7.0. See the Test Loads section of the
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample
3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
4. Differential input swing = 800mV and input slew rate = 1.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
7. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
8. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
9. The PCI Express Base Specification 7.0, Revision 0.7 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

the PCIe device in an SRIS system, the channel is very short and the user may choose to use this more relaxed value as the jitter limit.

Table 13. PCIe Refclk Phase Jitter (CLKSEL_tri = M, Both CLKIN Running) – Normal Conditions[1][2][3][4]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 7.0. See the Test Loads section of the
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample
3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
4. Differential input swing = 1600mV and input slew rate = 3.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
7. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
8. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
9. The PCI Express Base Specification 7.0, Revision 0.7 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

the PCIe device in an SRIS system, the channel is very short and the user may choose to use this more relaxed value as the jitter limit.

Table 14. PCIe Refclk Phase Jitter (CLKSEL_tri = M, Both CLKIN Running) – Degraded Conditions[1][2][3][4]

1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 7.0. See the Test Loads section of the
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample
3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
4. Differential input swing = 800mV and input slew rate = 1.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
7. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
8. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
9. The PCI Express Base Specification 7.0, Revision 0.7 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

the PCIe device in an SRIS system, the channel is very short and the user may choose to use this more relaxed value as the jitter limit.

2.4.2 Other Phase Jitter

2.4.3 Output Frequencies, Startup Time and LOS Timing

Table 15. Non-PCIe Refclk Phase Jitter (CLKSEL_tri = 0 or 1, Unselected CLKIN Off) [1][2][3]

1. See Test Loads for test configuration. Measured with one input at 100MHz and the other at 156.25MHz.
2. SMA100B used as signal source.
3. RC19xxx devices meet all legacy QPI/UPI specifications by meeting the PCIe and DB2000Q specifications listed in this document.
4. Differential input swing = 1600mV and input slew rate = 3.5V/ns
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed. CLKSEL_tri

= M is only recommended for PCIe applications.

1. Differential input swing = 800mV and input slew rate = 1.5V/ns

Table 16. Output Frequencies, Startup Time and LOS Timing

1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output. PWRGD_PGWRDNb
2. VDD stable, measured from de-assertion of PWRGD_PWRDNb.
3. The clock detect circuit does not qualify the accuracy of the input clock.
4. PWRGD_PWRDNb high. The clock detect circuit will park the outputs in a low/low state within this time.
5. PWRGD_PWRDNb high. The clock detect circuit will drive the outputs to a high/low state within this time and then begin clocking the outputs.

2.4.4 CLK (LP-HCSL) AC/DC Output Characteristics

Table 17. 85Ω CLK AC/DC Characteristics for Source-Terminated 100MHz PCIe [1]

1. Standard high impedance load with C L = 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 7.0 or from relevant x86 processor specifications, whichever is
3. Measured from single-ended waveform.
4. Defined as the maximum instantaneous voltage including overshoot.
5. Defined as the minimum instantaneous voltage including undershoot.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
9. Measured from differential waveform.
10. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 18. 100Ω CLK AC/DC Characteristics for Source-Terminated 100MHz PCIe [1]

1. Standard high impedance load with C L = 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 7.0 or from relevant x86 processor specifications, whichever is
3. Measured from single-ended waveform.
4. Defined as the maximum instantaneous voltage including overshoot.
5. Defined as the minimum instantaneous voltage including undershoot.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
9. Measured from differential waveform.
10. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 19. 85Ω CLK AC/DC Characteristics for Non-PCIe Applications, Source-Terminated Loads [1]

1. Standard high impedance load with C L = 2pF. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 20. 100Ω CLK AC/DC Characteristics for Non-PCIe Applications, Source-Terminated Loads [1]

1. Standard high impedance load with C L = 2pF. See Test Loads.
2. Measured from single-ended waveform.

1. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
2. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
3. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
4. Measured from differential waveform.

Table 21. 85ohm CLK AC/DC Output Characteristics for Non-PCIe Applications, Double-Terminated Loads [1]

1. Both Tx and Rx are terminated (double-terminated) with CL= 2pF. This reduces amplitude by 50%. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 22. 100ohm CLK AC/DC Output Characteristics for Non-PCIe Applications, Double-Terminated Loads [1]

2.4.5 CLKIN AC/DC Characteristics

Figure 8. Clock Input Bias Network

1. Both Tx and Rx are terminated (double-terminated) with CL= 2pF. This reduces amplitude by 50%. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 23. CLKIN AC/DC Characteristics

1. See the PCIe Phase Jitter tables for values required for performance.
2. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero-crossing.

2.4.6 Skew

2.4.7 I/O Signals

Table 24. Output-to-Output and Input-to-Output Skew [1]

1. This parameter is defined in accordance with JEDEC Standard 65.
2. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 25. I/O Electrical Characteristics [1] Bi-level, single-ended control inputs. the specific device for details. the specific device for details. specific device for details. specific device for details.

2.4.8 Power Supply Current

1. For SCLK and SDATA, see the SMBus Electrical Characteristics table.
2. These values are compliant with JESD8C.01.
3. Measured from single-ended waveform.

Table 26. Power Supply Current [1][2]

1. Output voltage set to 800mV.

Table 26. Power Supply Current [1][2] (Cont.)

2.4.9 SMBus Electrical Characteristics

Figure 9. SMBus Target Timing Diagram Table 27. SMBus DC Electrical Characteristics [1]

1. V OH is governed by the VPUP, the voltage rail to which the pull-up resistors are connected.
2. See I/O Electrical Characteristics table.

Table 28. SMBus AC Electrical Characteristics

1. Power must be applied and PWRGD_PWRDNb must be a 1 for the SMBus to be active.

2.4.10 Side-band Interface

Figure 10. Side-Band Interface Timing

1. A host (master) should not drive the clock at a frequency below the minimum fSMB. Further, the operating clock frequency should not be reduced

buffering and so forth for longer than 100 µs in a non-periodic way.

1. A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the VIH,MIN of the SMBCLK signal) to bridge the

undefined region of the falling edge of SMBCLK.

1. Target devices may have caused other target devices to hold SDA low. This is the maximum time that a device can hold SMBDAT low after the
2. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of

than tTIMEOUT,MAX. Typical device examples include the host controller, and embedded controller, and most devices that can control the SMBus. a stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds the SMBCLK low for tTIMEOUT,MAX or longer.

1. The device has the option of detecting a timeout if the SMBDATA pin is also low for this time.
2. t HIGH,MAX provides a simple guaranteed method for hosts to detect bus idle conditions. A host can assume that the bus is free if it detects that the

clock and data signals have been high for greater than tHIGH,MAX.

1. t LOW:MEXT is the cumulative time a host device is allowed to extend its clock cycles within each byte of a message as defined from START-to-ACK,

be greater than tLOW:MEXT on a given byte. This parameter is measured with a full-speed target device as the sole target of the host.

1. The rise and fall time measurement limits are defined as follows:
2. Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

Current O/P Config. Next O/P Config.

Figure 11. AC/DC Test Load for Differential Outputs (Standard PCIe Source-Terminated) Table 29. Side-Band Interface AC/DC Electrical Characteristics

1. Refers to the output frequency for the selected clock.
2. Control input must be monotonic from 20% to 80% of input swing.

Table 30. Parameters for AC/DC Test Load (Standard PCIe Source-Terminated)

R31DS0020EU0116 Rev.1.16 Page 37 May 11, 2026 RC192xx Datasheet 4. General SMBus Serial Interface Information

4.1 How to Write

▪ Controller (host) sends a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) sends the byte count = X ▪ Renesas clock will acknowledge ▪ Controller (host) starts sending Byte N through Byte N+X-1 ▪ Renesas clock will acknowledge each byte one at a time ▪ Controller (host) sends a stop bit

4.2 How to Read

▪ Controller (host) will send a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) will send a separate start bit ▪ Controller (host) sends the read address ▪ Renesas clock will acknowledge ▪ Renesas clock will send the data byte count = X ▪ Renesas clock sends Byte N+X-1 ▪ Renesas clock sends Byte L through Byte X (if X(H) was written to Byte 7) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit Index Block Write Operation Controller (Host) Renesas (Target/Receiver) T starT bit Target Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK P stoP bit Index Block Read Operation Controller (Host) Renesas (Target/Receiver) T starT bit Target Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Target Address RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not P stoP bit

4.3 Write Lock Functionality (RC19208, RC19216)

4.4 SMBus Address Selection (RC19208, RC19216)

4.5 SMBus Register Set (RC19208, RC19216)

Table 33. RC19208 and RC19216 SMBus Register Set

2 RESERVED RESERVED 7:0 RO 0 RESERVED -

3 OEb_PIN_READBACK_1

4 SBEN_READBACK_

5 VENDOR_REVISION_ID

6 DEVICE_ID DEVICE_ID 7:0 RO See

Table 33. RC19208 and RC19216 SMBus Register Set (Cont.)

7 BYTE_COUNT

8 SBI_MASK_0

9 SBI_MASK_1

10 CLOCK_SELECT

11 SBI_READBACK_0

12 SBI_READBACK_1

13 RESERVED RESERVED 7:0 RW 0 RESERVED -

14 RC19216

14 RC19208

15 RC19216

15 RC19208

16 RESERVED RESERVED 7:0 RW 0 RESERVED -

17 LPHCSL_AMP_CTRL

18 PD_RESTORE_LOSb_

19 RESERVED RESERVED 7:0 RW 0x7 RESERVED -

20 OUTPUT IMPEDANCE 7_0

21 OUTPUT IMPEDANCE

35 CLKIN CONFIG

5.1 Inputs, Outputs, and Output Enable Control

5.1.1 Recommendations for Unused Inputs and Outputs

5.1.1.1 Unused Differential CLKIN Inputs

open. Renesas recommends that no trace be attached to unused CLKIN pins.

5.1.1.2 Unused Single-ended Control Inputs

change the pin state or are desired for design robustness, 10kohm is the recommended value.

5.1.1.3 Unused Differential CLK Outputs

38 WRITE_LOCK

39 WRITE_LOCK_LOS_EVT

5.1.1.4 Unused SMBus Clock and Data Pins

may be used for debug, separate resistors should be used. 10kohm is the recommended value.

5.1.2 Differential CLKIN Configurations

This feature is enabled by the AC_IN bit. ▪ Internal pull-down resistors (Rp) to terminate the clock input at the receiver. This feature is enabled by the Rx_TERM bit. and transmission line length vary from the 100MHz PCIe standard. Figure 14 through Figure 17 illustrate the above items. Figure 14. HCSL Input Levels (PCIe Standard) Figure 15. LVDS Input Levels Figure 16. External AC-Coupling Figure 17. Receiver Termination

5.1.3 Differential CLK Output Configurations

5.1.3.1 Direct-Coupled HCSL Loads

HCSL-level inputs with no external components. They support both 85ohm and 100ohm differential impedances. half of the source-terminated values.

5.1.3.2 AC-Coupled non-HCSL Loads

terminating the RC19xxx CLK outputs to other logic families such as LVDS, LVPECL, or CML, see AN-891. Figure 18 to Figure 20 show the various CLK output configurations. Figure 18. Direct-Coupled Source-Terminated HCSL Figure 19. Direct-Coupled Double-Terminated HCSL Figure 20. AC-Coupled

5.2 Power Down Tolerant Pins

before it has received power. Figure 21 provides an example of a PDT call-out in a datasheet.

5.3 Flexible Startup Sequencing

Figure 21. Example: Power Down Tolerant Pin Descriptions CLKIN running before VDD is applied, and can have VDD applied and sit for extended periods with no input clock.

5.4 Loss of Signal and Automatic Clock Parking

up. CLKIN is represented differentially in Figure 23. Table 34. Flexible Startup Sequences

Figure 22. LOSb De-assert Timing RC192xx Devices Note: The LOSb pin monitors the selected input clock in the RC192xx multiplexers. Figure 23. LOSb Assert Timing

5.5 Output Enable Control

when all three mechanisms indicate “enabled.” The following sections describe the three mechanisms.

5.5.1 SMBus Output Enable Bits

between the enable and disable states are glitch-free in both directions.

5.5.2 Output Enable (OEb) Pins

low/low state. All OEb pins enable and disable the controlled outputs in a glitch-free, synchronous manner.

5.6 RC192xx Clock Multiplexer OEb Pins

5.6.1 Side-Band Interface (SBI)

This section does not apply to the RC19202 because it does not have a side-band interface. individual clock output. As buffers grow in output count, dedicated OEb pins become problematic for two reasons. First, the clock buffer pin count becomes much larger than it otherwise would be, resulting in a larger package. outgrows the GPIO pins of an FPGA or micro-controller. simple 3-wire (4-wire if the SBI_OUT pin is used) interface that can control all outputs across multiple devices. pins per output. It is protocol-free, hardware-oriented and runs at speeds up to 25MHz, much faster than SMBus. Table 35. RC19216 and RC19208 OEb Mapping

1. See the OEb_ASSIGNMENT registers in the RC192xx datasheet.

Table 36. RC19204 and RC19202 OEb Mapping

1. See the OEb_ASSIGNMENT registers in the RC192xx datasheet.

R31DS0020EU0116 Rev.1.16 Page 53 May 11, 2026 RC192xx Datasheet Another SBI advantage is that it is active after power is applied and before PWRGD is asserted. External logic can disable specific outputs before PWRGD is asserted, and can then dynamically adjust the output run state during device operation. The SBI can make the adjustments much more rapidly than SMBus. The RC192xx 4-wire SBI interface consists of the SBI_IN, SBI_CLK, SHFT_LDb, and SBI_OUT pins. The RC192xx SBI is enabled by strapping the SBI_ENQ pin to 1. When enabled, various OEb pins become the SBI interface. The exact pins that are multiplexed vary with device. The SBI_ENQ pin strap takes effect as soon as power is applied and is not dependent on the assertion of PWRGD_PWRDNb to 1. Because of this, the SBI_ENQ must be static and cannot change once power is applied. If SBI_ENQ is 0 when power is applied, the SBI is disabled and has no impact on enabling or disabling outputs. The SBI consists of a shift register, an SMBus readback register (of the shift register contents), and an SMBus MASK register. The SBI shifts a bit stream containing the enable/disable pattern into the shift register. A 1 enables an output and a 0 disables an output. All shift-register bits default to 1 at power up, indicating an enabled state. This means that the SBI can be used to disable outputs at power up because the default is enabled. The SBI has its own SBI_CLK and does not need a running CLKIN to shift in an enable/disable pattern. This provides utmost flexibility for setting output run state before the SMBus becomes active or before the CLKIN is applied. When the SBI indicates enabled, the standard SMBus output enable bits and OEb pins can control the outputs. The SBI feeds common output enable/disable synchronization logic ensuring glitch-free enable and disable of outputs. Note: The glitch-free synchronization logic requires the CLKIN be running to enable or disable the outputs with this mechanism. If the application does not use the SBI, the SBI_ENQ pin can be tied to 0, and the entire SBI has no impact on enabling or disabling clock outputs. The SBI Mask registers allow the user to block the disable function of the SBI via the SMBus. The SBI Mask registers default to 0 at power-up, allowing the SBI shift register bits to disable their respective output. After asserting the PWRGD_PWRDNb pin high, the SMBus is active and the SBI mask registers can be configured via SMBus to mask off (block) the SBI disable function. In other words, setting and SBI Mask bit to 1 forces the SBI to always indicate “enable” for the respective output. This allows the user to prevent the SBI from accidentally turning off a critical output. The RC192xx clock multiplexer provides the ability to read back the SBI shift register contents via the SMBus. The SMBus readback values update on each falling edge of SHFT_LDb. Note: The SBI shift register can only be read using the SMBus; the SMBus cannot be used to load it. Figure 24 shows the high-level functional description of SBI.

Figure 24. Side-band Interface High-Level Functional Diagram (RC192xx shown)

5.6.1.1 Using the SBI

Byte 1 bit 7. The last bit shifted in would be the output enable/disable for CLK0, which is in Byte 0, bit 0. Figure 25. RC19216 Side Band Shift Order Count is equal to the number of outputs in each device. Figure 26. RC19208 Side Band Shift Order

5.6.1.2 Side-Band Interface Timing

Characteristics, see Table 29. Figure 27. Side-Band Interface Functional Timing

5.6.1.3 Side-Band Interface Connection Topologies

device. When using the daisy-chain topology, the user must shift a complete set of bits for the combined devices. the SBI_CLK and SBI_IN pins. at the cost of an additional GPIO per device.

Figure 28. Side-Band Interface Star Topology controller. It uses the SBI_OUT pin of one device to drive the SBI_IN pin of the next device in the daisy chain. the SBI bit stream consists of 48 bits. Figure 29. Side-Band Interface Daisy-Chain Topology AC-coupled buffer is used, SBI_CLK must be continuously free-running. DC-coupled buffers are recommended.

5.6.2 Output Enable/Disable Priority

enabled in order for the output to be enabled. A logical representation of the priority logic is shown in Figure 30. Figure 30. Output Enable/Disable Priority (Logical)

R31DS0020EU0116 Rev.1.16 Page 57 May 11, 2026 RC192xx Datasheet

5.7 PCB Layout Recommendations

Proper layout is critical to achieving the full functionality and efficiency of the device. For information on how to support optimal electrical performance, effective thermal management, and overall system reliability, see the PCIe Buffer-Mux Layout Recommendations Application Note. 6. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revision of this document. 7. Marking Diagrams RC19216 80-VFQFPN ▪ Lines 2 is the part number ▪ Line 3:

• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. RC19208 48-VFQFPN ▪ Lines 1 and 2 are the part number ▪ Line 3:
• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. RC19204 28-VFQFPN ▪ Line 2 is the part number ▪ Line 3:
• “$$” is the factory code.
• “Y” is the last digit of the year and “WW” the work week the part was assembled.
• “*” is the 3-digit sequential code RC19202 20-VFQFPN ▪ Line 1 is the part number ▪ Line 2 “A” is part of the part number and “*” is the sequential code ▪ Line 3:
• “$” denotes the mark location code.
• “YWW” denotes the assembly date: “Y” is the last digit of the year and “WW” are the last two digits of work week.

R31DS0020EU0116 Rev.1.16 Page 58 May 11, 2026 RC192xx Datasheet 8. Ordering Information 9. Revision History Part Number Carrier Type Number of Outputs Output Impedance Package Temp. Range RC19216AGN6#BD0 Tray 16 Selectable 6 × 6 mm, 0.5mm pitch 80-VFQFPN -40 to +105°C RC19216AGN6#KD0 Tape and Reel (EIA-481-D) RC19208AGNA#BB0 Tray 8 Selectable 6 × 6 mm, 0.4mm pitch 48-VFQFPN -40 to +105°C RC19208AGNA#KB0 Tape and Reel (EIA-481-D) RC19204AGNL#BB0 Tray 4 Selectable 4 × 4 mm, 0.4mm pitch 28-VFQFPN -40 to +105°C RC19204AGNL#KB0 Tape and Reel (EIA-481-D) RC19202AGNT#BD0 Tray 2 Selectable 3 × 3 mm, 0.4mm pitch 20-VFQFPN -40 to +105°C RC19202AGNT#KD0 Tape and Reel (EIA-481-D) Revision Date Description

1.16 May 11, 2026 ▪ Added a caution statement to Absolute Maximum Ratings

1.15 Apr 21, 2026 ▪ Updated the marking diagram information for the RC19204 (see Marking Diagrams)

1.14 Dec 8, 2025

▪ Changed references to PCI Express Base Specification 6.0 to PCI Express Base Specification 7.0 ▪ Changed master/slave terminology to host/target, where appropriate ▪ Updated the formatting of Table 15

1.12 Jun 28, 2025 Added PCB Layout Recommendations

1.11 May 4, 2025 ▪ Completed a minor non-technical update

1.10 Apr 30, 2025

▪ Changed the description of all NC pins in RC19216 Pin Descriptions ▪ Changed pin 15 to NC from DNC in RC19204 Pin Assignments and RC19204 Pin Descriptions ▪ Updated the specification values in Table 9 to Table 14

1.09 Mar 31, 2025 ▪ Added PU to the Type information for the OEb_H_SBI_OUT pin in Table 1 and Table 2

1.08 Jul 30, 2024 ▪ Updated references to the 6 x 6 package to 80-VFQFPN. No technical changes were made

1.07 Jul 26, 2023

▪ Updated title in Figure 22 ▪ Updated text to RC192xx(A) from RC19xxxA or RC190xxA in section 5.6.1 ▪ Updated Figure 24 ▪ Updated text in section 5.6.1.2 ▪ Updated part numbers in section 5.6.1.3 ▪ Removed references and figures that referenced RC190xx.

1.06 Jun 29, 2023

▪ Updated RC19216 information for pins E11, K11, L2, L6, and L11 in Table 1 ▪ Updated RC19208 information for pins 16, 18, 24, 25, 34, 35, 43, and 44 in Table 2 ▪ Updated RC19204 information for pins 9, 16, 19, and 25 in Table 3 ▪ Updated RC19202 information for pins 12 and 15 in Table 4

1.05 Nov 17, 2022 ▪ Changed t SLEW to 6 from 4 in Table 29

1.04 Oct 17, 2022 ▪ Completed a minor, non-technical update to Table 19

▪ Completed other minor changes

1.03 July 6, 2022 ▪ Corrected labeling of multiplexer inputs in all block diagrams

1.02 May 4, 2022 ▪ Updated the marking information for the RC19202

1.01 Apr 11, 2022

▪ Updated Pin Type of all pins beginning with OEb to properly indicate internal pull-down (PD) resistors ▪ Minor reformatting of Pin Descriptions to reduce required space in Pin Description tables and to provide consistency across devices 1.00 Feb 24, 2022 Initial release.

M

12 BCDEFGHJKL

Ø0.225 6.00 ±0.10 SIDE VIEW 6.00 ±0.10Pin 1Index 0.50 5.50 Ref0.25 ±0.10 0.352.80 ±0.10 0.80 ±0.10C 5.500.50 5.500.500.352.80 2.80RECOMMENDED LAND PATTERN(PCB Top View, NSMD Design) 0.08C © Renesas Electronics Corporation

Pin 1 ID6.00 ±0.10 4.20 ±0.10 121324 37 480.40 ±0.10 0.20 0.40 0.90 ±0.10 0.05 Max.(0.20)Seating Plane0.08CC 0.354.20 4.20 6.300.200.40 5.206.30 PackageOutline (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN SIDE VIEW TOP VIEWBOTTOM VIEW © Renesas Electronics Corporation

2.60 4.303.20 4.30 2.60 (PCB Top View, NSMD Design) 0.35 Seating Plane Package Outline 4.00 ±0.10 4.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW SIDE VIEW0.08C 0.200.40 RECOMMENDED LAND PATTERN 0.90 ±0.10 C(0.20)0.05 Max 781415 2122 28 0.35 (0.30) 0.40 ±0.10 2.60 ±0.10 2.60 ±0.10 0.40 0.20 © Renesas Electronics Corporation

(PCB Top View, NSMD Design) Seating Plane 3.00 ±0.10 3.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW SIDE VIEW0.08C RECOMMENDED LAND PATTERN 0.90 ±0.10 C(0.20)0.05 Max 561011 1516 20min 0.20 0.40 ±0.10 1.65 ±0.10 1.65 ±0.10 0.40 0.20 Package Outline 1.65 3.302.20 1.65 1.65 0.200.40 A. PIN1 ID OPTION DETAILS A. Pin1 IDOption A. Pin1 IDOption © Renesas Electronics Corporation

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