RC191XX_V01 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1.1 Signal Types
  • 1.2 RC19108 Pin Information
  • 1.2.1 RC19108 Pin Assignments
  • 1.2.2 RC19108 Pin Descriptions
  • 1.3 RC19108A001 Pin Information
  • 1.3.1 RC19108A001 Pin Assignments
  • 1.3.2 RC19108A001 Pin Descriptions
  • 1.4 RC19104 Pin Information
  • 1.4.1 RC19104 Pin Assignments
  • 1.4.2 RC19104 Pin Descriptions
  • 1.5 RC19104A001 Pin Information
  • 1.5.1 RC19104A001 Pin Assignments
  • 1.5.2 RC19104A001 Pin Descriptions
  • 1.6 RC19102 Pin Information
  • 1.6.1 RC19102 Pin Assignments
  • 1.6.2 RC19102 Pin Descriptions
  • 2.1 Absolute Maximum Ratings
  • 2.2 Recommended Operating Conditions
  • 2.3 Thermal Specifications
  • 2.4 Electrical Specifications
  • 2.4.1 Additive Phase Jitter
  • 2.4.2 Output Frequencies, Startup Time, and LOS Timing
  • 2.4.3 CLK AC/DC Output Characteristics
  • 2.4.4 CLKIN AC/DC Characteristics
  • 2.4.5 Output-to-Output and Input-to-Output Skew
  • 2.4.6 I/O Electrical Characteristics
  • 2.4.7 Power Supply Current
  • 2.4.8 SMBus Electrical Characteristics
  • 4.1 How to Write
  • 4.2 How to Read
  • 4.3 SMBus Bit Types
  • 4.4 Write Lock Functionality
  • 4.5 SMBus Address Decode
  • 4.6 SMBus Registers
  • 4.6.1 OUTPUT_ENABLE
  • 4.6.2 OEB_PIN_READBACK
  • 4.6.3 LOS_CONFIG
  • 4.6.4 VENDOR_REVISION_ID
  • 4.6.5 DEVICE_ID
  • 4.6.6 BYTE_COUNT
  • 4.6.7 SLEW_AMP_SELECT
  • 4.6.8 INPUT_PULLUP_PULLDOWN_4
  • 4.6.9 AMP_CTRL_ALT
  • 4.6.10 AMP_CTRL_DEF
  • 4.6.11 PD_RESTORE_LOSb_CONFIG
  • 4.6.12 OUTPUT_IMPEDANCE_7_0
  • 4.6.13 OUTPUT_REC_SEL_7_0

Features

▪ Very low additive phase jitter:

  • PCIe Gen5: 5.9fs RMS (typ)
  • PCIe Gen6: 3.5fs RMS (typ)
  • PCIe Gen7: 2.4fs RMS (typ)
  • DB2000Q: 10fs RMS (typ)
  • 12kHz - 20MHz (156.25MHz): 33fs RMS (typ.) ▪ Power Down Tolerant (PDT) inputs ▪ Flexible Startup Sequencing (FSS) ▪ Automatic Clock Parking (ACP) upon loss of CLKIN ▪ Spread-spectrum tolerant ▪ CLKIN accepts HCSL or LVDS signal levels ▪ -40 to +105°C, 1.8V ± 5% operation ▪ Devices provide:
  • Pin or SMBus selectable 34Ω, 85Ω, or 100Ω differential output impedance
  • Pin or SMBus selectable output slew rate
  • Pin or SMBus selectable output amplitude
  • 9 SMBus addresses plus write protection

Figure 1. RC191xx Block Diagram

  1. RC19102 does not have these pins.

R31DS0190EU0108 Rev.1.08 Page 3 May 11, 2026 RC191xx Datasheet

R31DS0190EU0108 Rev.1.08 Page 4 May 11, 2026 RC191xx Datasheet 1. Pin Information

1.1 Signal Types

Term Description [1] 1. Some pins have both internal pull-up and pull-down resistors which bias the pins to VDD/2. Other pins are multi- mode and have an internal pull-up or internal pull-down depending on the mode. I Input O Input OD Open Drain Output I/O Bi-Directional PD Pull-down PU Pull-up Z Tristate D Driven X Don’t care SE Single ended DIF Differential PWR 1.8 V power GND Ground PDT Power Down Tolerant: These signals tolerate being driven when the device is powered down. For information, see Absolute Maximum Ratings.

1.2 RC19108 Pin Information

1.2.1 RC19108 Pin Assignments

Figure 2. RC19108 40-VFQFPN – Top View

1.2.2 RC19108 Pin Descriptions

Table 1. RC19108 Pin Descriptions

1 LOSb O, OD,

of signal on the input clock.

2 SLEWRATE_SEL I, SE, PU,

Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate.

3 SADR_tri1 I, SE, PD,

and tri-level input thresholds in the electrical tables.

4 SADR_tri0 I, SE, PD,

and tri-level input thresholds in the electrical tables.

5 SDATA I/O, SE,

OD Data pin for SMBus interface. 6 SCLK I, SE Clock pin of SMBus interface. 8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input. 10 VDDCLK PWR Clock Power supply. 11 ZOUTSEL_tri I, SE, PD Input to select differential output impedance.

  • 40 39 38 37 36 35 34 33 32 31 LOSb 13 0 OEb3 SLEWRATE_sel 22 9 CLKb3 SADR_tri1 32 8 CLK3 SADR_tri0 42 7 OEb4 SDATA 52 6 VDDCLK SCLK 62 5 CLKb4 VDDDIG 72 4 CLK4 CLKIN 82 3 CLKb5 CLKINb 92 2 CLK5 VDDCLK 10 21 OEb5 11 12 13 14 15 16 17 18 19 20ZOUTSEL_tri PWRGD_PWRDNb VDDCLK OEb7 CLK7 CLKb7 CLK6 CLKb6 OEb6 VDDCLK RC19108 Top View Connect EPAD to ground

12 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 13 VDDCLK PWR Clock power supply.

14 OEb7 I, SE, PU,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 15 CLK7 O, DIF True clock output. 16 CLKb7 O, DIF Complementary clock output. 17 CLK6 O, DIF True clock output. 18 CLKb6 O, DIF Complementary clock output.

19 OEb6 I, SE, PU,

Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 20 VDDCLK PWR Clock power supply.

21 OEb5 I, SE, PU,

Active low input for enabling output 5. 0 = Enable output, 1 = Disable output. 22 CLK5 O, DIF True clock output. 23 CLKb5 O, DIF Complementary clock output. 24 CLK4 O, DIF True clock output. 25 CLKb4 O, DIF Complementary clock output. 26 VDDCLK PWR Clock Power supply.

27 OEb4 I, SE, PU,

Active low input for enabling output 4. 0 = Enable output, 1 = Disable output. 28 CLK3 O, DIF True clock output. 29 CLKb3 O, DIF Complementary clock output.

30 OEb3 I, SE, PU,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output. 31 CLK2 O, DIF True clock output. 32 CLKb2 O, DIF Complementary clock output.

33 OEb2 I, SE, PU,

Active low input for enabling output 2. 0 = Enable output, 1 = Disable output.

34 OEb1 I, SE, PU,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 35 CLK1 O, DIF True clock output. 36 CLKb1 O, DIF Complementary clock output. 37 VDDCLK PWR Clock power supply. 38 CLK0 O, DIF True clock output. 39 CLKb0 O, DIF Complementary clock output.

40 OEb0 I, SE, PU,

Active low input for enabling output 0. 0 = Enable output, 1 = Disable output. 41 EPAD GND Connect Epad to ground. Table 1. RC19108 Pin Descriptions (Cont.)

1.3 RC19108A001 Pin Information

1.3.1 RC19108A001 Pin Assignments

Figure 3. RC19108 40-VFQFPN – Top View

1.3.2 RC19108A001 Pin Descriptions

Table 2. RC19108A001 Pin Descriptions of signal on the input clock.

2 AMPLITUDE_SEL I, SE, PD,

and tri-level input thresholds in the electrical tables. and tri-level input thresholds in the electrical tables. OD Data pin for SMBus interface. 6 SCLK I, SE Clock pin of SMBus interface. 8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input. 10 VDDCLK PWR Clock Power supply.

  • 40 39 38 37 36 35 34 33 32 31 LOSb 13 0 OEb3 AMPLITUDE_SEL 22 9 CLKb3 SADR_tri1 32 8 CLK3 SADR_tri0 42 7 OEb4 SDATA 52 6 VDDCLK SCLK 62 5 CLKb4 VDDDIG 72 4 CLK4 CLKIN 82 3 CLKb5 CLKINb 92 2 CLK5 VDDCLK 10 21 OEb5 11 12 13 14 15 16 17 18 19 20ZOUTSEL_tri PWRGD_PWRDNb VDDCLK OEb7 CLK7 CLKb7 CLK6 CLKb6 OEb6 VDDCLK RC19108A001 Top View Connect EPAD to ground

11 ZOUTSEL_tri I, SE, PD Input to select differential output impedance. enters Power Down Mode, subsequent high assertions exit Power Down Mode. 13 VDDCLK PWR Clock power supply. Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 15 CLK7 O, DIF True clock output. 16 CLKb7 O, DIF Complementary clock output. 17 CLK6 O, DIF True clock output. 18 CLKb6 O, DIF Complementary clock output. Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 20 VDDCLK PWR Clock power supply. Active low input for enabling output 5. 0 = Enable output, 1 = Disable output. 22 CLK5 O, DIF True clock output. 23 CLKb5 O, DIF Complementary clock output. 24 CLK4 O, DIF True clock output. 25 CLKb4 O, DIF Complementary clock output. 26 VDDCLK PWR Clock Power supply. Active low input for enabling output 4. 0 = Enable output, 1 = Disable output. 28 CLK3 O, DIF True clock output. 29 CLKb3 O, DIF Complementary clock output. Active low input for enabling output 3. 0 = Enable output, 1 = Disable output. 31 CLK2 O, DIF True clock output. 32 CLKb2 O, DIF Complementary clock output. Active low input for enabling output 2. 0 = Enable output, 1 = Disable output. Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 35 CLK1 O, DIF True clock output. 36 CLKb1 O, DIF Complementary clock output. 37 VDDCLK PWR Clock power supply. 38 CLK0 O, DIF True clock output. 39 CLKb0 O, DIF Complementary clock output. Active low input for enabling output 0. 0 = Enable output, 1 = Disable output. 41 EPAD GND Connect Epad to ground. Table 2. RC19108A001 Pin Descriptions (Cont.)

1.4 RC19104 Pin Information

1.4.1 RC19104 Pin Assignments

Figure 4. RC19104 28-VFQFPN – Top View

1.4.2 RC19104 Pin Descriptions

Table 3. RC19104 Pin Descriptions

1 SADR_tri1 I, SE, PD,

and the tri-level input thresholds in the electrical tables.

2 SADR_tri0 I, SE, PD,

and the tri-level input thresholds in the electrical tables.

3 SDATA I/O, SE,

OD Data pin for SMBus interface. 4 SCLK I, SE Clock pin of SMBus interface. 6 CLKIN I, DIF True clock input. 7 CLKINb I, DIF Complementary clock input. 8 ZOUTSEL_tri I, SE, PD Input to select differential output impedance.

9 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 10 VDDCLK PWR Clock power supply.

11 OEb7 I, SE, PU,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 12 CLK7 O, DIF True clock output. 13 CLKb7 O, DIF Complementary clock output.

14 OEb5 I, SE, PD,

Active low input for enabling output 5. 0 = Enable output, 1 = Disable output.

  • 2 82 72 62 52 42 32 2 SADR_tri1 1 21 OEb3 SADR_tri0 2 20 CLKb3 SDATA 3 19 CLK3 SCLK 4 18 VDDCLK VDDDIG 5 17 CLKb5 CLKIN 6 16 CLK5 CLKINb 7 15 VDDCLK 8 9 10 11 12 13 14ZOUTSEL_tri PWRGD_PWRDNb VDDCLK OEb7 CLK7 CLKb7 OEb5 RC19104 Top view Connect epad to ground

15 VDDCLK PWR Clock power supply. 16 CLK5 O, DIF True clock output. 17 CLKb5 O, DIF Complementary clock output. 18 VDDCLK PWR Clock power supply. 19 CLK3 O, DIF True clock output. 20 CLKb3 O, DIF Complementary clock output.

21 OEb3 I, SE,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

22 OEb1 I, SE,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 23 CLK1 O, DIF True clock output. 24 CLKb1 O, DIF Complementary clock output. 25 VDDCLK PWR Clock power supply.

27 SLEWRATE_SEL I, SE, PU,

Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate.

28 LOSb O, OD,

of signal on the input clock. 29 EPAD GND Connect to ground. Table 3. RC19104 Pin Descriptions (Cont.)

1.5 RC19104A001 Pin Information

1.5.1 RC19104A001 Pin Assignments

Figure 5. RC19104A100 28-VFQFPN – Top View

1.5.2 RC19104A001 Pin Descriptions

Table 4. RC19104A100 Pin Descriptions and the tri-level input thresholds in the electrical tables. and the tri-level input thresholds in the electrical tables. OD Data pin for SMBus interface. 4 SCLK I, SE Clock pin of SMBus interface. 6 CLKIN I, DIF True clock input. 7 CLKINb I, DIF Complementary clock input. 8 ZOUTSEL_tri I, SE, PD Input to select differential output impedance. enters Power Down Mode, subsequent high assertions exit Power Down Mode. 10 VDDCLK PWR Clock power supply. Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 12 CLK7 O, DIF True clock output. 13 CLKb7 O, DIF Complementary clock output.

  • 2 82 72 62 52 42 32 2 SADR_tri1 1 21 OEb3 SADR_tri0 2 20 CLKb3 SDATA 3 19 CLK3 SCLK 4 18 VDDCLK VDDDIG 5 17 CLKb5 CLKIN 6 16 CLK5 CLKINb 7 15 VDDCLK 8 9 10 11 12 13 14ZOUTSEL_tri PWRGD_PWRDNb VDDCLK OEb7 CLK7 CLKb7 OEb5 RC19104A001 Top view Connect epad to ground

Active low input for enabling output 5. 0 = Enable output, 1 = Disable output. 15 VDDCLK PWR Clock power supply. 16 CLK5 O, DIF True clock output. 17 CLKb5 O, DIF Complementary clock output. 18 VDDCLK PWR Clock power supply. 19 CLK3 O, DIF True clock output. 20 CLKb3 O, DIF Complementary clock output. Active low input for enabling output 3. 0 = Enable output, 1 = Disable output. Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 23 CLK1 O, DIF True clock output. 24 CLKb1 O, DIF Complementary clock output. 25 VDDCLK PWR Clock power supply.

27 AMPLITUDE_SEL I, SE, PD,

of signal on the input clock. 29 EPAD GND Connect to ground. Table 4. RC19104A100 Pin Descriptions (Cont.)

1.6 RC19102 Pin Information

1.6.1 RC19102 Pin Assignments

Figure 6. RC19102 20-VFQFPN – Top View

1.6.2 RC19102 Pin Descriptions

Table 5. RC19102 Pin Descriptions 1 CLKIN0 I, DIF, PDT True clock input. 2 CLKINb0 I, DIF, PDT Complementary clock input. 3 VDDCLK PWR Clock power supply. 8 VDDCLK PWR Clock power supply. 9 CLK5 O, DIF True clock output. 10 CLKb5 O, DIF Complementary clock output. 11 ZOUTSEL_tri I, SE, PD Input to select differential output impedance.

12 OEb5 I, SE, PU,

Active low input for enabling output 5. 1 = disable output, 0 = enable output.

13 LOSb O, OD,

of signal on the input clock. 14 VDDCLK PWR Clock power supply.

15 OEb3 I, SE, PU,

Active low input for enabling output 3. 1 = disable output, 0 = enable output. 16 CLK3 O, DIF True clock output. 17 CLKb3 O, DIF Complementary clock output. 18 VDDCLK PWR Clock power supply. 19 VDDDIG PWR Digital power. 20 GNDSUB GND Ground pin for substrate. 21 EPAD GND Connect to ground.

  • 20 19 18 17 16 CLKIN0 1 15 OEb3 CLKINb0 2 14 VDDA VD DIN 0 3 13 LOSb NC 4 12 OEb5 NC 5 11 ZOUTSEL_tri 6789 1 0NC NC VDDCLK CLK5 CLKb5 RC19102 Top View Connect to EPAD to G ND

2.1 Absolute Maximum Ratings

conditions can adversely impact product reliability and result in failures not covered by warranty. Table 6. Absolute Maximum Ratings

2.2 Recommended Operating Conditions

  1. Inputs not designated Power Down Tolerant (PDT) in the pin description tables.
  2. Inputs designated Power Down Tolerant (PDT) in the pin description tables.
  3. The V PUP voltage may be applied before main VDD is applied. The LOSb pin is PDT to this voltage, not to 3.6V.

Table 7. Recommended Operation Conditions (power ramps must be monotonic).

2.3 Thermal Specifications

Table 8. Thermal Characteristics

2.4 Electrical Specifications

2.4.1 Additive Phase Jitter

Table 9. PCIe Refclk Phase Jitter - Normal Conditions [1][2][3]

  1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

  1. Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83.

  1. Differential input swing ≥ 1600mV and input slew rate ≥ 3.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe
  2. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
  3. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
  4. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
  5. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
  6. Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
  7. The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

Table 10. PCIe Refclk Phase Jitter - Degraded Conditions [1][2][3]

  1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0. For the exact measurement setup,

see Test Loads. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements.

  1. Jitter measurements are made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of

the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83.

  1. Differential input swing ≥ 800mV and input slew rate ≥ 1.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe

Gen1) must be less than the jitter specification listed.

  1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
  2. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
  3. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
  4. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
  5. Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
  6. The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification limits,

PCIe device in an SRIS system, the channel is very short and the user can choose to use this more relaxed value as the jitter limit.

2.4.2 Output Frequencies, Startup Time, and LOS Timing

Table 11. Non-PCIe Refclk Phase Jitter [1][2][3]

  1. See Test Loads for test configuration.
  2. SMA100B used as signal source.
  3. The RC19xxx devices meet all legacy QPI/UPI specifications by meeting the PCIe and DB2000Q specifications listed in this document.
  4. Differential input swing = 1,600mV and input slew rate = 3.5V/ns.
  5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
  6. Differential input swing = 800mV and input slew rate = 1.5V/ns.

Table 12. Output Frequencies, Startup Time, and LOS Timing

  1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output.

PWRGD_PWRDNb tied to VDD in this case.

  1. VDD stable, measured from de-assertion of PWRGD_PWRDNb.
  2. The clock detect circuit does not qualify the accuracy of the input clock. The first input clock must appear to release the power on reset

and enable the LOS circuit at power up.

  1. PWRGD_PWRDNb high. The Automatic Clock Parking (ACP) circuit - if enabled - will park the outputs in a low/low state within this time. See

Byte4, bit 4, LOSb_ACP_ENABLE.

  1. PWRGD_PWRDNb high. The device will drive the outputs to a high/low state within this time and then begin clocking the outputs.

2.4.3 CLK AC/DC Output Characteristics

Table 13. 85Ω CLK AC/DC Characteristics – Source-Terminated 100MHz PCIe Applications [1]

  1. Standard high impedance load with C L= 2pF. For more information, see Figure 9, ZOUTSEL_tri = 0.
  2. The specification limits are taken from either the PCIe Base Specification Revision 7.0 or from relevant x86 processor specifications, whichever is
  3. Measured from single-ended waveform.
  4. Defined as the maximum instantaneous voltage including overshoot.
  5. Defined as the minimum instantaneous voltage including undershoot.
  6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
  7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
  8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
  9. Measured from differential waveform.
  10. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

  1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 14. 100Ω CLK AC/DC Characteristics – Source-Terminated 100MHz PCIe Applications [1]

  1. Standard high impedance load with C L= 2pF. For more information, see Figure 9, ZOUTSEL_tri = 1.
  2. The specification limits are taken from either the PCIe Base Specification Revision 7.0 or from relevant x86 processor specifications, whichever
  3. Measured from single-ended waveform.
  4. Defined as the maximum instantaneous voltage including overshoot.
  5. Defined as the minimum instantaneous voltage including undershoot.
  6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
  7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
  8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in

VCROSS for any particular system.

  1. Measured from differential waveform.
  2. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

  1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate.

Table 15. 85 ohm CLK AC/DC Characteristics – Source-Terminated, Non-PCIe Applications [1]

  1. Standard high impedance load with C L= 2pF. For more information, see Figure 9, ZOUTSEL_tri = 0.
  2. Measured from single-ended waveform.
  3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
  4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
  5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
  6. Measured from differential waveform.

Table 16. 85 ohm CLK AC/DC Characteristics – Double-Terminated, Non-PCIe Applications [1]

  1. Both Tx and Rx are terminated (double-terminated) with C L= 2pF. This reduces amplitude by 50%. For more information, see Figure 10,
  1. Measured from single-ended waveform.
  2. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
  3. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
  4. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
  5. Measured from differential waveform.

Table 17. 100 ohm CLK AC/DC Characteristics – Source-Terminated, Non-PCIe Applications [1]

  1. Standard high impedance load with C L= 2pF. For more information, see Figure 9, ZOUTSEL_tri = 1.
  2. Measured from single-ended waveform.
  3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
  4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
  5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
  6. Measured from differential waveform.

Table 18. 100 ohm CLK AC/DC Characteristics – Double-Terminated, Non-PCIe Applications [1]

  1. Both Tx and Rx are terminated (double-terminated) with C L= 2pF. This reduces amplitude by 50%. For more information, see Figure 10,
  2. Measured from single-ended waveform.
  3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
  4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
  5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
  6. Measured from differential waveform.

Table 19. 34ohm CLK AC/DC Characteristics - Rx-Terminated, Non-PCIe Applications [1]

  1. ZOUTSEL_tri = M. This setting turns off the source termination, provided approximately 75% of the source-terminated amplitude at the receiver
  2. Measured from single-ended waveform.
  3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
  4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
  5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
  6. Measured from differential waveform.

Table 18. 100 ohm CLK AC/DC Characteristics – Double-Terminated, Non-PCIe Applications [1] (Cont.)

2.4.4 CLKIN AC/DC Characteristics

Figure 7. Clock Input Bias Network

2.4.5 Output-to-Output and Input-to-Output Skew

Table 20. CLKIN AC/DC Characteristics for DC-Coupled Operation[1]

  1. See the Additive Phase Jitter tables for values required for performance. The CLKIN is designed for a ground-referenced differential input where
  2. Low/Low is an invalid differential state. LOW-LOW_DETECT allows the receiver turn itself off when such a condition is detected
  3. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero-crossing. Table 21. Output-to-Output and Input-to-Output Skew [1]

  1. These parameters are measured with the loads in Figure 10.
  2. This parameter is defined in accordance with JEDEC Standard 65.
  3. Defined as the time between to output rising edge and the input rising edge that caused it.

2.4.6 I/O Electrical Characteristics

Table 22. I/O Electrical Characteristics

  1. For SCLK and SDATA, see the SMBus DC Electrical Characteristics table.
  2. These values are compliant with JESD8-7A 1.8V Normal Range.

Single-ended inputs, unless otherwise listed.

2.4.7 Power Supply Current

Table 23. Power Supply Current [1][2][3]

  1. For more information, see Test Loads.
  2. Output voltage set to 800mV. Slew rate has negligible effect on current consumption, so only fast is listed.
  3. Total operating current is obtained by adding (I DDCLK x number of outputs used) + IDDCLK_CORE + IDDDIG. Power down current is obtained by
  4. The value specified is for one output pair. Multiply this value by the number of outputs in use.

2.4.8 SMBus Electrical Characteristics

This section applies to all devices except the RC19102 because the RC19102 does not have an SMBus interface. Figure 8. SMBus Target Timing Diagram Table 24. SMBus DC Electrical Characteristics [1]

  1. V OH is governed by the VPUP, the voltage rail to which the pull-up resistors are connected. The maximum VPUP voltage is 3.6V.
  2. See I/O Electrical Characteristics.

Table 25. SMBus AC Electrical Characteristics

  1. Power must be applied and PWRGD_PWRDNb must be a 1 for the SMBus to be active.

R31DS0190EU0108 Rev.1.08 Page 28 May 11, 2026 RC191xx Datasheet 2. A host should not drive the clock at a frequency below the minimum f SMB. Further, the operating clock frequency should not be reduced below the minimum value of fSMB due to periodic clock extending by target devices as defined in Section 5.3.3 of System Management Bus (SMBus) Specification, Version 3.2, dated 12 Jan, 2022. This limit does not apply to the bus idle condition, and this limit is independent from the tLOW: SEXT and tLOW: MEXT limits. For example, if the SMBCLK is high for tHIGH,MAX, the clock must not be periodically stretched longer than 1/fSMB,MIN – tHIGH,MAX. This requirement does not pertain to a device that extends the SMBCLK low for data processing of a received byte, data buffering and so forth for longer than 100 µs in a non-periodic way. 3. A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the VIH,MIN of the SMBCLK signal) to bridge the undefined region of the falling edge of SMBCLK. 4. Target devices may have caused other target devices to hold SDA low. This is the maximum time that a device can hold SMBDAT low after the host raises SMBCLK after the last bit of a transaction. A target device may detect how long SDA is held low and release SDA after the time out period. 5. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of tTIMEOUT,MIN. After the host in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than tTIMEOUT,MAX. Typical device examples include the host controller, and embedded controller, and most devices that can host the SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or a stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds the SMBCLK low for tTIMEOUT,MAX or longer. 6. The device has the option of detecting a timeout if the SMBDATA pin is also low for this time. 7. t HIGH,MAX provides a simple guaranteed method for hosts to detect bus idle conditions. A host can assume that the bus is free if it detects that the clock and data signals have been high for greater than tHIGH,MAX. 8. tLOW:MEXT is the cumulative time a host device is allowed to extend its clock cycles within each byte of a message as defined from START-to- ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a target device or another host will also extend the clock causing the combined clock low time to be greater than tLOW:MEXT on a given byte. This parameter is measured with a full-speed target device as the sole target of the host. 9. The rise and fall time measurement limits are defined as follows: Rise Time Limits: (VIL:MAX - 0.15 V) to (VIH:MIN + 0.15 V) Fall Time Limits: (VIH:MIN + 0.15 V) to (VIL:MAX - 0.15 V) 10. Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

Figure 11. Test Load for PCIe Phase Jitter Measurements Table 28. Parameters for PCIe Phase Jitter Measurements

  1. PCIe Gen6 specifies L = 0cm for 32 and 64 GT/s. L = 25.4cm is more conservative.

R31DS0190EU0108 Rev.1.08 Page 31 May 11, 2026 RC191xx Datasheet 4. General SMBus Serial Interface Information This section applies to all device except the RC19102 which does not have an SMBus interface.

4.1 How to Write

▪ Controller (host) sends a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) sends the byte count = X ▪ Renesas clock will acknowledge ▪ Controller (host) starts sending Byte N through Byte N+X-1 ▪ Renesas clock will acknowledge each byte one at a time ▪ Controller (host) sends a stop bit

4.2 How to Read

▪ Controller (host) will send a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) will send a separate start bit ▪ Controller (host) sends the read address ▪ Renesas clock will acknowledge ▪ Renesas clock will send the data byte count = X ▪ Renesas clock sends Byte N+X-1 ▪ Renesas clock sends Byte L through Byte X (if X(H) was written to Byte 7) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit Index Block Write Operation Controller (Host) Renesas (Target/Receiver) T starT bit Target Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK P stoP bit Index Block Read Operation Controller (Host) Renesas (Target/Receiver) T starT bit Target Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Target Address RD ReaD ACK Data Byte Count = X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not acknowledge P stoP bit

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4.3 SMBus Bit Types

4.4 Write Lock Functionality

4.5 SMBus Address Decode

Bit Description Definition RO Read-only RW Read-write RW1C Read/Write ‘1’ to clear RESERVED Undefined do not write WRITE_LOCK WRITE_LOCK RW1C SMBus Write Protect 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes Address Selection Binary Value Hex Value SADR_tri1 SADR_tri0 7 6 5 4 3 2 1 Rd/Wrt 0 1 1 0 1 0 1 1 0 D6 M 1 1 0 1 1 0 0 0 D8 1 1 1 0 1 1 0 1 0 DA M 0 1 1 0 0 0 1 1 0 C6 M 1 1 0 0 1 0 0 0 C8 1 1 1 0 0 1 0 1 0 CA 0 1 0 1 0 0 1 1 0 A6 M 1 0 1 0 1 0 0 0 A8 1 1 0 1 0 1 0 1 0 AA

4.6 SMBus Registers

4.6.1 OUTPUT_ENABLE

Table 29. Register Index

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4.6.2 OEB_PIN_READBACK

OEb Pin Readback Register.

4.6.3 LOS_CONFIG

Loss of Signal and Async Mode Configuration Register. 1 clk1_en RW 0x1 CLK1 enable. 0 = Output is disabled (low/low) 1 = Output is enabled 0 clk0_en RW 0x1 CLK0 enable. 0 = Output is disabled (low/low) 1 = Output is enabled OEB_PIN_READBACK Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 rb_oeb7 RO 0x1 State of OEb7 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 6 rb_oeb6 RO 0x1 State of OEb6 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 5 rb_oeb5 RO 0x1 State of OEb5 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 4 rb_oeb4 RO 0x1 State of OEb4 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 3 rb_oeb3 RO 0x1 State of OEb3 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 2 rb_oeb2 RO 0x1 State of OEb2 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 1 rb_oeb1 RO 0x1 State of OEb1 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high 0 rb_oeb0 RO 0x1 State of OEb0 pin. The default pin state is 1 if not driven to a 0. 0 = Pin low 1 = Pin high LOS_CONFIG Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 reserved RW 0x0 Reserved 6 losb_rw1c_en RW 0x1 LOS sticky bit enable. Enables the LOS sticky bit (B0x27[1]). This bit must be set to 1 if B0x4[2] is set to 0. 0 = Disable 1 = Enable 5 reserved RW 0x0 Reserved OUTPUT_ENABLE Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.6.4 VENDOR_REVISION_ID

Vendor ID, Revision ID Register.

4.6.5 DEVICE_ID

Device ID Register.

4.6.6 BYTE_COUNT

Number of Bytes Returned on an SMBus Block Read. 4 losb_acp_en RW 0x1 Automatic clock parking enable. Enables Automatic Clock Parking of outputs to a low/low state when LOS condition occurs. 0 = Disable 1 = Enable 3 reserved RW 0x0 Reserved 2 losb_config RW 0x1 Configure LOSb pin operating mode. Determines if the LOSb pin is a real-time or sticky. If sticky, the LOSb pin is driven by the LOSb RW1C sticky bit. 1 = LOSb real-time 0 = LOSb from RW1C sticky bit 1:0 reserved RW 0x0 Reserved VENDOR_REVISION_ID Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 rid RO 0x0 REVISION ID. Silicon Revision. 0x0 = A revision 3:0 vid RO 0x1 VENDOR ID. Vendor ID. 0x1 = Renesas DEVICE_ID Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:0 device_id RO 0x18 RC19108 device ID listed as default. 0x18 = RC19108 0x14 = RC19104 BYTE_COUNT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:5 reserved RW 0x0 Reserved 4:0 byte_count RW 0x7 Writing to this register configures how many bytes will be returned on an SMBus block read. LOS_CONFIG Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.6.7 SLEW_AMP_SELECT

Multifunction Pin Configuration Register.

4.6.8 INPUT_PULLUP_PULLDOWN_4

Internal Pull-up / Pull-down Configuration Register. SLEW_AMP_SELECT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 slew_amp_sel RW 0x0 Multi-function pin selection. The pin is defined as either Slew Rate Select or Amplitude Select. If Amplitude Select is chosen, refer to registers 0x10 and 0x11. 0 = Pin is Slew Rate Select pin (RC191xxA) 1 = Pin is Amplitude Select pin (RC191xxA001) 6:0 reserved RW 0x0 Reserved INPUT_PULLUP_PULLDOWN_4 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 reserved RW 0x8 Reserved 3 sdata_pullup RW 0x0 Enable/disable internal pull-up. The default pin state is high when the internal pull-up is enabled. If the SMBus is not used, this bit may be set to hold the SDATA pin in an inactive state. It should not be set if the SMBus is used in the system. 0 = Disable internal pull-up 1 = Enable internal pull-up 2 reserved RW 0x0 Reserved 1 sclk_pullup RW 0x0 Enable/disable internal pull-up. The default pin state is high when the internal pull-up is enabled. If the SMBus is not used, this bit may be set to hold the SDATA pin in an inactive state. It should not be set if the SMBus is used in the system. 0 = Disable internal pull-up 1 = Enable internal pull-up 0 reserved RW 0x0 Reserved

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4.6.9 AMP_CTRL_ALT

Alternate Amplitude Selection Register.

4.6.10 AMP_CTRL_DEF

Default Amplitude Selection Register. AMP_CTRL_ALT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 amp_cntrl_alt RW 0xB Alternate amplitude control. When the multifunction pin is configured as Amplitude Select, this field defines the single-ended output amplitude when the pin = 1. When the multifunction pin is configured as Slew Rate Selection, this field has no impact. 0x0 = 625mV 0x1 = 650mV 0x2 = 675mV 0x3 = 700mV 0x4 = 725mV 0x5 = 750mV 0x6 = 775mV 0x7 = 800mV 0x8 = 825mV 0x9 = 850mV amp_cntrl_alt (continued) 0xA = 875mV 0xB = 900mV 0xC = 925mV 0xD = 950mV 0xE = 975mV 0xF = 1000mV 3:0 reserved RW 0x0 Reserved AMP_CTRL_DEF Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:4 amp_cntrl_def RW 0x7 Default amplitude control. When the multifunction pin is configured as Slewrate Select, or when the pin is configured as Amplitude Select and the pin = 0, this field defines the single-ended output amplitude. 0x0 = 625mV 0x1 = 650mV 0x2 = 675mV 0x3 = 700mV 0x4 = 725mV 0x5 = 750mV 0x6 = 775mV 0x7 = 800mV 0x8 = 825mV 0x9 = 850mV amp_cntrl_def (continued) 0xA = 875mV 0xB = 900mV 0xC = 925mV 0xD = 950mV 0xE = 975mV 0xF = 1000mV 3:0 reserved RW 0x0 Reserved

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4.6.11 PD_RESTORE_LOSb_CONFIG

Configuration and Status Register.

4.6.12 OUTPUT_IMPEDANCE_7_0

Output Impedance Select Register 0. PD_RESTORE_LOSb_CONFIG Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:5 reserved RW 0x0 Reserved 4 ck_acquire_rb RO 0x0 Clock acquired readback. This bit indicates if a clock was ever detected (LOSb de-asserted) for the current power cycle. 0 = Clock never acquired 1 = Clock acquired at least once before 3 pd_restoreb RW 0x1 Save configuration in power-down. This bit determines the behavior of the device when the PWRGD_PWRDNb pin is asserted low. This bit is automatically returned to 1 after PWRGD_PWRDNb is toggled 1-0-1 with the bit set to 0. 0 = Config Cleared 1 = Config Saved 2 sdata_time_out_en RW 0x1 Enable SMB time out monitoring SDATA. This bit enables a timeout for the SMBus data path. This timeout monitor is in addition to the mandatory SCLK timeout monitor. These monitors release a hung SMBus. 0 = Disable SDATA time out 1 = Enable SDATA time out 1 reserved RO 0x0 Reserved 0 losb_rb RO 0x0 Real-time read back of input clock detect. This bit provides a real-time status of the clock input. The default value assumes no input clock present. 0 = LOS event detected (no CLKIN detected) 1 = No LOS event detected (CLKIN detected) OUTPUT_IMPEDANCE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 clk7_impedance0 RW 0x0 CLK7 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[7] are set to 0. ZOUTSEL_tri = M: this bit is set to 0 and B0x15[7] is set to 1. ZOUTSEL_tri= 1: this bit is set to 1 and B0x15[7] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 6 clk6_impedance0 RW 0x0 CLK6 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[6] are set to 0. ZOUTSEL_tri = M: this bit is set to 0, ignored, and B0x15[6] is set to 1. ZOUTSEL_tri = 1: this bit is set to 1 and B0x15[6] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 5 clk5_impedance0 RW 0x0 CLK5 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[5] are set to 0. ZOUTSEL_tri = M: this bit is set to 0, ignored, and B0x15[5] is set to 1. ZOUTSEL_tri= 1: this bit is set to 1 and B0x15[5] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 4 clk4_impedance0 RW 0x0 CLK4 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[4] are set to 0. ZOUTSEL_tri = M: this bit is set to 0, ignored, and B0x15[4] is set to 1. ZOUTSEL_tri= 1: this bit is set to 1 and B0x15[4] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended

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4.6.13 OUTPUT_REC_SEL_7_0

Output Impedance Select Register 1. 3 clk3_impedance0 RW 0x0 CLK3 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[3] are set to 0. ZOUTSEL_tri = M: this bit is set to 0, ignored, and B0x15[3] is set to 1. ZOUTSEL_tri= 1: this bit is set to 1 and B0x15[3] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 2 clk2_impedance0 RW 0x0 CLK2 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[2] are set to 0. ZOUTSEL_tri = M: this bit is set to 0, ignored, and B0x15[2] is set to 1. ZOUTSEL_tri= 1: this bit is set to 1 and B0x15[2] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 1 clk1_impedance0 RW 0x0 CLK1 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[1] are set to 0. ZOUTSEL_tri = M: this bit is set to 0, ignored, and B0x15[1] is set to 1. ZOUTSEL_tri= 1: this bit is set to 1 and B0x15[1] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended 0 clk0_impedance0 RW 0x0 CLK0 impedance select bit 0. ZOUTSEL_tri = 0: this bit and B0x15[0] are set to 0. ZOUTSEL_tri = M: this bit is set to 0, ignored, and B0x15[0] is set to 1. ZOUTSEL_tri= 1: this bit is set to 1 and B0x15[0] is set to 0. 0 = 85 ohm differential, 42.5 ohm single-ended 1 = 100 ohm differential, 50 ohm single-ended OUTPUT_REC_SEL_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 clk7_impedance1 RW 0x1 CLK7 impedance select bit 1. ZOUTSEL_tri = 0 or 1: this bit is set to 0 at power up and the appropriate value is set in B0x14[7]. ZOUTSEL_tri = M: this bit is set to 1 at power up, B0x14[7] is set to 0 and ignored. 0 = See B0x14[7] 1 = 34 ohm differential, 17 ohm single-ended 6 clk6_impedance1 RW 0x1 CLK6 impedance select bit 1. ZOUTSEL_tri = 0 or 1: this bit is set to 0 at power up and the appropriate value is set in B0x14[6]. ZOUTSEL_tri = M: this bit is set to 1 at power up, B0x14[6] is set to 0 and ignored. 0 = See B0x14[6] 1 = 34 ohm differential, 17 ohm single-ended 5 clk5_impedance1 RW 0x1 CLK5 impedance select bit 1. ZOUTSEL_tri = 0 or 1: this bit is set to 0 at power up and the appropriate value is set in B0x14[5]. ZOUTSEL_tri = M: this bit is set to 1 at power up, B0x14[5] is set to 0 and ignored. 0 = See B0x14[5] 1 = 34 ohm differential, 17 ohm single-ended 4 clk4_impedance1 RW 0x1 CLK4 impedance select bit 1. ZOUTSEL_tri = 0 or 1: this bit is set to 0 at power up and the appropriate value is set in B0x14[4]. ZOUTSEL_tri = M: this bit is set to 1 at power up, B0x14[4] is set to 0 and ignored. 0 = See B0x14[4] 1 = 34 ohm differential, 17 ohm single-ended OUTPUT_IMPEDANCE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.6.14 OUTPUT_SLEW_RATE_7_0

Output Slewrate Select Register. 3 clk3_impedance1 RW 0x1 CLK3 impedance select bit 1. ZOUTSEL_tri = 0 or 1: this bit is set to 0 at power up and the appropriate value is set in B0x14[3]. ZOUTSEL_tri = M: this bit is set to 1 at power up, B0x14[3] is set to 0 and ignored. 0 = See B0x14[3] 1 = 34 ohm differential, 17 ohm single-ended 2 clk2_impedance1 RW 0x1 CLK2 impedance select bit 1. ZOUTSEL_tri = 0 or 1: this bit is set to 0 at power up and the appropriate value is set in B0x14[2]. ZOUTSEL_tri = M: this bit is set to 1 at power up, B0x14[2] is set to 0 and ignored. 0 = See B0x14[2] 1 = 34 ohm differential, 17 ohm single-ended 1 clk1_impedance1 RW 0x1 CLK1 impedance select bit 1. ZOUTSEL_tri = 0 or 1: this bit is set to 0 at power up and the appropriate value is set in B0x14[1]. ZOUTSEL_tri = M: this bit is set to 1 at power up, B0x14[1] is set to 0 and ignored. 0 = See B0x14[1] 1 = 34 ohm differential, 17 ohm single-ended 0 clk0_impedance1 RW 0x1 CLK0 impedance select bit 1. ZOUTSEL_tri = 0 or 1: This bit is set to 0 at power up and the appropriate value is set in B0x14[0]. ZOUTSEL_tri = M: This bit is set to 1 at power up, B0x14[0] is set to 0 and ignored. 0 = See B0x14[0] 1 = 34 ohm differential, 17 ohm single-ended OUTPUT_SLEW_RATE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7 clk7_slewrate RW 0x1 CLK7 slew rate select. If B0xA[7] = 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7] = 1 at startup, default = 1 0 = Slow slew rate 1 = Fast slew rate 6 clk6_slewrate RW 0x1 CLK6 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 5 clk5_slewrate RW 0x1 CLK5 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 4 clk4_slewrate RW 0x1 CLK4 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 3 clk3_slewrate RW 0x1 CLK3 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate OUTPUT_REC_SEL_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.6.15 LOW-LOW_DETECT

CLKIN Low-Low Detect Enable Register.

4.6.16 RECEIVER_CONTROL

CLKIN Configuration Register. 2 clk2_slewrate RW 0x1 CLK2 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 1 clk1_slewrate RW 0x1 CLK1 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate 0 clk0_slewrate RW 0x1 CLK0 slew rate select. If B0xA[7]= 0 at power up, the SLEWRATE_SEL pin sets the default. After power up, the value can be changed via SMBus. If B0xA[7]= 1 at startup, default=1 0 = Slow slew rate 1 = Fast slew rate LOW-LOW_DETECT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:3 reserved RW 0x12 Reserved 2 low_low_det_enable RW 0x1 Enable low-low detect circuit on CLKIN. Allows the device to detect a low-low condition on CLKIN and turn off the receiver. (Low-low is not a valid differential state). 0 = Disable 1 = Enable 1:0 reserved RW 0x0 Reserved RECEIVER_CONTROL Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:2 reserved RW 0x0 Reserved 1 ac_in RW 0x0 AC-couple CLKIN. When AC-coupling CLKIN, set this bit to enable internal bias circuitry on the CLKIN. This eliminates the need for external bias components on the CLKIN side of the AC-coupling capacitor. 0 = Disable internal bias (DC-coupled) 1 = Enable internal bias (AC-coupled) 0 rx_term RW 0x0 Enable internal termination for CLKIN. Applications requiring receiver terminations may set this bit to enable termination resistors to ground on both the CLKIN and CLKINb pins. PCIe applications generally require Rx_TERM to be 0. 0 = Disable internal termination (PCIe) 1 = Enable internal termination OUTPUT_SLEW_RATE_7_0 Bit Field Descriptions Bit Field Field Name Field Type Default Value Description

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4.6.17 WRITE_LOCK

Non-Clearable Write Lock Register.

4.6.18 WRITE_LOCK_LOS_EVT

Clearable Write Lock and LOS Event Sticky Register. WRITE_LOCK Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:1 reserved RW 0x0 Reserved 0 write_lock RW 0x0 Non-clearable SMBus write lock bit. When written to one, the SMBus registers cannot be written. They may be read. This bit can only be cleared by cycling power. 0 = SMBus writes are not prohibited by WRITE_LOCK 1 = SMBus locked for writing WRITE_LOCK_LOS_EVT Bit Field Descriptions Bit Field Field Name Field Type Default Value Description 7:2 reserved RW1C 0x0 Reserved 1 los_evt_rw1c RW1C 0x0 LOS event sticky bit. A 1 indicates that an LOS event occurred. The bit can be cleared by writing a 1. 0 = No LOS event detected 1 = LOS event detected. 0 write_lock_rw1c RW1C 0x0 Clearable SMBus write lock bit. When written to one, the SMBus control registers cannot be written. They may be read. This bit may be cleared by writing a 1 to it. 0 = SMBus writes are not prohibited by WRITE_LOCK_RW1C 1 = SMBus locked for writing

5.1 Inputs, Outputs, and Output Enable Control

from floating input clock condition.

5.1.1 Recommendations for Unused Inputs and Outputs

5.1.1.1 Unused Single-ended Control Inputs

change the pin state or are desired for design robustness, 10kohm is the recommended value.

5.1.1.2 Unused Differential CLK Outputs

outputs. While not required (but highly recommended), the best design practice is to disable unused CLK outputs. This is easily accomplished with the dedicated OEb pin for each output.

5.1.1.3 Unused SMBus Clock and Data Pins

are 3.3V tolerant and may be used with a 3.3V pull-up voltage.

5.1.2 Differential CLKIN Configurations

This feature is enabled by the AC_IN bit. ▪ Internal pull-down resistors (Rp) to terminate the clock input at the receiver. This feature is enabled by the Rx_TERM bit. and transmission line length vary from the 100MHz PCIe standard. displayed in Figure 12 to Figure 15. Table 30. CLKIN Configuration Bits LVDS Input Levels 1 0 Eliminates need for external bias circuit. External AC-Coupling 1 0 Eliminates need for external bias circuit.

5.1.3 Differential CLK Output Configurations

5.1.3.1 Direct-Coupled HCSL Loads

HCSL-level inputs with no external components. They support both 85 ohm and 100 ohm differential impedances. half of the source-terminated values.

5.1.3.2 AC-Coupled non-HCSL Loads

terminating the RC191xx CLK outputs to other logic families such as LVDS, LVPECL, or CML, see AN-891. Figure 16 to Figure 19 show the various CLK output configurations. Figure 16. Direct-Coupled Source-Terminated HCSL (ZOUT_SEL_tri = 0 or 1) Figure 12. HCSL Input Levels (PCIe Standard) Figure 13. LVDS Input Levels Figure 14. External AC-Coupling Figure 15. Receiver Termination

Figure 17. Direct-Coupled Double-Terminated HCSL Figure 18. Receiver-Terminated Load (ZOUT_SEL_tri = M) Figure 19. AC-Coupled Non-PCIe Load

5.2 Power Down Tolerant Pins

Power Down Tolerant (PDT) pins can be driven even though VDD is not present (the device is not powered). descriptions to identify which pins are PDT. PDT pins are also 3.3V tolerant.

5.3 Flexible Startup Sequencing

CLKIN running before VDD is applied, and can have VDD applied and sit for extended periods with no input clock. Table 31. Flexible Startup Sequences

5.4 Loss of Signal and Automatic Clock Parking

The RC191xx devices have a Loss of Signal (LOS) circuit to detect the presence or absence of an input clock. LOSb de-assertion timing for the RC191xx clock buffers. LOSb defaults to low at power up. Figure 20. LOSb De-assert Timing RC191xx Devices Figure 21. LOSb Assert Timing

5.5 Output Enable Control

mechanisms indicate “enabled.” The following sections describe the mechanisms.

5.5.1 SMBus Output Enable Bits

This section does not apply to the RC19102 because it does not have an SMBus. and disable states are glitch-free in both directions.

5.5.2 Output Enable (OEb) Pins

R31DS0190EU0108 Rev.1.08 Page 47 May 11, 2026 RC191xx Datasheet the OEb pin is low the controlled output is enabled. If the OEb pin is high, the controlled output is disabled to a low/low state. All OEb pins enable and disable the controlled outputs in a glitch-free, synchronous manner. Note: The glitch-free synchronization logic requires the CLKIN be running to enable or disable the outputs with this mechanism.

5.6 PCB Layout Recommendations

Proper layout is critical to achieving the full functionality and efficiency of the device. For information on how to support optimal electrical performance, effective thermal management, and overall system reliability, see the PCIe Buffer-Mux Layout Recommendations Application Note. 6. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see the package links in Ordering Information). The package information is the most current data available and is subject to change without revision of this document. 7. Marking Diagrams RC19108A ▪ Line 1 is the part number. ▪ Line 2:

  • “$” indicates the mark code.
  • “YWW” indicates the last digit of the year and work week the part was assembled.
  • “***” indicates the assembly lot number. RC19108A001 ▪ Lines 1 and 2 comprise the part number. ▪ Line 3:
  • “$” indicates the mark code.
  • “YWW” indicates the last digit of the year and work week the part was assembled.
  • “***” indicates the assembly lot number. RC19104A ▪ Line 1 is the part number. ▪ Line 2:
  • “$” indicates the mark code.
  • “YWW” indicates the last digit of the year and work week the part was assembled.
  • “***” indicates the assembly lot number.

R31DS0190EU0108 Rev.1.08 Page 48 May 11, 2026 RC191xx Datasheet 8. Ordering Information RC19104A001 ▪ Lines 1 and 2 comprise the part number. ▪ Line 3:

  • “$” indicates the mark code.
  • “YWW” indicates the last digit of the year and work week the part was assembled.
  • “*” indicates the assembly lot number. RC19102A ▪ Lines 1 and 2 comprise the part number (RC excluded). ▪ Line 2: “*” indicates the assembly lot number. ▪ Line 3:
  • “$” indicates the mark code.
  • “YWW” indicates the last digit of the year and work week the part was assembled. Part Number Carrier Type Pin Function Option Number of Outputs Package Temp. Range RC19108AGND#BB0 Tray Slewrate Selection 8 5 × 5 mm, 0.4mm pitch, 40-VFQFPN -40 to +105°C RC19108AGND#KB0 Tape and Reel (EIA-481-D) RC19108A001GND#BB0 Tray Amplitude SelectionRC19108A001GND#KB0 Tape and Reel (EIA-481-D) RC19104AGNL#BB0 Tray Slewrate Selection 4 4 × 4 mm, 0.4mm pitch, 28-VFQFPN -40 to +105°C RC19104AGNL#KB0 Tape and Reel (EIA-481-D) RC19104A001GNL#BB0 Tray Amplitude SelectionRC19104A001GNL#KB0 Tape and Reel (EIA-481-D) RC19102AGNT#BD0 Tray N/A 2 3 × 3 mm, 0.4mm pitch, 20-VFQFPN -40 to +105°C RC19102AGNT#KD0 Tape and Reel (EIA-481-D)

R31DS0190EU0108 Rev.1.08 Page 49 May 11, 2026 RC191xx Datasheet 9. Revision History Revision Date Description

1.08 May 11, 2026 ▪ Added a caution statement to Absolute Maximum Ratings

1.07 Nov 10, 2025

▪ Deleted non-applicable parameter description information from Table 9 and Table 10. Also changed all references to PCI Express Base Specification 6.0 to PCI Express Base Specification 7.0 ▪ Changed the maximum value for “V DDCLK Operating Current per Output Pair, 85Ω impedance“; Fast slew rate, double-terminated load at 100MHz to 13.5 in Table 23

1.06 Sep 24, 2025 Updated the binary values of [6:5] in SMBus Address Decode

1.04 Jun 28, 2025 Added PCB Layout Recommendations

1.03 Mar 27, 2025

▪ Completed a minor re-arrangement of Features section ▪ Corrected footnote 3 in Table 10 ▪ Update reference in footnote 2 of SMBus AC Electrical Characteristics from Version 3.1, dated 19 Mar, 2018 to Version 3.2, dated 12 Jan, 2022 ▪ Updated t HD:DAT to 0ns per SMBus Version 3.2 ▪ Added decimal values to Register Index ▪ Changed all references 33ohm differential output impedance to 34ohm for consistency ▪ Simplified Power Supply Current

1.02 Jan 31, 2025 ▪ Updated the binary values of [3:1] in SMBus Address Decode

▪ Changed master/slave to host/target where appropriate 1.01 Nov 6, 2024 ▪ Added PCIe Gen7 information to Table 9 and Table 10. Also updated front page text accordingly ▪ Corrected Table 11

1.00 Jul 31, 2024 Initial release

(PCB Top View, NSMD Design) 0.35 0.35 5.00 ±0.10 5.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW0.40 ±0.10 3.50 ±0.10 3.50 ±0.10 0.40 SIDE VIEW RECOMMENDED LAND PATTERN 0.20 (0.35) 0.200.40Package Outline 3.50 3.50 4.20 5.30 5.30 © Renesas Electronics Corporation

2.60 4.303.20 4.30 2.60 (PCB Top View, NSMD Design) 0.35 Seating Plane Package Outline 4.00 ±0.10 4.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW SIDE VIEW0.08C 0.200.40 RECOMMENDED LAND PATTERN 0.90 ±0.10 C(0.20)0.05 Max 781415 2122 28 0.35 (0.30) 0.40 ±0.10 2.60 ±0.10 2.60 ±0.10 0.40 0.20 © Renesas Electronics Corporation

(PCB Top View, NSMD Design) Seating Plane 3.00 ±0.10 3.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW SIDE VIEW0.08C RECOMMENDED LAND PATTERN 0.90 ±0.10 C(0.20)0.05 Max 561011 1516 20min 0.20 0.40 ±0.10 1.65 ±0.10 1.65 ±0.10 0.40 0.20 Package Outline 1.65 3.302.20 1.65 1.65 0.200.40 A. PIN1 ID OPTION DETAILS A. Pin1 IDOption A. Pin1 IDOption © Renesas Electronics Corporation

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