RC19013A100GNGBB0

RC190XX RENESAS | Alldatasheet

Document overview

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• PDF pages: 109

Technical content

Datasheet sections

• 1.1 Signal Types
• 1.2 RC19024A Pin Assignments
• 1.2.1 RC19024A Pin Descriptions
• 1.3 RC19020A Pin Assignments
• 1.3.1 RC19020A Pin Descriptions
• 1.4 RC19020A072 Pin Configuration
• 1.4.1 RC19020A072 Pin Descriptions
• 1.5 RC19016A Pin Assignments
• 1.5.1 RC19016A Pin Descriptions
• 1.6 RC19013A Pin Assignments
• 1.6.1 RC19013A Pin Descriptions
• 1.7 RC19008A Pin Assignments
• 1.7.1 RC19008A Pin Descriptions
• 1.8 RC19004A Pin Assignments
• 1.8.1 RC19004A Pin Descriptions
• 2.1 Absolute Maximum Ratings
• 2.2 ESD Ratings
• 2.3 Recommended Operation Conditions
• 2.4 Thermal Information
• 2.5 Electrical Characteristics
• 2.5.1 Phase Jitter
• 2.5.2 Output Frequencies, Startup Time, and LOS Timing
• 2.5.3 RC1902xA CLK AC/DC Output Characteristics
• 2.5.4 RC1901xA/RC1900xA CLK AC/DC Output Characteristics
• 2.5.5 Output-to-Output and Input-to-Output Skew
• 2.5.6 I/O Signals
• 2.5.7 Power Supply Current
• 2.5.8 CLKIN AC/DC Characteristics
• 2.5.9 SMBus Electrical Characteristics
• 2.5.10 Side-Band Interface
• 4.1 How to Write
• 4.2 How to Read
• 4.3 SMBus Bit Types
• 4.4 Write Lock Functionality
• 4.5 SMBus Address Decode
• 4.6 RC19024A SMBus Registers
• 4.7 RC19020A SMBus Registers
• 4.8 RC19020A072 SMBus Registers
• 4.9 RC1901xA/RC1900xA SMBus Registers
• 5.1 Inputs, Outputs, and Output Enable Control
• 5.1.1 Recommendations for Unused Inputs and Outputs

Features

▪ PCIe Gen5 additive phase jitter: 6fs RMS ▪ PCIe Gen6 additive phase jitter: 4fs RMS ▪ DB2000Q additive phase jitter: 10fs RMS ▪ 12kHz to 20MHz additive phase jitter: 30fs RMS at 156.25MHz ▪ Power Down Tolerant (PDT) inputs ▪ Flexible Startup Sequencing (FSS) ▪ Automatic Clock Parking (ACP) upon loss of CLKIN ▪ Selectable output slew rate via pin or SMBus ▪ 4-wire Side-Band Interface supports high-speed serial output enable and device daisy-chaining ▪ 9 selectable SMBus addresses ▪ SMBus write protection features ▪ Spread-spectrum tolerant ▪ 85Ω or 100Ω (A100 suffix) output impedance ▪ CLKIN accepts HCSL or LVDS signal levels ▪ -40 to +105°C, 3.3V ±10% operation Figure 1. RC190xx Block Diagram

1. RC1901xA/0xA only. Other devices use SMBus.
2. On some devices the SBI is muxed with OEb pins. See pinouts

for e xa ct configuratio ns. All devices ha ve ded ica ted SB I_ENQ pin.

R31DS0016EU0110 Rev.1.10 Page 3 Dec 1, 2022 RC190xx Datasheet

R31DS0016EU0110 Rev.1.10 Page 4 Dec 1, 2022 RC190xx Datasheet 1. Pin Information

1.1 Signal Types

Note that some pins have both internal pull-up and pull-down resistors which bias the pins to VDD/2. Other pins are multi-mode and have an internal pull-up or internal pull-down depending on the mode. Term Description I Input O Input OD Open Drain Output I/O Bi-Directional PD Pull-down PU Pull-up Z Tristate D Driven X Don’t care SE Single ended DIF Differential PWR 3.3 V power GND Ground PDT Power Down Tolerant: These signals must tolerate being driven when the device is powered down.

1.2 RC19024A Pin Assignments

Figure 2. RC19024A 100-VFQFPN – Top View

1.2.1 RC19024A Pin Descriptions

Table 1. RC19024A Pin Descriptions register. The function is this pin is controlled by the SBEN or SBI_ENQ pin. For more information, see Side-Band Interface (SBI). 0 = enable output, 1 = disable output. Clocks data into the SBI on the rising edge. A2 CLK23B O, DIF Complementary clock output. A3 CLK23 O, DIF True clock output.

A4 CLKINb I, DIF, PDT Complementary clock input. A5 CLKIN I, DIF, PDT True clock input. desired state. It cannot dynamically change. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins. A9 SCLK I, SE, PDT Clock pin of SMBus interface. A10 SDAT I/O, OD, PDT Data pin for SMBus interface. A11 CLK0b O, DIF Complementary clock output. A12 CLK0 O, DIF True clock output. A13 CLK1b O, DIF Complementary clock output. A14 CLK1 O, DIF True clock output. A15 CLK2b O, DIF Complementary clock output. A16 CLK2 O, DIF True clock output. A17 CLK3b O, DIF Complementary clock output. A18 CLK3 O, DIF True clock output. A19 CLK4b O, DIF Complementary clock output. A20 CLK4 O, DIF True clock output. A21 CLK5b O, DIF Complementary clock output. A22 CLK5 O, DIF True clock output. A23 CLK6b O, DIF Complementary clock output. A24 CLK6 O, DIF True clock output. A25 CLK7b O, DIF Complementary clock output. A26 CLK7 O, DIF True clock output. A27 CLK8b O, DIF Complementary clock output. A28 CLK8 O, DIF True clock output. A29 CLK9b O, DIF Complementary clock output. A30 CLK9 O, DIF True clock output. A31 CLK10b O, DIF Complementary clock output. A32 CLK10 O, DIF True clock output. A33 CLK11b O, DIF Complementary clock output. A34 CLK11 O, DIF True clock output. Table 1. RC19024A Pin Descriptions (Cont.)

A35 CLK12b O, DIF Complementary clock output. A36 CLK12 O, DIF True clock output. A37 CLK13b O, DIF Complementary clock output. A38 CLK13 O, DIF True clock output. A39 CLK14b O, DIF Complementary clock output. A40 CLK14 O, DIF True clock output. A41 CLK15b O, DIF Complementary clock output. A42 CLK15 O, DIF True clock output. A43 CLK16b O, DIF Complementary clock output. A44 CLK16 O, DIF True clock output. A45 CLK17b O, DIF Complementary clock output. A46 CLK17 O, DIF True clock output. A47 CLK18b O, DIF Complementary clock output. A48 CLK18 O, DIF True clock output. A49 CLK19b O, DIF Complementary clock output. A50 CLK19 O, DIF True clock output. A51 CLK20b O, DIF Complementary clock output. A52 CLK20 O, DIF True clock output. A53 CLK21b O, DIF Complementary clock output. A54 CLK21 O, DIF True clock output. A55 CLK22b O, DIF Complementary clock output. A56 CLK22 O, DIF True clock output. pin. Refer to the Side-Band Interface (SBI) section for details. 0 = enable output, 1 = disable output. B3 VDDCLK PWR Clock Power supply. B4 VDDDIG PWR Digital Power supply. B8 VDDCLK PWR Clock Power supply.

B10 GND GND Connect to ground. 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. B15 VDDCLK PWR Clock Power supply. OEb_ASSIGNMENT[2:0] registers for details. 0 = enable output, 1 = disable output. 0 = enable output, 1 = disable output. B21 VDDCLK PWR Clock Power supply. 0 = enable output, 1 = disable output. B24 SBI_OUT O, SE Side-Band Interface data output. B27 VDDCLK PWR Clock Power supply. 0 = enable output, 1 = disable output. B33 VDDCLK PWR Clock Power supply.

this pin indicates a loss of signal on the input clock. B40 VDDCLK PWR Clock Power supply. B43 GND GND Connect to ground. N/A EPAD GND Connect epad to ground.

1.3 RC19020A Pin Assignments

Figure 3. RC19020A 80-GQFN – Top View 9QXL2001B NC pins (C2 and G11).

1.3.1 RC19020A Pin Descriptions

Table 2. RC19020A Pin Descriptions A1 CLK17 O, DIF True clock output. A2 CLKb16 O, DIF Complementary clock output. A3 CLK16 O, DIF True clock output. A4 CLKb15 O, DIF Complementary clock output. A5 CLK15 O, DIF True clock output. A6 CLKb14 O, DIF Complementary clock output.

A7 CLK14 O, DIF True clock output. A8 CLKb13 O, DIF Complementary clock output. A9 CLK13 O, DIF True clock output. A10 CLKb12 O, DIF Complementary clock output. A11 CLK12 O, DIF True clock output. A12 CLKb11 O, DIF Complementary clock output. B1 CLKb17 O, DIF Complementary clock output. B2 VDDCLK PWR Power supply for clock outputs. Decode table and the tri-level input thresholds in the electrical tables. B6 VDDCLK PWR Power supply for clock outputs. Decode table and the tri-level input thresholds in the electrical tables. Active low input for enabling output 12. 0 = enable output, 1 = disable output. B11 VDDCLK PWR Power supply for clock outputs. B12 CLK11 O, DIF True clock output. C1 CLK18 O, DIF True clock output. C2 SBI_OUT O, SE Side-Band Interface data output. Active low input for enabling output 11. 0 = enable output, 1 = disable output. C12 CLKb10 O, DIF Complementary clock output. D1 CLKb18 O, DIF Complementary clock output. D12 CLK10 O, DIF True clock output. E1 CLK19 O, DIF True clock output. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins. Table 2. RC19020A Pin Descriptions (Cont.)

more information, see Side-Band Interface (SBI). 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. Active low input for enabling output 9. 0 = enable output, 1 = disable output. F1 CLKb19 O, DIF Complementary clock output. F12 CLKb9 O, DIF Complementary clock output. indicates a loss of signal on the input clock. G12 CLK9 O, DIF True clock output. PDT Complementary clock input. H2 VDDR PWR Power supply for clock input (receiver). Active low input for enabling output 8. 0 = enable output, 1 = disable output. H12 CLKb8 O, DIF Complementary clock output. J1 CLK0 O, DIF True clock output. J12 CLK8 O, DIF True clock output. K1 CLKb0 O, DIF Complementary clock output. Active low input for enabling output 7. 0 = enable output, 1 = disable output. K12 CLKb7 O, DIF Complementary clock output. L1 CLK1 O, DIF True clock output. L2 VDDCLK PWR Power supply for clock outputs. OD, PDT Data pin for SMBus interface.

PDT Clock pin of SMBus interface. Active low input for enabling output 5or the data pin for the Side-Band Interface. information, see Side-Band Interface (SBI). 0 = Enable output, 1 = Disable output. 0 = Enable output, 1 = Disable output. Clocks data into the SBI shift register on the rising edge. L11 VDDCLK PWR Power supply for clock outputs. L12 CLK7 O, DIF True clock output. M1 CLKb1 O, DIF Complementary clock output. M2 CLK2 O, DIF True clock output. M3 CLKb2 O, DIF Complementary clock output. M4 CLK3 O, DIF True clock output. M5 CLKb3 O, DIF Complementary clock output. Input notifies device to sample latched inputs and start up on first high assertion. M7 CLK4 O, DIF True clock output. M8 CLKb4 O, DIF Complementary clock output. M9 CLK5 O, DIF True clock output. M10 CLKb5 O, DIF Complementary clock output. M11 CLK6 O, DIF True clock output. M12 CLKb6 O, DIF Complementary clock output. N/A EPAD GND Connect epad to ground.

1.4 RC19020A072 Pin Configuration

Figure 4. RC19020A072 72-VFQFPN – Top View placed on 9QXL2000 NC pins (5, 15 and 16).

1.4.1 RC19020A072 Pin Descriptions

Table 3. RC19020A072 Pin Descriptions 1 VDDCLK PWR Power supply for clock outputs. the board may remain to support non-IDT DB2000Q devices. board may remain to support non-IDT DB2000Q devices. 5 SBI_OUT O, SE Side-Band Interface data output.

• 7 27 17 06 96 86 76 66 56 46 36 26 16 05 95 85 75 65 5 V DDCLK 1 54 OEb11 GND 2 53 CLKb11 rcomp_NC 3 52 CLK11 vdd_NC 4 51 OEb10_SHFT_LDb SBI_OUT 5 50 CLKb10 PWRGD_PWRDNb 6 49 CLK10 GND 7 48 OEb9 VD D R 8 47 CLKb9 CLKIN 9 46 CLK9 CLKINb 10 45 V DDCLK SADR_tri0 11 44 GND SDATA 12 43 OEb8 SCLK 13 42 CLKb8 SADR_tri1 14 41 CLK8 SBI_ENQ 15 40 OEb7 LOSb 16 39 CLKb7 CLKb19 17 38 CLK7 CLK19 18 37 OEb6_SBI_CLK 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36CLK0 CLKb0 VDDCLK CLK1 CLKb1 CLK2 CLKb2 GND CLK3 CLKb3 CLK4 CLKb4 VDDCLK CLK5 CLKb5 OEb5_SBI_IN CLK6 CLKb6 RC19020A072 10 x 10 mm, x 0.5mm pitch Top View connect EPAD to GND Note: Polarity of CLK19 is reversed from CLK[18:0] per DB2000Q Specification Rev1.2

6 PWRGD_PWRDNb I, SE, PU,

Input notifies device to sample latched inputs and start up on first high assertion. 8 VDDR PWR Power supply for clock input (receiver).

9 CLKIN I, DIF,

10 CLKINb I, DIF,

PDT Complementary clock input.

11 SADR_tri0 I, SE, PD,

Decode table and refer to the tri-level input thresholds in the electrical tables.

12 SDATA I/O, SE,

OD, PDT Data pin for SMBus interface.

13 SCLK I, SE,

PDT Clock pin of SMBus interface.

14 SADR_tri1 I, SE, PD,

Decode table and refer to the tri-level input thresholds in the electrical tables.

15 SBI_ENQ I, SE, PD,

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

16 LOSb O, OD,

indicates a loss of signal on the input clock. 17 CLKb19 O, DIF Complementary clock output. 18 CLK19 O, DIF True clock output. 19 CLK0 O, DIF True clock output. 20 CLKb0 O, DIF Complementary clock output. 21 VDDCLK PWR Power supply for clock outputs. 22 CLK1 O, DIF True clock output. 23 CLKb1 O, DIF Complementary clock output. 24 CLK2 O, DIF True clock output. 25 CLKb2 O, DIF Complementary clock output. 27 CLK3 O, DIF True clock output. 28 CLKb3 O, DIF Complementary clock output. 29 CLK4 O, DIF True clock output. 30 CLKb4 O, DIF Complementary clock output. 31 VDDCLK PWR Power supply for clock outputs. Table 3. RC19020A072 Pin Descriptions (Cont.)

32 CLK5 O, DIF True clock output. 33 CLKb5 O, DIF Complementary clock output.

34 OEb5_SBI_IN I, SE, PU,

Active low input for enabling output 5 or the data pin for the Side-Band Interface. Side-Band Interface (SBI) section for details. 0 = enable output, 1 = disable output. 35 CLK6 O, DIF True clock output. 36 CLKb6 O, DIF Complementary clock output.

37 OEb6_SBI_CLK I, SE, PU,

Band Interface (SBI) section for details. 0 = enable output, 1 = disable output. Clocks data into the SBI shift register on the rising edge. 38 CLK7 O, DIF True clock output. 39 CLKb7 O, DIF Complementary clock output.

40 OEb7 I, SE, PU,

Active low input for enabling output 7. 0 = enable output, 1 = disable output. 41 CLK8 O, DIF True clock output. 42 CLKb8 O, DIF Complementary clock output.

43 OEb8 I, SE, PU,

Active low input for enabling output 8. 0 = enable output, 1 = disable output. 45 VDDCLK PWR Power supply for clock outputs. 46 CLK9 O, DIF True clock output. 47 CLKb9 O, DIF Complementary clock output.

48 OEb9 I, SE,

Active low input for enabling output 9. 0 = enable output, 1 = disable output. 49 CLK10 O, DIF True clock output. 50 CLKb10 O, DIF Complementary clock output.

51 OEb10_SHFT_LDb I, SE, PU,

to the Side-Band Interface (SBI) section for details. 0 = enable output, 1 = disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 52 CLK11 O, DIF True clock output.

53 CLKb11 O, DIF Complementary clock output.

54 OEb11 I, SE, PU,

Active low input for enabling output 11. 0 = enable output, 1 = disable output. 55 CLK12 O, DIF True clock output. 56 CLKb12 O, DIF Complementary clock output.

57 OEb12 I, SE, PU,

Active low input for enabling output 12. 0 = enable output, 1 = disable output. 58 VDDCLK PWR Power supply for clock outputs. 59 CLK13 O, DIF True clock output. 60 CLKb13 O, DIF Complementary clock output. 61 CLK14 O, DIF True clock output. 62 CLKb14 O, DIF Complementary clock output. 64 CLK15 O, DIF True clock output. 65 CLKb15 O, DIF Complementary clock output. 66 CLK16 O, DIF True clock output. 67 CLKb16 O, DIF Complementary clock output. 68 VDDCLK PWR Power supply for clock outputs. 69 CLK17 O, DIF True clock output. 70 CLKb17 O, DIF Complementary clock output. 71 CLK18 O, DIF True clock output. 72 CLKb18 O, DIF Complementary clock output. 73 EPAD GND Connect EPAD to Ground.

1.5 RC19016A Pin Assignments

Figure 5. RC19016A 64-VFQFPN – Top View

1.5.1 RC19016A Pin Descriptions

Table 4. RC19016A Pin Descriptions

1 LOSb O, OD,

indicates a loss of signal on the input clock.

2 SLEWRATE_SEL I, SE, PU,

Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate.

3 SADR_tri1 I, SE, PD,

Decode table and the tri-level input thresholds in the electrical tables.

4 SADR_tri0 I, SE, PD,

Decode table and the tri-level input thresholds in the electrical tables.

5 SDATA I/O, SE,

OD Data pin for SMBus interface.

• 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LOSb 1 48 OEb5_SBI_CLK SLEWRA TE_SEL 2 47 CLKb5 SA DR_tri1 3 46 CLK5 SA DR_tri0 4 45 OEb6 SD ATA 5 44 VD D C LK SCLK 6 43 CLKb6 V DDDIG 7 42 CLK6 CLKIN 8 41 CLKb7 CLKINb 9 40 CLK7 OE b15 10 39 OEb7 OE b14 11 38 CLKb8 V DDCLK 12 37 CLK8 CLK15 13 36 OEb8 CLKb15 14 35 CLKb9 CLK14 15 34 CLK9 CLKb14 16 33 VDDCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32SBI_ENQ PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 CLK12 CLKb12 OEb12 CLK11 CLKb11 OEb11 CLK10 CLKb10 OEb10 OEb9_SBI_IN RC19016 64-VFQFPN top view connect EPAD to ground

6 SCLK I, SE Clock pin of SMBus interface. 8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input.

10 OEb15 I, SE, PD,

Active low input for enabling output 15. 0 = Enable output, 1 = Disable output.

11 OEb14 I, SE, PD,

Active low input for enabling output 14. 0 = Enable output, 1 = Disable output. 12 VDDCLK PWR Clock power supply. 13 CLK15 O, DIF True clock output. 14 CLKb15 O, DIF Complementary clock output. 15 CLK14 O, DIF True clock output. 16 CLKb14 O, DIF Complementary clock output.

17 SBI_ENQ I, SE, PD,

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

18 PWRGD_PWRDNb I, SE, PU,

Input notifies device to sample latched inputs and start up on first high assertion. 19 VDDCLK PWR Clock power supply.

20 OEb13_SHFT_LDb I, SE, PD,

information, see Side-Band Interface (SBI). 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 21 CLK13 O, DIF True clock output. 22 CLKb13 O, DIF Complementary clock output. 23 CLK12 O, DIF True clock output. 24 CLKb12 O, DIF Complementary clock output.

25 OEb12 I, SE, PD,

Active low input for enabling output 12. 0 = Enable output, 1 = Disable output. 26 CLK11 O, DIF True clock output. 27 CLKb11 O, DIF Complementary clock output.

28 OEb11 I, SE, PD,

Active low input for enabling output 11. 0 = Enable output, 1 = Disable output. 29 CLK10 O, DIF True clock output. 30 CLKb10 O, DIF Complementary clock output. Table 4. RC19016A Pin Descriptions (Cont.)

31 OEb10 I, SE, PD,

Active low input for enabling output 10. 0 = Enable output, 1 = Disable output.

32 OEb9_SBI_IN I, SE, PD,

Active low input for enabling output 9 or the data pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. 33 VDDCLK PWR Clock Power supply. 34 CLK9 O, DIF True clock output. 35 CLKb9 O, DIF Complementary clock output.

36 OEb8 I, SE, PD,

Active low input for enabling output 8. 0 = Enable output, 1 = Disable output. 37 CLK8 O, DIF True clock output. 38 CLKb8 O, DIF Complementary clock output.

39 OEb7 I, SE, PD,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 40 CLK7 O, DIF True clock output. 41 CLKb7 O, DIF Complementary clock output. 42 CLK6 O, DIF True clock output. 43 CLKb6 O, DIF Complementary clock output. 44 VDDCLK PWR Clock Power supply.

45 OEb6 I, SE, PD,

Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 46 CLK5 O, DIF True clock output. 47 CLKb5 O, DIF Complementary clock output.

48 OEb5_SBI_CLK I, SE, PD,

0 = Enable output, 1 = Disable output. Clocks data into the SBI on the rising edge. 49 CLK4 O, DIF True clock output. 50 CLKb4 O, DIF Complementary clock output.

51 OEb4 I, SE, PD,

0 = Enable output, 1 = Disable output. 52 CLK3 O, DIF True clock output. 53 CLKb3 O, DIF Complementary clock output.

54 OEb3 I, SE, PD,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

55 OEb2_SBI_OUT I, SE, PD

Band Interface (SBI). Note: This pin is NOT PDT. 0 = Enable output, 1 = Disable output. SBI shift register data output. 56 CLK2 O, DIF True clock output. 57 CLKb2 O, DIF Complementary clock output. 58 VDDCLK PWR Clock Power supply. 59 CLK1 O, DIF True clock output. 60 CLKb1 O, DIF Complementary clock output.

61 OEb1 I, SE, PD,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 62 CLK0 O, DIF True clock output. 63 CLKb0 O, DIF Complementary clock output.

64 OEb0 I, SE, PD,

Active low input for enabling output 0. 0 = Enable output, 1 = Disable output.

1.6 RC19013A Pin Assignments

Figure 6. RC19013A 56-VFQFPN – Top View

1.6.1 RC19013A Pin Descriptions

Table 5. RC19013A Pin Descriptions a loss of signal on the input clock. Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate. Decode table and the tri-level input thresholds in the electrical tables. Decode table and the tri-level input thresholds in the electrical tables. OD Data pin for SMBus interface. 6 SCLK I, SE Clock pin of SMBus interface.

• 56 55 54 53 52 51 50 49 48 47 46 45 44 43 LOSb 1 42 OEb6_SBI_CLK SLEWRA TE_SEL 2 41 V DDCLK SADR_tri1 3 40 CLKb6 SADR_tri0 4 39 CLK6 SDATA 5 38 CLKb7 SCLK 6 37 CLK7 V DDDIG 7 36 OEb7 CLKIN 8 35 CLKb8 CLKINb 9 34 CLK8 OEb14 10 33 OEb8 VDDCLK 11 32 CLKb9 CLK14 12 31 CLK9 CLKb14 13 30 V DDCLK SBI_ENQ 14 29 OEb9_SBI_IN 15 16 17 18 19 20 21 22 23 24 25 26 27 28PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 CLK12 CLKb12 OEb12 CLK11 CLKb11 OEb11 CLK10 CLKb10 OEb10 RC19013 Connect EPAD to ground Top view

8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input.

10 OEb14 I, SE, PD,

Active low input for enabling output 14. 0 = Enable output, 1 = Disable output. 11 VDDCLK PWR Clock power supply. 12 CLK14 O, DIF True clock output. 13 CLKb14 O, DIF Complementary clock output.

14 SBI_ENQ I, SE, PD,

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

15 PWRGD_PWRDNb I, SE, PU,

Input notifies device to sample latched inputs and start up on first high assertion. 16 VDDCLK PWR Clock Power supply.

17 OEb13_SHFT_LDb I, SE, PD,

information, see Side-Band Interface (SBI). 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 18 CLK13 O, DIF True clock output. 19 CLKb13 O, DIF Complementary clock output. 20 CLK12 O, DIF True clock output. 21 CLKb12 O, DIF Complementary clock output.

22 OEb12 I, SE, PD,

Active low input for enabling output 12. 0 = Enable output, 1 = Disable output. 23 CLK11 O, DIF True clock output. 24 CLKb11 O, DIF Complementary clock output.

25 OEb11 I, SE, PD,

Active low input for enabling output 11. 0 = Enable output, 1 = Disable output. 26 CLK10 O, DIF True clock output. 27 CLKb10 O, DIF Complementary clock output.

28 OEb10 I, SE, PD,

Active low input for enabling output 10. 0 = Enable output, 1 = Disable output. Table 5. RC19013A Pin Descriptions (Cont.)

29 OEb9_SBI_IN I, SE, PD,

Active low input for enabling output 9 or the data pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. 30 VDDCLK PWR Clock power supply. 31 CLK9 O, DIF True clock output. 32 CLKb9 O, DIF Complementary clock output.

33 OEb8 I, SE, PD,

Active low input for enabling output 8. 0 = Enable output, 1 = Disable output. 34 CLK8 O, DIF True clock output. 35 CLKb8 O, DIF Complementary clock output.

36 OEb7 I, SE, PD,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 37 CLK7 O, DIF True clock output. 38 CLKb7 O, DIF Complementary clock output. 39 CLK6 O, DIF True clock output. 40 CLKb6 O, DIF Complementary clock output. 41 VDDCLK PWR Clock power supply.

42 OEb6_SBI_CLK I, SE, PD,

0 = Enable output, 1 = Disable output. Clocks data into the SBI shift register on the rising edge. 43 CLK3 O, DIF True clock output. 44 CLKb3 O, DIF Complementary clock output.

45 OEb3 I, SE, PD,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

46 OEb2_SBI_OUT I, SE, PD

Side-Band Interface (SBI). Note: This pin is NOT PDT. 0 = Enable output, 1 = Disable output. SBI shift register data output. 47 CLK2 O, DIF True clock output. 48 CLKb2 O, DIF Complementary clock output. 49 VDDCLK PWR Clock power supply. 50 CLK1 O, DIF True clock output.

1.7 RC19008A Pin Assignments

Figure 7. RC19008A 40-VFQFPN – Top View

1.7.1 RC19008A Pin Descriptions

51 CLKb1 O, DIF Complementary clock output.

52 OEb1 I, SE, PD,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 53 CLK0 O, DIF True clock output. 54 CLKb0 O, DIF Complementary clock output.

55 OEb0 I, SE, PD,

Active low input for enabling output 0. 0 = Enable output, 1 = Disable output. 57 EPAD GND Connect epad to ground. Table 6. RC19008A Pin Descriptions a loss of signal on the input clock. Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate.

• 40 39 38 37 36 35 34 33 32 31 LOSb 13 0 OEb5_SBI_CLK SL EWRA TE_ SEL22 9 CLKb5 SADR_tri1 32 8 CLK5 SADR_tri0 42 7 OEb6 SDATA 52 6 V DDCLK SCLK 62 5 CLKb6 V DDDIG72 4 CLK6 CLKIN 82 3 CLKb7 CLKINb 92 2 CLK7 V DDCLK10 21 OEb7 11 12 13 14 15 16 17 18 19 20SBI_ENQ PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 CLK10 CLKb10 OEb10_SBI_IN VDDCLK RC19008 Connect EPAD to ground Top View

Decode table and tri-level input thresholds in the electrical tables. Decode table and tri-level input thresholds in the electrical tables. OD Data pin for SMBus interface. 6 SCLK I, SE Clock pin of SMBus interface. 8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input. 10 VDDCLK PWR Clock Power supply.

11 SBI_ENQ I, SE, PD,

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

12 PWRGD_PWRDNb I, SE, PU,

Input notifies device to sample latched inputs and start up on first high assertion. 13 VDDCLK PWR Clock power supply.

14 OEb13_SHFT_LDb I, SE, PD,

information, see Side-Band Interface (SBI). 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 15 CLK13 O, DIF True clock output. 16 CLKb13 O, DIF Complementary clock output. 17 CLK10 O, DIF True clock output. 18 CLKb10 O, DIF Complementary clock output.

19 OEb10_SBI_IN I, SE, PD,

Active low input for enabling output 10 or the data pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. SBI shift-register data input. 20 VDDCLK PWR Clock power supply.

21 OEb7 I, SE, PD,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. Table 6. RC19008A Pin Descriptions (Cont.)

22 CLK7 O, DIF True clock output. 23 CLKb7 O, DIF Complementary clock output. 24 CLK6 O, DIF True clock output. 25 CLKb6 O, DIF Complementary clock output. 26 VDDCLK PWR Clock Power supply.

27 OEb6 I, SE, PD,

Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 28 CLK5 O, DIF True clock output. 29 CLKb5 O, DIF Complementary clock output.

30 OEb5_SBI_CLK I, SE, PD,

0 = Enable output, 1 = Disable output. Clocks data into the SBI on the rising edge. 31 CLK3 O, DIF True clock output. 32 CLKb3 O, DIF Complementary clock output.

33 OEb3 I, SE, PD,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

34 OEb2_SBI_OUT I, SE, PD

Side-Band Interface (SBI). Note: This pin is NOT PDT. 0 = Enable output, 1 = Disable output. SBI shift register data output. 35 CLK2 O, DIF True clock output. 36 CLKb2 O, DIF Complementary clock output. 37 VDDCLK PWR Clock power supply. 38 CLK1 O, DIF True clock output. 39 CLKb1 O, DIF Complementary clock output.

40 OEb1 I, SE, PD,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 41 EPAD GND Connect epad to ground.

1.8 RC19004A Pin Assignments

Figure 8. RC19004A 28-VFQFPN – Top View

1.8.1 RC19004A Pin Descriptions

Table 7. RC19004A Pin Descriptions

1 SADR_tri1 I, SE, PD,

Decode table and the tri-level input thresholds in the electrical tables.

2 SADR_tri0 I, SE, PD,

Decode table and the tri-level input thresholds in the electrical tables.

3 SDATA I/O, SE,

OD Data pin for SMBus interface. 4 SCLK I, SE Clock pin of SMBus interface. 6 CLKIN I, DIF True clock input. 7 CLKINb I, DIF Complementary clock input.

8 SBI_ENQ I, SE, PD,

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

9 PWRGD_PWRDNb I, SE, PU,

Input notifies device to sample latched inputs and start up on first high assertion.

• 28 27 26 25 24 23 22 SA DR_tri1 1 21 OEb5_SBI_CLK SA DR_tri0 2 20 CLKb5 SDATA 3 19 CLK5 SCLK 4 18 V DDCLK V DDDIG 5 17 CLKb9 CLKIN 6 16 CLK9 CLKINb7 15 V DDCLK 8 9 10 11 12 13 14SBI_ENQ PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 OEb9_SBI_IN RC19004 Connect epad to ground Top view

10 VDDCLK PWR Clock power supply.

11 OEb13_SHFT_LDb I, SE, PD,

information, see Side-Band Interface (SBI). 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 12 CLK13 O, DIF True clock output. 13 CLKb13 O, DIF Complementary clock output.

14 OEb9_SBI_IN I, SE, PD,

Active low input for enabling output 9 or the data pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. 15 VDDCLK PWR Clock power supply. 16 CLK9 O, DIF True clock output. 17 CLKb9 O, DIF Complementary clock output. 18 VDDCLK PWR Clock power supply. 19 CLK5 O, DIF True clock output. 20 CLKb5 O, DIF Complementary clock output.

21 OEb5_SBI_CLK I, SE, PD,

0 = Enable output, 1 = Disable output. Clocks data into the SBI on the rising edge.

22 OEb2_SBI_OUT I, SE, PD

Side-Band Interface (SBI). Note: This pin is NOT PDT. 0 = Enable output, 1 = Disable output. SBI shift register data output. 23 CLK2 O, DIF True clock output. 24 CLKb2 O, DIF Complementary clock output. 25 VDDCLK PWR Clock power supply.

27 SLEWRATE_SEL I, SE, PU,

Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate. Table 7. RC19004A Pin Descriptions (Cont.)

2.1 Absolute Maximum Ratings

2.2 ESD Ratings

28 LOSb O, OD,

a loss of signal on the input clock. 29 EPAD GND Connect to ground.

1. Pins designated Power Down Tolerant (PDT) in the pin description tables.
2. Pins not designated Power Down Tolerant (PDT) in the pin description tables.

R31DS0016EU0110 Rev.1.10 Page 31 Dec 1, 2022 RC190xx Datasheet

2.3 Recommended Operation Conditions

2.4 Thermal Information

Symbol Parameter Condition Minimum Typical Maximum Unit TJ Maximum Junction Temperature - - - 125 °C TA Ambient Operating Temperature - -40 25 105 °C tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic). 0.05 - 5 ms Package [1] Symbol Condition Typical Value (°C/W) 8 × 8 mm 100-VFQFPN (5.1 × 5.1 mm ePad) θJc Junction to Case 8.6 θJb Junction to Base 0.6 θJA0 Junction to Air, still air 21.4 θJA1 Junction to Air, 1 m/s air flow 17.9 θJA3 Junction to Air, 3 m/s air flow 15.8 θJA5 Junction to Air, 5 m/s air flow 15.3 6 × 6 mm 80-GQFN (2.8 × 2.8 mm ePad) θJc Junction to Case 44 θJb Junction to Base 2 θJA0 Junction to Air, still air 33 θJA1 Junction to Air, 1 m/s air flow 29 θJA3 Junction to Air, 3 m/s air flow 28 θJA5 Junction to Air, 5 m/s air flow 27 10 × 10 mm 72-VFQFPN (5.95 × 5.95 mm ePad) θJc Junction to Case 16.9 θJb Junction to Base 2.7 θJA0 Junction to Air, still air 26.4 θJA1 Junction to Air, 1 m/s air flow 22.7 θJA3 Junction to Air, 3 m/s air flow 20.6 θJA5 Junction to Air, 5 m/s air flow 19.8 9 × 9 mm 64-VFQFPN (5.2 × 5.2 mm ePad) θJc Junction to Case 24.6 θJb Junction to Base 2.7 θJA0 Junction to Air, still air 26.8 θJA1 Junction to Air, 1 m/s air flow 22.9 θJA3 Junction to Air, 3 m/s air flow 21.5 θJA5 Junction to Air, 5 m/s air flow 20.7

R31DS0016EU0110 Rev.1.10 Page 32 Dec 1, 2022 RC190xx Datasheet 7 × 7 mm 56-VFQFPN (5.3 × 5.3 mm ePad) θJc Junction to Case 26.6 θJb Junction to Base 3.4 θJA0 Junction to Air, still air 26.9 θJA1 Junction to Air, 1 m/s air flow 23.4 θJA3 Junction to Air, 3 m/s air flow 21.9 θJA5 Junction to Air, 5 m/s air flow 21.0 5 × 5 mm 40-VFQFPN (3.3 × 3.3 mm ePad) θJc Junction to Case 37.0 θJb Junction to Base 4.8 θJA0 Junction to Air, still air 33.1 θJA1 Junction to Air, 1 m/s air flow 29.6 θJA3 Junction to Air, 3 m/s air flow 28.0 θJA5 Junction to Air, 5 m/s air flow 27.1 4 × 4 mm 28-VFQFPN (2.6 × 2.6 mm ePad) θJc Junction to Case 45.3 θJb Junction to Base 2.2 θJA0 Junction to Air, still air 36.3 θJA1 Junction to Air, 1 m/s air flow 32.7 θJA3 Junction to Air, 3 m/s air flow 31.0 θJA5 Junction to Air, 5 m/s air flow 30.0 1. ePad soldered to board. Package [1] Symbol Condition Typical Value (°C/W)

2.5 Electrical Characteristics

2.5.1 Phase Jitter

Table 8. PCIe Refclk Phase Jitter - Normal Conditions[1][2][3][8]

1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 6.0, Revision 1.0. For the exact
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a

jitter using a multiplication factor of 8.83.

1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any
2. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
5. The PCI Express Base Specification 6.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values; it does not provide

can choose to use this more relaxed value as the jitter limit.

1. Differential input swing ≥ 1600mV and input slew rate ≥ 3.5V/ns

Table 9. PCIe Refclk Phase Jitter - Degraded Conditions[1][2][3][8]

1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 6.0, Revision 1.0. For the exact
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a

jitter using a multiplication factor of 8.83.

1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any
2. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
5. The PCI Express Base Specification 6.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values; it does not provide

may choose to use this more relaxed value as the jitter limit.

1. Differential input swing = 800mV and input slew rate = 1.5V/ns

2.5.2 Output Frequencies, Startup Time, and LOS Timing

Table 10. Non-PCIe Refclk Phase Jitter [1][2][3]

1. See Test Loads for test configuration.
2. SMA100B used as signal source.
3. The RC19xxx devices meet all legacy QPI/UPI specifications by meeting the PCIe and DB2000Q specifications listed in this document.
4. Differential input swing = 1,600mV and input slew rate = 3.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Differential input swing = 800mV and input slew rate = 1.5V/ns.

Table 11. Output Frequencies, Startup Time, and LOS Timing

1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output.

PWRGD_PWRDNb tied to VDD in this case.

1. VDD stable, measured from de-assertion of PWRGD_PWRDNb.
2. The clock detect circuit does not qualify the accuracy of the input clock. The first input clock must appear to release the power on reset

and enable the LOS circuit at power up.

1. PWRGD_PWRDNb high. The Automatic Clock Parking (ACP) circuit - if enabled - will park the outputs in a low/low state within this time.

See Byte4, bit 4 LOSb_ACP_ENABLE.

1. PWRGD_PWRDNb high. The device will drive the outputs to a high/low state within this time and then begin clocking the outputs.

2.5.3 RC1902xA CLK AC/DC Output Characteristics

The tables in this section apply to the RC19024A, RC19020A and RC19020A072. Table 12. RC1902xA 85-ohm CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe [1]

1. Standard high impedance load with CL = 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 6.0 or from relevant x86 processor specifications,

whichever is more stringent.

1. Measured from single-ended waveform.
2. Defined as the maximum instantaneous voltage including overshoot.
3. Defined as the minimum instantaneous voltage including undershoot.

1. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
2. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance

in VCROSS for any particular system.

1. Measured from differential waveform.
2. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be
3. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered

Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 13. RC1902xA 85Ω CLK AC/DC Characteristics - Non-PCIe, Source-Terminated Loads [1]

1. Standard high impedance load with CL = 2pF. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS
2. Measured from differential waveform.

Table 14. RC1902xA 85Ω CLK AC/DC Characteristics - Non-PCIe, Double-Terminated Loads[1]

1. Both Tx and Rx are terminated (double-terminated) with CL = 2pF. This reduces amplitude by 50%. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS

~50% due to double termination).

1. Measured from differential waveform.

2.5.4 RC1901xA/RC1900xA CLK AC/DC Output Characteristics

Table 15. RC1901xA/RC1900xA 85Ω CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe Applications [1]

1. Standard high impedance load with CL= 2pF. For more information, see Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 6.0 or from relevant x86 processor specifications,

whichever is more stringent.

1. Measured from single-ended waveform.
2. Defined as the maximum instantaneous voltage including overshoot.

1. Defined as the minimum instantaneous voltage including undershoot.
2. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
3. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance

in VCROSS for any particular system.

1. Measured from differential waveform.
2. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on

REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 16. RC1901xA\\RC1900xA 100Ω CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe Apps [1]

1. Standard high impedance load with CL= 2pF. For more information, see Test Loads.
2. The specification limits are taken from either the PCIe Base Specification Revision 6.0 or from relevant x86 processor specifications,

whichever is more stringent.

1. Measured from single-ended waveform.
2. Defined as the maximum instantaneous voltage including overshoot.
3. Defined as the minimum instantaneous voltage including undershoot.
4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance

in VCROSS for any particular system.

1. Measured from differential waveform.
2. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on

REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 16. RC1901xA\\RC1900xA 100Ω CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe Apps [1] (Cont.)

Table 17. RC1901xA/RC1900xA 85Ω CLK AC/DC Characteristics - Non-PCIe Apps, Source-Terminated Loads [1]

1. Standard high impedance load with CL= 2pF. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS
2. Measured from differential waveform.

Table 18. RC1901xA/RC1900xA 85Ω CLK AC/DC Characteristics - Non-PCIe Apps, Double-Terminated Loads [1]

1. Both Tx and Rx are terminated (double-terminated) with CL= 2pF. This reduces amplitude by 50%. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS
2. Measured from differential waveform.

Table 19. RC1901xA/RC1900xA 100Ω CLK AC/DC Characteristics - Non-PCIe Apps, Source-Terminated Loads [1]

1. Standard high impedance load with CL= 2pF. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS
2. Measured from differential waveform.

Table 20. RC1901xA/RC1900xA 100Ω CLK AC/DC Characteristics–Non-PCIe Apps, Double-Terminated Loads [1]

2.5.5 Output-to-Output and Input-to-Output Skew

1. Both Tx and Rx are terminated (double-terminated) with CL= 2pF. This reduces amplitude by 50%. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

1. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS
2. Measured from differential waveform.

Table 21. RC1902xA Output-to-Output and Input-to-Output Skew [1]

1. For more information, see Test Loads.
2. This parameter is defined in accordance with JEDEC Standard 65.
3. Defined as the time between to output rising edge and the input rising edge that caused it.

2.5.6 I/O Signals

Table 22. RC1901xA/RC1900xA Output-to-Output and Input-to-Output Skew [1]

1. For more information, see Test Loads.
2. This parameter is defined in accordance with JEDEC Standard 65.
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 23. I/O Electrical Characteristics Single-ended inputs, unless otherwise listed.

2.5.7 Power Supply Current

1. For SCLK and SDATA, see the SMBus Electrical Characteristics table.
2. These values are compliant with JESD8C.01.

Table 24. Power Supply Current [1][2][3] terminated load at maximum output frequency. terminated load at maximum output frequency. Table 23. I/O Electrical Characteristics (Cont.)

terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. Table 24. Power Supply Current [1][2][3] (Cont.)

terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency.

terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency.

1. For more information, see Test Loads.
2. Output voltage set to 800mV. Slew rate has negligible effect on current consumption, so only fast is listed.
3. Total operating current is obtained by adding IDDCLK + IDDDIG, or IDDCLK + IDDR for a particular device and operating mode. Power

down current is obtained by adding IDDCLK_PD + IDDDIG_PD, or IDDCLK_PD + IDDR_PD for a particular device.

2.5.8 CLKIN AC/DC Characteristics

Figure 9. Clock Input Bias Network

2.5.9 SMBus Electrical Characteristics

Figure 10. SMBus Slave Timing Diagram Table 25. CLKIN AC/DC Characteristic

1. For values required for performance, see the Phase Jitter tables.
2. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero-crossing. Table 26. SMBus DC Electrical Characteristics [1]

1. VOH is governed by the VPUP, the voltage rail to which the pull-up resistors are connected.
2. For more information, see I/O Electrical Characteristics.

Table 27. SMBus AC Electrical Characteristics

1. Power must be applied and PWRGD_PWRDNb must be a 1 for the SMBus to be active.
2. A master should not drive the clock at a frequency below the minimum fSMB. Further, the operating clock frequency should not be reduced

received byte, data buffering and so forth for longer than 100 µs in a non-periodic way.

1. A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the VIH,MIN of the SMBCLK signal) to bridge

the undefined region of the falling edge of SMBCLK.

1. Slave devices may have caused other slave devices to hold SDA low. This is the maximum time that a device can hold SMBDAT low after
2. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the

timeout holds the SMBCLK low for tTIMEOUT,MAX or longer.

1. The device has the option of detecting a timeout if the SMBDATA pin is also low for this time.
2. tHIGH,MAX provides a simple guaranteed method for masters to detect bus idle conditions. A master can assume that the bus is free if it

detects that the clock and data signals have been high for greater than tHIGH,MAX.

1. tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from

the sole target of the master.

1. The rise and fall time measurement limits are defined as follows:
2. Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

2.5.10 Side-Band Interface

Figure 11. Side-Band Interface Timing Figure 11 is the timing diagram and Table 28 provides the electrical characteristics for the Side-Band Interface. The SBI supports clock rates up to 25MHz. Table 28. Electrical Characteristics – Side-Band Interface

1. Refers to the output clock.
2. Control input must be monotonic from 20% to 80% of input swing.

Current O/P Config. Next O/P Config.

Figure 14. Test Load for PCIe Phase Jitter Measurements Table 31. Parameters for PCIe Gen5 Jitter Measurement

1. PCIe Gen6 specifies L = 0cm for 32 and 64 GT/s. L = 25.4cm is more conservative.

R31DS0016EU0110 Rev.1.10 Page 56 Dec 1, 2022 RC190xx Datasheet 4. General SMBus Serial Interface Information

4.1 How to Write

▪ Controller (host) sends a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) sends the byte count = X ▪ Renesas clock will acknowledge ▪ Controller (host) starts sending Byte N through Byte N+X-1 ▪ Renesas clock will acknowledge each byte one at a time ▪ Controller (host) sends a stop bit

4.2 How to Read

▪ Controller (host) will send a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) will send a separate start bit ▪ Controller (host) sends the read address ▪ Renesas clock will acknowledge ▪ Renesas clock will send the data byte count = X ▪ Renesas clock sends Byte N+X-1 ▪ Renesas clock sends Byte L through Byte X (if X(H) was written to Byte 7) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit Index Block Write Operation Controller (Host) Renesas (Slave/Receiver) T starT bit Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK P stoP bit Index Block Read Operation Controller (Host) Renesas T starT bit Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not P stoP bit

R31DS0016EU0110 Rev.1.10 Page 57 Dec 1, 2022 RC190xx Datasheet

4.3 SMBus Bit Types

4.4 Write Lock Functionality

4.5 SMBus Address Decode

Bit Description Definition RO Read-only RW Read-write RW1C Read/Write ‘1’ to clear RESERVED Undefined do not write WRITE_LOCK WRITE_LOCK RW1C SMBus Write Protect 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes Address Selection Binary Value Hex Value SADR_tri1 SADR_tri0 7 6 5 4 3 2 1 Rd/Wrt 0 1 1 0 1 1 0 0 0 D8 M 1 1 0 1 1 0 1 0 DA 1 1 1 0 1 1 1 1 0 DE M 0 1 1 0 0 0 0 1 0 C2 M 1 1 0 0 0 1 0 0 C4 1 1 1 0 0 0 1 1 0 C6 0 1 1 0 0 1 0 1 0 CA M 1 1 0 0 1 1 0 0 CC 1 1 1 0 0 1 1 1 0 CE

4.6 RC19024A SMBus Registers

Table 32. RC19024A SMBus Registers

0 OUTPUT_ENABLE_0

1 OUTPUT_ENABLE_1

2 OUTPUT_ENABLE_2

3 OEb_PIN_READBACK

4 SBEN_RDBK_

5 VENDOR_REVISION_ID

6 DEVICE_ID DEVICE_ID [7:0] RO 0x18 Device ID -

7 BYTE_COUNT

8 SBI_MASK_0

Table 32. RC19024A SMBus Registers (Cont.)

9 SBI_MASK_1

10 SBI_MASK_2

11 SBI_READBACK_0 [1]

12 SBI_READBACK_1 [1]

13 SBI_READBACK_2 [1]

14 OEb_ASSIGNMENT_0

15 OEb_ASSIGNMENT_1

16 OEb_ASSIGNMENT_2

17 LPHCSL_AMP_CTRL

18 PD_RESTORE_LOSb

19 Reserved RESERVED [7:0] RW 0x07 RESERVED -

20 OUTPUT_SLEW_

21 OUTPUT_SLEW_

22 OUTPUT_SLEW_

38 WRITE_LOCK_NCLEAR

39 WRITE_LOCK_CLEAR_

1. Register only valid when the Side-Band Interface is enabled (SBI_ENQ = 1).

4.7 RC19020A SMBus Registers

Table 33. RC19020A SMBus Registers

0 OUTPUT_ENABLE_2

1 OUTPUT_ENABLE_0

2 OUTPUT_ENABLE_1

6 DEVICE_ID DEVICE_ID [7:0] RO 0xC9 Device ID -

Table 33. RC19020A SMBus Registers (Cont.)

11 OUTPUT_SLEW_

12 OUTPUT_SLEW_

13 OUTPUT_SLEW_

19 RESERVED - - - - RESERVED -

20 LPHCSL_AMP_CTRL

21 PD_RESTORE_LOSb

33 SBI_READBACK_0 [1]

34 SBI_READBACK_1 [1]

35 SBI_READBACK_2 [1]

1. Register only valid when the Side-Band Interface is enabled (SBI_ENQ = 1).

4.8 RC19020A072 SMBus Registers

Table 34. RC19020A072 SMBus Registers

6 DEVICE_ID DEVICE_ID [7:0] RO 0xC8 Device ID -

8 OEb_Configuration_A

9 OEb_Configuration_B

10 OEb_Configuration_C_

Table 34. RC19020A072 SMBus Registers (Cont.)

20 RESERVED - - - - RESERVED -

22 SBI_MASK_0 [2]

23 SBI_MASK_1 [2]

24 SBI_MASK_2 [2]

33 SBI_READBACK_0 [2]

34 SBI_READBACK_1 [2]

35 SBI_READBACK_2 [2]

4.9 RC1901xA/RC1900xA SMBus Registers

1. Register is only valid when the Side-Band Interface is not enabled (SBI_ENQ = 0).
2. Register only valid when the Side-Band Interface is enabled (SBI_ENQ = 1).

Table 35. RC1901xA/RC1900xA SMBus Registers

2 OEb_PIN_READBACK_0

3 OEb_PIN_READBACK_1

5 VENDOR_REVISION_

Table 35. RC1901xA/RC1900xA SMBus Registers (Cont.)

6 DEVICE_ID [7:0] DEVICE_ID RO 0x18

10 RESERVED [7:0] Reserved - - - -

18 PD_RESTORE_LOSb_

19 RESERVED [7:0] Reserved - - - -

38 WRITE_LOCK_

39 WRITE_LOCK_

R31DS0016EU0110 Rev.1.10 Page 81 Dec 1, 2022 RC190xx Datasheet 5. Applications Information

5.1 Inputs, Outputs, and Output Enable Control

5.1.1 Recommendations for Unused Inputs and Outputs

5.1.1.1 Unused Differential CLKIN Inputs

The CLKIN/CLKINb inputs of the RC19xxx devices have internal bias networks that protect the devices from a floating input clock condition. For RC192xx multiplexers that use only one input clock, the unused input can be left open. Renesas recommends that no trace be attached to unused CLKIN pins.

5.1.1.2 Unused Single-ended Control Inputs

The single-ended control pins have internal pull-up and/or internal pull-down resistors and do not require external resistors. They can be left floating if the default pin state is the desired state. If external resistors are needed to change the pin state or are desired for design robustness, 10kohm is the recommended value.

5.1.1.3 Unused Differential CLK Outputs

All unused CLK outputs can be left floating. Renesas recommends that no trace be attached to unused CLK outputs. While not required (but is highly recommended), the best design practice is to disable unused CLK outputs.

5.1.1.4 Unused SMBus Clock and Data Pins

If the SMBus interface is not used, the clock and data pins must be pulled high with an external resistor. The two pins can share a resistor if there is no possibility of using the SMBus interface for debug purposes. If the interface may be used for debug, separate resistors should be used. 10kohm is the recommended value.

5.1.2 Differential CLKIN Configurations

The RC19xxx clock input buffer supports four configurations: ▪ Direct connection to HCSL-level inputs ▪ Direct connection to LVDS-level inputs with external termination resistor ▪ Internal self-bias circuit for applications that externally AC-couple the input clock

• This feature is enabled by the AC_IN bit. ▪ Internal pull-down resistors (Rp) to terminate the clock input at the receiver.
• This feature is enabled by the Rx_TERM bit. Devices with multiple input clocks have individual AC_IN and Rx_TERM configuration bits for each input. The internal input clock terminations prevent reflections and are useful for non-PCIe applications, where the frequency and transmission line length vary from the 100MHz PCIe standard. Figure 15 through Figure 18 illustrate the above items.

5.1.3 Differential CLK Output Configurations

5.1.3.1 Direct-Coupled HCSL Loads

HCSL-level inputs with no external components. They support both 85ohm and 100ohm differential impedances. half of the source-terminated values.

5.1.3.2 AC-Coupled non-HCSL Loads

terminating the RC19xxx CLK outputs to other logic families such as LVDS, LVPECL, or CML, see AN-891. Figure 19 to Figure 21 show the various CLK output configurations. Figure 19. Direct-Coupled Source-Terminated HCSL Figure 15. HCSL Input Levels (PCIe Standard) Figure 16. LVDS Input Levels Figure 17. External AC-Coupling Figure 18. Receiver Termination

Figure 20. Direct-Coupled Double-Terminated HCSL Figure 21. AC-Coupled

5.2 Power Down Tolerant Pins

before it has received power. Figure 22 provides an example of a PDT call-out in a data sheet.

5.3 Flexible Startup Sequencing

Figure 22. Example: Power Down Tolerant Pin Descriptions CLKIN running before VDD is applied, and can have VDD applied and sit for extended periods with no input clock.

5.4 Loss of Signal and Automatic Clock Parking

the LOS_EVT bit in the SMBus register space. There are two slightly different LOSb pin behaviors at power up. differentially in Figure 23 and Figure 24. Figure 23. LOSb De-assert Timing, RC1900x, RC1901x, RC19024 after power up. So, the LOSb pin will be high until the first clock edge after power up. on the 20-output buffers and all RC192xx multiplexers defaults to low at power up. Figure 24. LOSb De-assert Timing RC19020, RC192xx Devices Note: The LOSb pin monitors the selected input clock in the RC192xx multiplexers. Table 36. Flexible Startup Sequences

Figure 25. LOSb Assert Timing

5.5 Output Enable Control

when all three mechanisms indicate “enabled.” The following sections describe the three mechanisms.

5.5.1 SMBus Output Enable Bits

between the enable and disable states are glitch-free in both directions.

5.5.2 Output Enable (OEb) Pins

low/low state. All OEb pins enable and disable the controlled outputs in a glitch-free, synchronous manner.

5.5.3 RC1902x Clock Buffer OEb Pins

outputs, and defaults to controlling one output. The RC19024A output enable mapping is described in Table 37. Table 37. RC19024A OEb Mapping

The RC19020A and the RC19020A072 each have 8 OEb pins. Some of the pins are muxed with SBI functions.

1. See the OEb_ASSIGNMENT registers in Table 32.

Table 38. RC19020A OEb Mapping Table 39. RC19020A072 OEb Mapping[1] Table 37. RC19024A OEb Mapping (Cont.)

pins are used for the SBI interface when SBI_ENQ = 1 (for more information, see Table 40).

1. See the OEb_ASSIGNMENT registers in Table 34.

Table 40. RC19016A, RC19013A, RC19008A, RC19004A Buffer OEb Mapping Table 39. RC19020A072 OEb Mapping[1] (Cont.)

R31DS0016EU0110 Rev.1.10 Page 88 Dec 1, 2022 RC190xx Datasheet

5.5.4 Side-Band Interface (SBI)

SMBus output enable bits and OEb pins are the traditional methods for enabling and disabling clocks. The 2-wire SMBus interface can enable or disable all clock outputs in a device. This pin efficiency is its advantage. The SMBus interface’s main drawback is that it is a relatively slow physical interface, whose software is one of several routines running on an often overtaxed micro-controller. OEb pins are real-time and are ideally dedicated to an individual clock output. As buffers grow in output count, dedicated OEb pins become problematic for two reasons. First, the clock buffer pin count becomes much larger than it otherwise would be, resulting in a larger package. Second, unless the OEb pins are used for CLKREQ# functionality, the number of pins that need to be controlled outgrows the GPIO pins of an FPGA or micro-controller. A third output enable/disable mechanism, the Side-Band Interface (SBI), addresses these issues. The SBI is a simple 3-wire (4-wire if the SBI_OUT pin is used) interface that can control all outputs across multiple devices. The SBI is only slightly less pin efficient than the SMBus, and is much more pin efficient than a dedicated OEb pins per output. It is protocol-free, hardware-oriented and runs at speeds up to 25MHz, much faster than SMBus. Another SBI advantage is that it is active after power is applied and before PWRGD is asserted. External logic can disable specific outputs before PWRGD is asserted, and can then dynamically adjust the output run state during device operation. The SBI can make the adjustments much more rapidly than SMBus. The RC19xxxA 4-wire SBI interface consists of the SBI_IN, SBI_CLK, SHFT_LDb, and SBI_OUT pins. The RC19xxxA SBI is enabled by strapping the SBI_ENQ pin to 1. When enabled, various OEb pins become the SBI interface. The exact pins that are multiplexed vary with device (for more information, see Table 40). The SBI_ENQ pin strap takes effect as soon as power is applied and is not dependent on the assertion of PWRGD_PWRDNb to 1. Because of this, the SBI_ENQ must be static and cannot change once power is applied. If SBI_ENQ is 0 when power is applied, the SBI is disabled and has no impact on enabling or disabling outputs. The SBI consists of a shift register, an SMBus readback register (of the shift register contents), and an SMBus MASK register. The SBI shifts a bit stream containing the enable/disable pattern into the shift register. A 1 enables an output and a 0 disables an output. All shift-register bits default to 1 at power up, indicating an enabled state. This means that the SBI can be used to disable outputs at power up because the default is enabled. The SBI has its own SBI_CLK and does not need a running CLKIN to shift in an enable/disable pattern. This provides utmost flexibility for setting output run state before the SMBus becomes active or before the CLKIN is applied. When the SBI indicates enabled, the standard SMBus output enable bits and OEb pins can control the outputs. The SBI feeds common output enable/disable synchronization logic ensuring glitch-free enable and disable of outputs. Note: The glitch-free synchronization logic requires the CLKIN be running to enable or disable the outputs with this mechanism. If the application does not use the SBI, the SBI_ENQ pin can be tied to 0, and the entire SBI has no impact on enabling or disabling clock outputs. The SBI Mask registers allow the user to block the disable function of the SBI via the SMBus. The SBI Mask registers default to 0 at power-up, allowing the SBI shift register bits to disable their respective output. After asserting the PWRGD_PWRDNb pin high, the SMBus is active and the SBI mask registers can be configured via SMBus to mask off (block) the SBI disable function. In other words, setting and SBI Mask bit to 1 forces the SBI to always indicate “enable” for the respective output. This allows the user to prevent the SBI from accidentally turning off a critical output. The RC190xx clock buffers provide the ability to read back the SBI shift register contents via the SMBus. The SMBus readback values update on each falling edge of SHFT_LDb. Note: The SBI shift register can only be read using the SMBus; the SMBus cannot be used to load it. Figure 26 shows the high-level functional description of SBI.

Figure 26. Side-band Interface High-Level Functional Diagram (RC19024A shown)

5.5.4.1 Using the SBI

which is in Byte 2 bit 7. The last bit shifted in would be the output enable/disable for CLK0, which is in Byte 0, bit 0. Figure 27. RC19024A Side-Band Shift Order

Figure 31. RC19008A Side-Band Shift Order Figure 32. RC19004A Side-Band Shift Order

5.5.4.2 Side-Band Interface Timing

Characteristics, see Table 28. Figure 33. Side-Band Interface Functional Timing

5.5.4.3 Side-Band Interface Connection Topologies

interface ignores any activity on the SBI_CLK and SBI_IN pins. devices to be controlled at the cost of an additional GPIO per device. Figure 34. Side-Band Interface Star Topology controller. It uses the SBI_OUT pin of one device to drive the SBI_IN pin of the next device in the daisy chain. the SBI bit stream consists of 48 bits. Figure 35. Side-Band Interface Daisy-Chain Topology

5.5.5 Output Enable/Disable Priority

enabled in order for the output to be enabled. A logical representation of the priority logic is shown in Figure 36. Figure 36. Output Enable/Disable Priority (Logical) available and is subject to change without revision of this document.

R31DS0016EU0110 Rev.1.10 Page 94 Dec 1, 2022 RC190xx Datasheet 7. Marking Diagrams

7.1 RC1901xA/RC1900xA Marking Diagrams

▪ Lines 1 and 2: part number. ▪ Line 3:

• “#” indicates stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. ▪ Lines 1 and 2 (for 85Ω); 1, 2, and 3 (for 100Ω): part number. ▪ Line 3 (for 85Ω) or 4 (for 100Ω):
• “#” indicates stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled. ▪ “$” indicates the mark code. ▪ Lines 1 and 2: part number. ▪ Line 3:
• “#” indicates stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled. ▪ “$” indicates the mark code. ▪ Line 1: truncated part number. ▪ Line 2:
• “YYWW” indicates the last two digits of the year and work week the part was assembled. ▪ “$” indicates the mark code. RC19016A 64-VFQFPN 85Ω RC19016A 64-VFQFPN 100Ω RC19013A 56-VFQFPN 85Ω RC19013A 56-VFQFPN 100Ω RC19008A 40-VFQFPN 85Ω RC19008A 40-VFQFPN 100Ω RC19004A 28-VFQFPN 85Ω RC19004A 28-VFQFPN 100Ω

R31DS0016EU0110 Rev.1.10 Page 95 Dec 1, 2022 RC190xx Datasheet

7.2 RC1902xA Marking Diagrams

▪ Lines 2 and 3: part number ▪ Line 4:

• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. ▪ “LOT” denotes the lot number
• “COO” denotes country of origin. ▪ Lines 2 and 3: part number ▪ Line 4:
• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. ▪ “LOT” denotes the lot number RC19024A 100-VFQFPN 85Ω RC19020A 80-GQFN 85Ω ▪ Lines 2 and 3: part number ▪ Line 4:
• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. ▪ “LOT” denotes the lot number
• “COO” denotes country of origin. RC19020A072 72-VFQFPN 85Ω

Table 41. Ordering Information

R31DS0016EU0110 Rev.1.10 Page 97 Dec 1, 2022 RC190xx Datasheet 9. Revision History Revision Date Description 1.10 Dec 1, 2022 ▪ Fixed the link for the 40-VFQFPN package in Table 41. 1.09 Nov 17, 2022 ▪ Changed tSLEW to 6 from 4 in Table 28.

1.08 Nov 15, 2022 ▪ Updated the description of RC19024 pin A7 in Table 1

1.07 Apr 11, 2022

▪ For all devices except RC19020A072:

• Updated Pin Type of all pins beginning with OEb to properly indicate internal pull-down (PD) resistors. ▪ For all devices except RC19020A072 and RC19024A:
• Removed Power-Down Tolerant indicator from multiplexed OEb SBI_OUT pins, they are not PDT. ▪ Minor reformatting of Pin Descriptions to reduce required space in Pin Description tables and to provide consistency across devices.

1.06 Apr 4, 2022

▪ Updated Loss of Signal and Automatic Clock Parking to change all CLK_IN to CLKIN for consistency. ▪ Inserted LOSb De-assert Timing RC19020, RC192xx Devices figure to distinguish the LOSb start-up behavior of those devices from the other devices.

1.05 Mar 23, 2022 Updated pins B10 and B43 from Do Not Connect (DNC) to GND on RC19024A Pin

Assignments to tie off floating pins used for test. 1.04 Mar 15, 2022 Updated the PCI Express Base Specification 6.0 revision reference to 1.0 in footnotes 1 and 7 in Table 8 and Table 9. 1.03 Mar 3, 2022 ▪ Corrected pin 10 of RC19008A from NC to VDDCLK (see RC19008A Pin Assignments). 1.02 Feb 24, 2022 ▪ Completed minor updates to titles of CLK AC/DC Characteristics Tables for clarity. ▪ Completed other minor changes

1.01 Feb 01, 2022

▪ Added RC19020A072 pin out and pin descriptions to data sheet. ▪ Updated Figure 9 for RC19020A and RC19020A072. ▪ Updated Figure 2 title to reference correct package type (VFQFPN) and updated “100- GQFN” references to “100-VFQFPN” throughout the document. ▪ Added RC19020A072 marking diagram to RC1902xA Marking Diagrams and updated marking descriptions of RC19020A and RC19020A072. 1.00 Jan 18, 2022 Initial release.

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M

12 BCDEFGHJKL

Ø0.225 6.00 ±0.10 SIDE VIEW 6.00 ±0.10Pin 1Index 0.50 5.50 Ref0.25 ±0.10 0.352.80 ±0.10 0.80 ±0.10C 5.500.50 5.500.500.352.80 2.80RECOMMENDED LAND PATTERN(PCB Top View, NSMD Design) 0.08C © Renesas Electronics Corporation

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© Integrated Device Technology, Inc. Package Revision HistoryRev No.Date CreatedDescriptionMay 8, 2017Rev 02Change Package Code QFN to VFQFPNSept 3, 2019Rev 03Update P1 Dimension from 5. 8 to 5.95 mm SQ

TOP VIEWBOTTOM VIEW2x2x 0.10C0.10C SIDE VIEW 16 3233 464764 9.00Index AreaAB 9.00 5.20 ±0.10 5.20 ±0.10 C0.35Pin 1 ID (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN 9.308.200.50 0.25 0.555.20 5.20C0.35 © Renesas Electronics Corporation

(PCB Top View, NSMD Design) 0.35 0.35 5.00 ±0.10 5.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW0.40 3.50 ±0.10 3.50 ±0.10 0.40 SIDE VIEW RECOMMENDED LAND PATTERN 0.20 (0.35) 0.200.40Package Outline 3.50 3.50 4.20 5.30 5.30 © Renesas Electronics Corporation

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