RC19002AGNT#BD0

RC190XX_V01 RENESAS | Alldatasheet

Document overview

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• PDF pages: 103

Technical content

Datasheet sections

• 1.1 Signal Types
• 1.2 RC19024 Pin Information
• 1.2.1 RC19024 Pin Assignments
• 1.2.2 RC19024 Pin Descriptions
• 1.3 RC19020 Pin Information
• 1.3.1 RC19020 Pin Assignments
• 1.3.2 RC19020 Pin Descriptions
• 1.4 RC19020A072 Pin Information
• 1.4.1 RC19020A072 Pin Assignments
• 1.4.2 RC19020A072 Pin Descriptions
• 1.5 RC19016 Pin Information
• 1.5.1 RC19016 Pin Assignments
• 1.5.2 RC19016 Pin Descriptions
• 1.6 RC19013 Pin Information
• 1.6.1 RC19013 Pin Assignments
• 1.6.2 RC19013 Pin Descriptions
• 1.7 RC19008 Pin Information
• 1.7.1 RC19008 Pin Assignments
• 1.7.2 RC19008 Pin Descriptions
• 1.8 RC19004 Pin Information
• 1.8.1 RC19004 Pin Assignments
• 1.8.2 RC19004 Pin Descriptions
• 1.9 RC19002 Pin Information
• 1.9.1 RC19002 Pin Assignments
• 1.9.2 RC19002 Pin Descriptions
• 2.1 Absolute Maximum Ratings
• 2.2 Recommended Operating Conditions
• 2.3 Thermal Specifications
• 2.4 Electrical Specifications
• 2.4.1 Phase Jitter
• 2.4.2 Output Frequencies, Startup Time, and LOS Timing
• 2.4.3 RC1902xA CLK AC/DC Output Characteristics
• 2.4.4 RC1901xA/RC1900xA CLK AC/DC Output Characteristics
• 2.4.5 Output-to-Output and Input-to-Output Skew
• 2.4.6 I/O Signals
• 2.4.7 Power Supply Current
• 2.4.8 CLKIN AC/DC Characteristics
• 2.4.9 SMBus Electrical Characteristics
• 2.4.10 Side-Band Interface
• 4.1 How to Write
• 4.2 How to Read
• 4.3 SMBus Bit Types
• 4.4 Write Lock Functionality
• 4.5 SMBus Address Decode
• 4.6 RC19024 SMBus Registers
• 4.7 RC19020 SMBus Registers
• 4.8 RC19020A072 SMBus Registers
• 4.9 RC19016/013/008/004 SMBus Registers

Features

▪ PCIe Gen5 additive phase jitter: 5.8fs RMS ▪ PCIe Gen6 additive phase jitter: 3.4fs RMS ▪ PCIe Gen7 additive phase jitter: 2.4fs RMS ▪ DB2000Q additive phase jitter: 10fs RMS ▪ 12kHz to 20MHz additive phase jitter: 30fs RMS at 156.25MHz ▪ Power Down Tolerant (PDT) inputs ▪ Flexible Startup Sequencing (FSS) ▪ Automatic Clock Parking (ACP) upon loss of CLKIN ▪ Spread-spectrum tolerant ▪ CLKIN accepts HCSL or LVDS signal levels ▪ -40 to +105°C, 3.3V ±10% operation ▪ All devices except RC19002:

• Selectable output slew rate via pin/SMBus
• 4-wire Side-Band Interface supports high-speed serial output enable and device daisy-chaining
• 9 SMBus addresses plus write protection
• 85Ω or 100Ω (A100 suffix) output impedance
• Pin-selectable slew rate ▪ RC19002: Pin-selectable output impedance

Figure 1. RC190xx Block Diagram

1. RC19016/13/08/04 only. Other devices use SMBus.
2. Some devices mux SBI with OEb pins. See specific pinouts. De vices with SBI have dedicated SBI_ENQ pin.
3. Does not apply to the RC19002. On RC19002, the SLEWRATE_SEL pin is ZOUT_SEL.

R31DS0016EU0128 Rev.1.28 Page 3 Nov 5, 2025 RC190xx Datasheet

R31DS0016EU0128 Rev.1.28 Page 4 Nov 5, 2025 RC190xx Datasheet 1. Pin Information

1.1 Signal Types

Term Description [1] 1. Some pins have both internal pull-up and pull-down resistors which bias the pins to VDD/2. Other pins are multi-mode and have an internal pull-up or internal pull-down depending on the mode. I Input O Output OD Open Drain Output I/O Bi-Directional PD Pull-down PU Pull-up Z Tristate D Driven X Don’t care SE Single ended DIF Differential PWR 3.3 V power GND Ground PDT Power Down Tolerant: These signals must tolerate being driven when the device is powered down.

1.2 RC19024 Pin Information

1.2.1 RC19024 Pin Assignments

Figure 2. RC19024 100-VFQFPN – Top View

1.2.2 RC19024 Pin Descriptions

Table 1. RC19024 Pin Descriptions Active low input for enabling output 23 or the clock pin for the SBI shift register. information, see Side-Band Interface (SBI). 0 = enable output, 1 = disable output. Clocks data into the SBI on the rising edge. A2 CLK23B O, DIF Complementary clock output. A3 CLK23 O, DIF True clock output. A4 CLKINb I, DIF, PDT Complementary clock input. A5 CLKIN I, DIF, PDT True clock input. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins. Decode table and the tri-level input thresholds in the electrical tables. A9 SCLK I, SE, PDT Clock pin of SMBus interface. A10 SDAT I/O, OD, PDT Data pin for SMBus interface. A11 CLK0b O, DIF Complementary clock output. A12 CLK0 O, DIF True clock output. A13 CLK1b O, DIF Complementary clock output. A14 CLK1 O, DIF True clock output. A15 CLK2b O, DIF Complementary clock output. A16 CLK2 O, DIF True clock output. A17 CLK3b O, DIF Complementary clock output. A18 CLK3 O, DIF True clock output. A19 CLK4b O, DIF Complementary clock output. A20 CLK4 O, DIF True clock output. A21 CLK5b O, DIF Complementary clock output. A22 CLK5 O, DIF True clock output. A23 CLK6b O, DIF Complementary clock output. A24 CLK6 O, DIF True clock output. A25 CLK7b O, DIF Complementary clock output. A26 CLK7 O, DIF True clock output. A27 CLK8b O, DIF Complementary clock output. A28 CLK8 O, DIF True clock output. A29 CLK9b O, DIF Complementary clock output. A30 CLK9 O, DIF True clock output.

A31 CLK10b O, DIF Complementary clock output. A32 CLK10 O, DIF True clock output. A33 CLK11b O, DIF Complementary clock output. A34 CLK11 O, DIF True clock output. A35 CLK12b O, DIF Complementary clock output. A36 CLK12 O, DIF True clock output. A37 CLK13b O, DIF Complementary clock output. A38 CLK13 O, DIF True clock output. A39 CLK14b O, DIF Complementary clock output. A40 CLK14 O, DIF True clock output. A41 CLK15b O, DIF Complementary clock output. A42 CLK15 O, DIF True clock output. A43 CLK16b O, DIF Complementary clock output. A44 CLK16 O, DIF True clock output. A45 CLK17b O, DIF Complementary clock output. A46 CLK17 O, DIF True clock output. A47 CLK18b O, DIF Complementary clock output. A48 CLK18 O, DIF True clock output. A49 CLK19b O, DIF Complementary clock output. A50 CLK19 O, DIF True clock output. A51 CLK20b O, DIF Complementary clock output. A52 CLK20 O, DIF True clock output. A53 CLK21b O, DIF Complementary clock output. A54 CLK21 O, DIF True clock output. A55 CLK22b O, DIF Complementary clock output. A56 CLK22 O, DIF True clock output. Interface. The function is this pin is controlled by the SBEN or SBI_ENQ pin. Refer to the Side-Band Interface (SBI) section for details. 0 = enable output, 1 = disable output. B3 VDDCLK PWR Clock Power supply. B4 VDDDIG PWR Digital Power supply. Decode table and the tri-level input thresholds in the electrical tables. B8 VDDCLK PWR Clock Power supply. B10 GND GND Connect to ground. Table 1. RC19024 Pin Descriptions (Cont.)

Interface. The function of this pin is controlled by the SBEN or SBI_ENQ pin. 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. B15 VDDCLK PWR Clock Power supply. 0 = enable output, 1 = disable output. 0 = enable output, 1 = disable output. B21 VDDCLK PWR Clock Power supply. 0 = enable output, 1 = disable output. B24 SBI_OUT O, SE Side-Band Interface data output. B27 VDDCLK PWR Clock Power supply. 0 = enable output, 1 = disable output. B33 VDDCLK PWR Clock Power supply. pin indicates a loss of signal on the input clock. B40 VDDCLK PWR Clock Power supply.

1.3 RC19020 Pin Information

1.3.1 RC19020 Pin Assignments

Figure 3. RC19020 80-VFQFPN – Top View 9QXL2001B NC pins (C2 and G11). B43 GND GND Connect to ground. N/A EPAD GND Connect Epad to ground.

1.3.2 RC19020 Pin Descriptions

Table 2. RC19020 Pin Descriptions A1 CLK17 O, DIF True clock output. A2 CLKb16 O, DIF Complementary clock output. A3 CLK16 O, DIF True clock output. A4 CLKb15 O, DIF Complementary clock output. A5 CLK15 O, DIF True clock output. A6 CLKb14 O, DIF Complementary clock output. A7 CLK14 O, DIF True clock output. A8 CLKb13 O, DIF Complementary clock output. A9 CLK13 O, DIF True clock output. A10 CLKb12 O, DIF Complementary clock output. A11 CLK12 O, DIF True clock output. A12 CLKb11 O, DIF Complementary clock output. B1 CLKb17 O, DIF Complementary clock output. B2 VDDCLK PWR Power supply for clock outputs. and the tri-level input thresholds in the electrical tables. B6 VDDCLK PWR Power supply for clock outputs. and the tri-level input thresholds in the electrical tables. Active low input for enabling output 12. 0 = enable output, 1 = disable output. B11 VDDCLK PWR Power supply for clock outputs. B12 CLK11 O, DIF True clock output. C1 CLK18 O, DIF True clock output. C2 SBI_OUT O, SE Side-Band Interface data output. Active low input for enabling output 11. 0 = enable output, 1 = disable output. C12 CLKb10 O, DIF Complementary clock output. D1 CLKb18 O, DIF Complementary clock output. D12 CLK10 O, DIF True clock output. E1 CLK19 O, DIF True clock output.

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins. Active low input for enabling output 10 or SHFT_LDb pin for the Side-Band Interface. information, see Side-Band Interface (SBI). 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. Active low input for enabling output 9. 0 = enable output, 1 = disable output. F1 CLKb19 O, DIF Complementary clock output. F12 CLKb9 O, DIF Complementary clock output. of signal on the input clock. G12 CLK9 O, DIF True clock output. PDT Complementary clock input. H2 VDDR PWR Power supply for clock input (receiver). Active low input for enabling output 8. 0 = enable output, 1 = disable output. H12 CLKb8 O, DIF Complementary clock output. J1 CLK0 O, DIF True clock output. J12 CLK8 O, DIF True clock output. K1 CLKb0 O, DIF Complementary clock output. Active low input for enabling output 7. 0 = enable output, 1 = disable output. K12 CLKb7 O, DIF Complementary clock output. L1 CLK1 O, DIF True clock output. L2 VDDCLK PWR Power supply for clock outputs. OD, PDT Data pin for SMBus interface. Table 2. RC19020 Pin Descriptions (Cont.)

PDT Clock pin of SMBus interface. 0 = Enable output, 1 = Disable output. 0 = Enable output, 1 = Disable output. Clocks data into the SBI shift register on the rising edge. L11 VDDCLK PWR Power supply for clock outputs. L12 CLK7 O, DIF True clock output. M1 CLKb1 O, DIF Complementary clock output. M2 CLK2 O, DIF True clock output. M3 CLKb2 O, DIF Complementary clock output. M4 CLK3 O, DIF True clock output. M5 CLKb3 O, DIF Complementary clock output. enters Power Down Mode, subsequent high assertions exit Power Down Mode. M7 CLK4 O, DIF True clock output. M8 CLKb4 O, DIF Complementary clock output. M9 CLK5 O, DIF True clock output. M10 CLKb5 O, DIF Complementary clock output. M11 CLK6 O, DIF True clock output. M12 CLKb6 O, DIF Complementary clock output. N/A EPAD GND Connect Epad to ground.

1.4 RC19020A072 Pin Information

1.4.1 RC19020A072 Pin Assignments

Figure 4. RC19020A072 72-VFQFPN – Top View placed on 9QXL2000 NC pins (5, 15 and 16).

1.4.2 RC19020A072 Pin Descriptions

Table 3. RC19020A072 Pin Descriptions 1 VDDCLK PWR Power supply for clock outputs. board may remain to support non-IDT DB2000Q devices. remain to support non-IDT DB2000Q devices. 5 SBI_OUT O, SE Side-Band Interface data output.

• 7 27 17 06 96 86 76 66 56 46 36 26 16 05 95 85 75 65 5 V DDCLK 1 54 OEb11 GND 2 53 CLKb11 rcomp_NC 3 52 CLK11 vdd_NC 4 51 OEb10_SHFT_LDb SBI_OUT 5 50 CLKb10 PWRGD_PWRDNb 6 49 CLK10 GND 7 48 OEb9 VD D R 8 47 CLKb9 CLKIN 9 46 CLK9 CLKINb 10 45 V DDCLK SADR_tri0 11 44 GND SDATA 12 43 OEb8 SCLK 13 42 CLKb8 SADR_tri1 14 41 CLK8 SBI_ENQ 15 40 OEb7 LOSb 16 39 CLKb7 CLKb19 17 38 CLK7 CLK19 18 37 OEb6_SBI_CLK 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36CLK0 CLKb0 VDDCLK CLK1 CLKb1 CLK2 CLKb2 GND CLK3 CLKb3 CLK4 CLKb4 VDDCLK CLK5 CLKb5 OEb5_SBI_IN CLK6 CLKb6 RC19020A072 10 x 10 mm, x 0.5mm pitch Top View connect EPAD to GND Note: Polarity of CLK19 is reversed from CLK[18:0] per DB2000Q Specification Rev1.2

6 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 8 VDDR PWR Power supply for clock input (receiver).

9 CLKIN I, DIF,

10 CLKINb I, DIF,

PDT Complementary clock input.

11 SADR_tri0 I, SE, PD,

and refer to the tri-level input thresholds in the electrical tables.

12 SDATA I/O, SE,

OD, PDT Data pin for SMBus interface.

13 SCLK I, SE,

PDT Clock pin of SMBus interface.

14 SADR_tri1 I, SE, PD,

and refer to the tri-level input thresholds in the electrical tables.

15 SBI_ENQ I, SE, PD,

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

16 LOSb O, OD,

of signal on the input clock. 17 CLKb19 O, DIF Complementary clock output. 18 CLK19 O, DIF True clock output. 19 CLK0 O, DIF True clock output. 20 CLKb0 O, DIF Complementary clock output. 21 VDDCLK PWR Power supply for clock outputs. 22 CLK1 O, DIF True clock output. 23 CLKb1 O, DIF Complementary clock output. 24 CLK2 O, DIF True clock output. 25 CLKb2 O, DIF Complementary clock output. 27 CLK3 O, DIF True clock output. 28 CLKb3 O, DIF Complementary clock output. 29 CLK4 O, DIF True clock output. 30 CLKb4 O, DIF Complementary clock output. 31 VDDCLK PWR Power supply for clock outputs. 32 CLK5 O, DIF True clock output. 33 CLKb5 O, DIF Complementary clock output. Table 3. RC19020A072 Pin Descriptions (Cont.)

34 OEb5_SBI_IN

Interface (SBI) section for details. 0 = enable output, 1 = disable output. 35 CLK6 O, DIF True clock output. 36 CLKb6 O, DIF Complementary clock output.

37 OEb6_SBI_CLK

Interface (SBI) section for details. 0 = enable output, 1 = disable output. Clocks data into the SBI shift register on the rising edge. 38 CLK7 O, DIF True clock output. 39 CLKb7 O, DIF Complementary clock output.

40 OEb7 I, SE,

Active low input for enabling output 7. 0 = enable output, 1 = disable output. 41 CLK8 O, DIF True clock output. 42 CLKb8 O, DIF Complementary clock output.

43 OEb8 I, SE,

Active low input for enabling output 8. 0 = enable output, 1 = disable output. 45 VDDCLK PWR Power supply for clock outputs. 46 CLK9 O, DIF True clock output. 47 CLKb9 O, DIF Complementary clock output.

48 OEb9 I, SE,

Active low input for enabling output 9. 0 = enable output, 1 = disable output. 49 CLK10 O, DIF True clock output. 50 CLKb10 O, DIF Complementary clock output.

51 OEb10_SHFT_LDb

Active low input for enabling output 10 or SHFT_LDb pin for the Side-Band Interface. Band Interface (SBI) section for details. 0 = enable output, 1 = disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 52 CLK11 O, DIF True clock output. 53 CLKb11 O, DIF Complementary clock output.

54 OEb11 I, SE,

Active low input for enabling output 11. 0 = enable output, 1 = disable output. 55 CLK12 O, DIF True clock output. 56 CLKb12 O, DIF Complementary clock output.

57 OEb12 I, SE,

Active low input for enabling output 12. 0 = enable output, 1 = disable output. 58 VDDCLK PWR Power supply for clock outputs.

59 CLK13 O, DIF True clock output. 60 CLKb13 O, DIF Complementary clock output. 61 CLK14 O, DIF True clock output. 62 CLKb14 O, DIF Complementary clock output. 64 CLK15 O, DIF True clock output. 65 CLKb15 O, DIF Complementary clock output. 66 CLK16 O, DIF True clock output. 67 CLKb16 O, DIF Complementary clock output. 68 VDDCLK PWR Power supply for clock outputs. 69 CLK17 O, DIF True clock output. 70 CLKb17 O, DIF Complementary clock output. 71 CLK18 O, DIF True clock output. 72 CLKb18 O, DIF Complementary clock output. 73 EPAD GND Connect EPAD to Ground.

1.5 RC19016 Pin Information

1.5.1 RC19016 Pin Assignments

Figure 5. RC19016 64-VFQFPN – Top View

1.5.2 RC19016 Pin Descriptions

Table 4. RC19016 Pin Descriptions

1 LOSb O, OD,

of signal on the input clock.

2 SLEWRATE_SEL I, SE, PU,

Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate.

3 SADR_tri1 I, SE, PD,

and the tri-level input thresholds in the electrical tables.

4 SADR_tri0 I, SE, PD,

and the tri-level input thresholds in the electrical tables.

5 SDATA I/O, SE,

OD Data pin for SMBus interface.

• 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LOSb 1 48 OEb5_SBI_CLK SLEWRA TE_SEL 2 47 CLKb5 SA DR_tri1 3 46 CLK5 SA DR_tri0 4 45 OEb6 SD ATA 5 44 VD D C LK SCLK 6 43 CLKb6 V DDDIG 7 42 CLK6 CLKIN 8 41 CLKb7 CLKINb 9 40 CLK7 OE b15 10 39 OEb7 OE b14 11 38 CLKb8 V DDCLK 12 37 CLK8 CLK15 13 36 OEb8 CLKb15 14 35 CLKb9 CLK14 15 34 CLK9 CLKb14 16 33 VDDCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32SBI_ENQ PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 CLK12 CLKb12 OEb12 CLK11 CLKb11 OEb11 CLK10 CLKb10 OEb10 OEb9_SBI_IN RC19016 64-VFQFPN top view connect EPAD to ground

6 SCLK I, SE Clock pin of SMBus interface. 8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input.

10 OEb15 I, SE, PU,

Active low input for enabling output 15. 0 = Enable output, 1 = Disable output.

11 OEb14 I, SE, PU,

Active low input for enabling output 14. 0 = Enable output, 1 = Disable output. 12 VDDCLK PWR Clock power supply. 13 CLK15 O, DIF True clock output. 14 CLKb15 O, DIF Complementary clock output. 15 CLK14 O, DIF True clock output. 16 CLKb14 O, DIF Complementary clock output.

17 SBI_ENQ I, SE, PD,

0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

18 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 19 VDDCLK PWR Clock power supply.

20 OEb13_SHFT_LDb

Active low input for enabling output 13 or SHFT_LDb pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 21 CLK13 O, DIF True clock output. 22 CLKb13 O, DIF Complementary clock output. 23 CLK12 O, DIF True clock output. 24 CLKb12 O, DIF Complementary clock output.

25 OEb12 I, SE, PU,

Active low input for enabling output 12. 0 = Enable output, 1 = Disable output. 26 CLK11 O, DIF True clock output. 27 CLKb11 O, DIF Complementary clock output.

28 OEb11 I, SE, PU,

Active low input for enabling output 11. 0 = Enable output, 1 = Disable output. 29 CLK10 O, DIF True clock output. 30 CLKb10 O, DIF Complementary clock output.

31 OEb10 I, SE, PU,

Active low input for enabling output 10. 0 = Enable output, 1 = Disable output. Table 4. RC19016 Pin Descriptions (Cont.)

32 OEb9_SBI_IN

0 = Enable output, 1 = Disable output. 33 VDDCLK PWR Clock Power supply. 34 CLK9 O, DIF True clock output. 35 CLKb9 O, DIF Complementary clock output.

36 OEb8 I, SE, PU,

Active low input for enabling output 8. 0 = Enable output, 1 = Disable output. 37 CLK8 O, DIF True clock output. 38 CLKb8 O, DIF Complementary clock output.

39 OEb7 I, SE, PU,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 40 CLK7 O, DIF True clock output. 41 CLKb7 O, DIF Complementary clock output. 42 CLK6 O, DIF True clock output. 43 CLKb6 O, DIF Complementary clock output. 44 VDDCLK PWR Clock Power supply.

45 OEb6 I, SE, PU,

Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 46 CLK5 O, DIF True clock output. 47 CLKb5 O, DIF Complementary clock output.

48 OEb5_SBI_CLK

0 = Enable output, 1 = Disable output. Clocks data into the SBI on the rising edge. 49 CLK4 O, DIF True clock output. 50 CLKb4 O, DIF Complementary clock output.

51 OEb4 I, SE, PU,

0 = Enable output, 1 = Disable output. 52 CLK3 O, DIF True clock output. 53 CLKb3 O, DIF Complementary clock output.

54 OEb3 I, SE, PU,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

55 OEb2_SBI_OUT

0 = Enable output, 1 = Disable output. SBI shift register data output. 56 CLK2 O, DIF True clock output.

1.6 RC19013 Pin Information

1.6.1 RC19013 Pin Assignments

Figure 6. RC19013 56-VFQFPN – Top View 57 CLKb2 O, DIF Complementary clock output. 58 VDDCLK PWR Clock Power supply. 59 CLK1 O, DIF True clock output. 60 CLKb1 O, DIF Complementary clock output.

61 OEb1 I, SE, PU,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 62 CLK0 O, DIF True clock output. 63 CLKb0 O, DIF Complementary clock output.

64 OEb0 I, SE, PU,

Active low input for enabling output 0. 0 = Enable output, 1 = Disable output.

• 56 55 54 53 52 51 50 49 48 47 46 45 44 43 LOSb 1 42 OEb6_SBI_CLK SLEWRA TE_SEL 2 41 V DDCLK SADR_tri1 3 40 CLKb6 SADR_tri0 4 39 CLK6 SDATA 5 38 CLKb7 SCLK 6 37 CLK7 V DDDIG 7 36 OEb7 CLKIN 8 35 CLKb8 CLKINb 9 34 CLK8 OEb14 10 33 OEb8 VDDCLK 11 32 CLKb9 CLK14 12 31 CLK9 CLKb14 13 30 V DDCLK SBI_ENQ 14 29 OEb9_SBI_IN 15 16 17 18 19 20 21 22 23 24 25 26 27 28PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 CLK12 CLKb12 OEb12 CLK11 CLKb11 OEb11 CLK10 CLKb10 OEb10 RC19013 Connect EPAD to ground Top view

1.6.2 RC19013 Pin Descriptions

Table 5. RC19013 Pin Descriptions of signal on the input clock. Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate. and the tri-level input thresholds in the electrical tables. and the tri-level input thresholds in the electrical tables. OD Data pin for SMBus interface. 6 SCLK I, SE Clock pin of SMBus interface. 8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input.

10 OEb14 I, SE, PU,

Active low input for enabling output 14. 0 = Enable output, 1 = Disable output. 11 VDDCLK PWR Clock power supply. 12 CLK14 O, DIF True clock output. 13 CLKb14 O, DIF Complementary clock output.

14 SBI_ENQ I, SE, PD,

Input that selects function of pins that are multiplexed between OE and SBI functionality. enabled. This pin must be strapped to its desired state. It cannot dynamically change. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

15 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 16 VDDCLK PWR Clock Power supply.

17 OEb13_SHFT_LDb

Active low input for enabling output 13 or SHFT_LDb pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 18 CLK13 O, DIF True clock output. 19 CLKb13 O, DIF Complementary clock output. 20 CLK12 O, DIF True clock output. 21 CLKb12 O, DIF Complementary clock output.

22 OEb12 I, SE, PU,

Active low input for enabling output 12. 0 = Enable output, 1 = Disable output. 23 CLK11 O, DIF True clock output. 24 CLKb11 O, DIF Complementary clock output.

25 OEb11 I, SE, PU,

Active low input for enabling output 11. 0 = Enable output, 1 = Disable output.

26 CLK10 O, DIF True clock output. 27 CLKb10 O, DIF Complementary clock output.

28 OEb10 I, SE, PU,

Active low input for enabling output 10. 0 = Enable output, 1 = Disable output.

29 OEb9_SBI_IN

0 = Enable output, 1 = Disable output. 30 VDDCLK PWR Clock power supply. 31 CLK9 O, DIF True clock output. 32 CLKb9 O, DIF Complementary clock output.

33 OEb8 I, SE, PU,

Active low input for enabling output 8. 0 = Enable output, 1 = Disable output. 34 CLK8 O, DIF True clock output. 35 CLKb8 O, DIF Complementary clock output.

36 OEb7 I, SE, PU,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 37 CLK7 O, DIF True clock output. 38 CLKb7 O, DIF Complementary clock output. 39 CLK6 O, DIF True clock output. 40 CLKb6 O, DIF Complementary clock output. 41 VDDCLK PWR Clock power supply.

42 OEb6_SBI_CLK

0 = Enable output, 1 = Disable output. Clocks data into the SBI shift register on the rising edge. 43 CLK3 O, DIF True clock output. 44 CLKb3 O, DIF Complementary clock output.

45 OEb3 I, SE, PU,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

46 OEb2_SBI_OUT

0 = Enable output, 1 = Disable output. SBI shift register data output. 47 CLK2 O, DIF True clock output. 48 CLKb2 O, DIF Complementary clock output. 49 VDDCLK PWR Clock power supply. 50 CLK1 O, DIF True clock output. Table 5. RC19013 Pin Descriptions (Cont.)

1.7 RC19008 Pin Information

1.7.1 RC19008 Pin Assignments

Figure 7. RC19008 40-VFQFPN – Top View

1.7.2 RC19008 Pin Descriptions

51 CLKb1 O, DIF Complementary clock output.

52 OEb1 I, SE, PU,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 53 CLK0 O, DIF True clock output. 54 CLKb0 O, DIF Complementary clock output.

55 OEb0 I, SE, PU,

Active low input for enabling output 0. 0 = Enable output, 1 = Disable output. 57 EPAD GND Connect Epad to ground. Table 6. RC19008 Pin Descriptions of signal on the input clock. Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate.

• 40 39 38 37 36 35 34 33 32 31 LOSb 13 0 OEb5_SBI_CLK SL EWRA TE_ SEL22 9 CLKb5 SADR_tri1 32 8 CLK5 SADR_tri0 42 7 OEb6 SDATA 52 6 V DDCLK SCLK 62 5 CLKb6 V DDDIG72 4 CLK6 CLKIN 82 3 CLKb7 CLKINb 92 2 CLK7 V DDCLK10 21 OEb7 11 12 13 14 15 16 17 18 19 20SBI_ENQ PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 CLK10 CLKb10 OEb10_SBI_IN VDDCLK RC19008 Connect EPAD to ground Top View

and tri-level input thresholds in the electrical tables. and tri-level input thresholds in the electrical tables. OD Data pin for SMBus interface. 6 SCLK I, SE Clock pin of SMBus interface. 8 CLKIN I, DIF True clock input. 9 CLKINb I, DIF Complementary clock input. 10 VDDCLK PWR Clock Power supply.

11 SBI_ENQ I, SE, PD,

Input that selects function of pins that are multiplexed between OE and SBI functionality. enabled. This pin must be strapped to its desired state. It cannot dynamically change. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

12 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 13 VDDCLK PWR Clock power supply.

14 OEb13_SHFT_LDb

Active low input for enabling output 13 or SHFT_LDb pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 15 CLK13 O, DIF True clock output. 16 CLKb13 O, DIF Complementary clock output. 17 CLK10 O, DIF True clock output. 18 CLKb10 O, DIF Complementary clock output.

19 OEb10_SBI_IN

0 = Enable output, 1 = Disable output. SBI shift-register data input. 20 VDDCLK PWR Clock power supply.

21 OEb7 I, SE, PU,

Active low input for enabling output 7. 0 = Enable output, 1 = Disable output. 22 CLK7 O, DIF True clock output. 23 CLKb7 O, DIF Complementary clock output. 24 CLK6 O, DIF True clock output. 25 CLKb6 O, DIF Complementary clock output. 26 VDDCLK PWR Clock Power supply. Table 6. RC19008 Pin Descriptions (Cont.)

27 OEb6 I, SE, PU,

Active low input for enabling output 6. 0 = Enable output, 1 = Disable output. 28 CLK5 O, DIF True clock output. 29 CLKb5 O, DIF Complementary clock output.

30 OEb5_SBI_CLK

0 = Enable output, 1 = Disable output. Clocks data into the SBI on the rising edge. 31 CLK3 O, DIF True clock output. 32 CLKb3 O, DIF Complementary clock output.

33 OEb3 I, SE, PU,

Active low input for enabling output 3. 0 = Enable output, 1 = Disable output.

34 OEb2_SBI_OUT

0 = Enable output, 1 = Disable output. SBI shift register data output. 35 CLK2 O, DIF True clock output. 36 CLKb2 O, DIF Complementary clock output. 37 VDDCLK PWR Clock power supply. 38 CLK1 O, DIF True clock output. 39 CLKb1 O, DIF Complementary clock output.

40 OEb1 I, SE, PU,

Active low input for enabling output 1. 0 = Enable output, 1 = Disable output. 41 EPAD GND Connect Epad to ground.

1.8 RC19004 Pin Information

1.8.1 RC19004 Pin Assignments

Figure 8. RC19004 28-VFQFPN – Top View

1.8.2 RC19004 Pin Descriptions

Table 7. RC19004 Pin Descriptions

1 SADR_tri1 I, SE, PD,

and the tri-level input thresholds in the electrical tables.

2 SADR_tri0 I, SE, PD,

and the tri-level input thresholds in the electrical tables.

3 SDATA I/O, SE,

OD Data pin for SMBus interface. 4 SCLK I, SE Clock pin of SMBus interface. 6 CLKIN I, DIF True clock input. 7 CLKINb I, DIF Complementary clock input.

8 SBI_ENQ I, SE, PD,

Input that selects function of pins that are multiplexed between OE and SBI functionality. enabled. This pin must be strapped to its desired state. It cannot dynamically change. 0 = SBI is disabled. Multiplexed pins function as output enables. 1 = SBI is enabled. Multiplexed pins function as SBI control pins.

9 PWRGD_PWRDNb I, SE, PU,

enters Power Down Mode, subsequent high assertions exit Power Down Mode. 10 VDDCLK PWR Clock power supply.

• 28 27 26 25 24 23 22 SA DR_tri1 1 21 OEb5_SBI_CLK SA DR_tri0 2 20 CLKb5 SDATA 3 19 CLK5 SCLK 4 18 V DDCLK V DDDIG 5 17 CLKb9 CLKIN 6 16 CLK9 CLKINb7 15 V DDCLK 8 9 10 11 12 13 14SBI_ENQ PWRGD_PWRDNb VDDCLK OEb13_SHFT_LDb CLK13 CLKb13 OEb9_SBI_IN RC19004 Connect epad to ground Top view

11 OEb13_SHFT_LDb I, SE, PU,

Active low input for enabling output 13 or SHFT_LDb pin for the Side-Band Interface. 0 = Enable output, 1 = Disable output. 0 = Disable SBI shift register, 1 = Enable SBI shift register. A falling edge transfers SBI shift register contents to SBI output control register. 12 CLK13 O, DIF True clock output. 13 CLKb13 O, DIF Complementary clock output.

14 OEb9_SBI_IN

0 = Enable output, 1 = Disable output. 15 VDDCLK PWR Clock power supply. 16 CLK9 O, DIF True clock output. 17 CLKb9 O, DIF Complementary clock output. 18 VDDCLK PWR Clock power supply. 19 CLK5 O, DIF True clock output. 20 CLKb5 O, DIF Complementary clock output.

21 OEb5_SBI_CLK

0 = Enable output, 1 = Disable output. Clocks data into the SBI on the rising edge.

22 OEb2_SBI_OUT

0 = Enable output, 1 = Disable output. SBI shift register data output. 23 CLK2 O, DIF True clock output. 24 CLKb2 O, DIF Complementary clock output. 25 VDDCLK PWR Clock power supply.

27 SLEWRATE_SEL I, SE, PU,

Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 = Fast Slew Rate.

28 LOSb O, OD,

of signal on the input clock. 29 EPAD GND Connect to ground. Table 7. RC19004 Pin Descriptions (Cont.)

1.9 RC19002 Pin Information

1.9.1 RC19002 Pin Assignments

Figure 9. RC19002 20-VFQFPN – Top View

1.9.2 RC19002 Pin Descriptions

Table 8. RC19002 Pin Descriptions 1 CLKIN0 I, DIF, PDT True clock input. 2 CLKINb0 I, DIF, PDT Complementary clock input. 3 VDDCLK PWR Clock power supply.

4 NC NC No connect

5 NC NC No connect

6 VDDCLK/DNC PWR/DNC

the pin unconnected, do not connect any traces – there must be no stubs.

7 GND/DNC GND/DNC

by removing any external pull-down resistor and any board trace must be removed. leaving the pin unconnected, do not connect any traces, there must be no stubs. 8 VDDCLK PWR Clock power supply. 9 CLK10 O, DIF True clock output. 10 CLKb10 O, DIF Complementary clock output. 11 ZOUTSEL I, SE, PD Input to select differential output impedance.

12 OEb10 I, SE, PU,

Active low input for enabling output 10. 1 = disable output, 0 = enable output.

13 LOSb O, OD,

of signal on the input clock. 14 VDDCLK PWR Clock power supply.

15 OEb5 I, SE, PU,

Active low input for enabling output 5. 1 = disable output, 0 = enable output.

• 20 19 18 17 16 CLKIN0 1 15 OEb5 CLKINb0 2 14 V DDCLK V DDCLK 3 13 LOSb NC 4 12 OEb10 NC 5 11 ZOUTSE L 6789 1 0VDDCLK/DNC GND/NC VDDCLK CLK10 CLKb10 RC19002 Connect to EP AD to GND. Top View .

16 CLK5 O, DIF True clock output. 17 CLKb5 O, DIF Complementary clock output. 18 VDDCLK PWR Clock power supply. 19 VDDDIG PWR Digital power. 20 GNDSUB GND Ground pin for substrate. 21 EPAD GND Connect to ground. Table 8. RC19002 Pin Descriptions (Cont.)

2.1 Absolute Maximum Ratings

2.2 Recommended Operating Conditions

2.3 Thermal Specifications

Table 9. Absolute Maximum Ratings

1. Pins designated Power Down Tolerant (PDT) in the pin description tables.
2. Pins not designated Power Down Tolerant (PDT) in the pin description tables.

Table 10. Recommended Operating Conditions Table 11. Thermal Specifications

Table 11. Thermal Specifications (Cont.)

2.4 Electrical Specifications

2.4.1 Phase Jitter

Table 12. PCIe Refclk Phase Jitter - Normal Conditions [1][2][3]

1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0, Revision 0.7. For the exact
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate

the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83.

1. Differential input swing ≥ 1600mV and input slew rate ≥ 3.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for

PCIe Gen1) must be less than the jitter specification listed.

1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
2. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
5. Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.

1. The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

this more relaxed value as the jitter limit. Table 13. PCIe Refclk Phase Jitter - Degraded Conditions [1][2][3]

1. The Refclk jitter is measured after applying the filter functions found in the PCI Express Base Specification 7.0, Revision 0.7. For the exact
2. Jitter measurements should be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate

the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83.

1. Differential input swing ≥ 800mV and input slew rate ≥ 1.5V/ns. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe

Gen1) must be less than the jitter specification listed.

1. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
2. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
3. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
4. Note that 0.15ps RMS is to be used in channel simulations to account for additional noise in a real system.
5. Note that 0.10ps RMS is to be used in channel simulations to account for additional noise in a real system.
6. The PCI Express Base Specification 7.0 provides the filters necessary to calculate SRIS jitter values; it does not provide specification

this more relaxed value as the jitter limit.

2.4.2 Output Frequencies, Startup Time, and LOS Timing

Table 14. Non-PCIe Refclk Phase Jitter [1][2][3]

1. See Test Loads for test configuration.
2. SMA100B used as signal source.
3. The RC19xxx devices meet all legacy QPI/UPI specifications by meeting the PCIe and DB2000Q specifications listed in this document.
4. Differential input swing = 1,600mV and input slew rate = 3.5V/ns.
5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.
6. Differential input swing = 800mV and input slew rate = 1.5V/ns.

Table 15. Output Frequencies, Startup Time, and LOS Timing

1. Measured from when all power supplies have reached > 90% of nominal voltage to the first stable clock edge on the output.

PWRGD_PWRDNb tied to VDD in this case.

1. VDD stable, measured from de-assertion of PWRGD_PWRDNb.
2. The clock detect circuit does not qualify the accuracy of the input clock. The first input clock must appear to release the power on reset

and enable the LOS circuit at power up.

1. PWRGD_PWRDNb high. The Automatic Clock Parking (ACP) circuit - if enabled - will park the outputs in a low/low state within this time. See

Byte4, bit 4 LOSb_ACP_ENABLE.

1. PWRGD_PWRDNb high. The device will drive the outputs to a high/low state within this time and then begin clocking the outputs.

2.4.3 RC1902xA CLK AC/DC Output Characteristics

The tables in this section apply to the RC19024, RC19020 and RC19020A072. Table 16. RC1902xA 85-ohm CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe [1]

1. Standard high impedance load with C L = 2pF. See Test Loads.
2. The specification limits are taken from either the PCIe Base Specification, Revision 7.0 or from relevant x86 processor specifications, whichever
3. Measured from single-ended waveform.
4. Defined as the maximum instantaneous voltage including overshoot.
5. Defined as the minimum instantaneous voltage including undershoot.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
9. Measured from differential waveform.

1. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 17. RC1902xA 85Ω CLK AC/DC Characteristics - Non-PCIe, Source-Terminated Loads [1]

1. Standard high impedance load with C L = 2pF. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 18. RC1902xA 85Ω CLK AC/DC Characteristics - Non-PCIe, Double-Terminated Loads[1]

2.4.4 RC1901xA/RC1900xA CLK AC/DC Output Characteristics

1. Both Tx and Rx are terminated (double-terminated) with C L = 2pF. This reduces amplitude by 50%. See Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 19. RC1901xA/RC1900xA 85Ω CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe Applications [1] Table 18. RC1902xA 85Ω CLK AC/DC Characteristics - Non-PCIe, Double-Terminated Loads (Cont.)[1]

1. Standard high impedance load with C L= 2pF. For more information, see Test Loads.
2. The specification limits are taken from either the PCIe Base Specification, Revision 7.0 or from relevant x86 processor specifications, whichever
3. Measured from single-ended waveform.
4. Defined as the maximum instantaneous voltage including overshoot.
5. Defined as the minimum instantaneous voltage including undershoot.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
9. Measured from differential waveform.
10. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 20. RC1901xA\\RC1900xA 100Ω CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe Apps [1]

1. Standard high impedance load with C L= 2pF. For more information, see Test Loads.
2. The specification limits are taken from either the PCIe Base Specification, Revision 7.0 or from relevant x86 processor specifications, whichever
3. Measured from single-ended waveform.
4. Defined as the maximum instantaneous voltage including overshoot.
5. Defined as the minimum instantaneous voltage including undershoot.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS
9. Measured from differential waveform.
10. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

1. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the

the maximum allowed difference should not exceed 20% of the slowest edge rate. Table 20. RC1901xA\\RC1900xA 100Ω CLK AC/DC Characteristics - Source-Terminated 100MHz PCIe Apps [1] (Cont.)

Table 21. RC1901xA/RC1900xA 85Ω CLK AC/DC Characteristics - Non-PCIe Apps, Source-Terminated Loads [1]

1. Standard high impedance load with C L= 2pF. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 22. RC1901xA/RC1900xA 85Ω CLK AC/DC Characteristics - Non-PCIe Apps, Double-Terminated Loads [1]

1. Both Tx and Rx are terminated (double-terminated) with C L= 2pF. This reduces amplitude by 50%. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 23. RC1901xA/RC1900xA 100Ω CLK AC/DC Characteristics - Non-PCIe Apps, Source-Terminated Loads [1]

1. Standard high impedance load with C L= 2pF. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

2.4.5 Output-to-Output and Input-to-Output Skew

Table 24. RC1901xA/RC1900xA 100Ω CLK AC/DC Characteristics–Non-PCIe Apps, Double-Terminated Loads [1]

1. Both Tx and Rx are terminated (double-terminated) with C L= 2pF. This reduces amplitude by 50%. For more information, see Test Loads.
2. Measured from single-ended waveform.
3. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLKb.
4. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for
5. Defined as the total variation of all crossing voltages of Rising CLK and Falling CLKb. This is the maximum allowed variance in VCROSS for any
6. Measured from differential waveform.

Table 25. RC1902xA Output-to-Output and Input-to-Output Skew [1]

1. For more information, see Test Loads.
2. This parameter is defined in accordance with JEDEC Standard 65.
3. Defined as the time between to output rising edge and the input rising edge that caused it.

2.4.6 I/O Signals

Table 26. RC1901xA/RC1900xA Output-to-Output and Input-to-Output Skew [1]

1. For more information, see Test Loads.
2. This parameter is defined in accordance with JEDEC Standard 65.
3. Defined as the time between to output rising edge and the input rising edge that caused it.

Table 27. I/O Electrical Characteristics Single-ended inputs, unless otherwise listed.

2.4.7 Power Supply Current

1. For SCLK and SDATA, see the SMBus Electrical Characteristics table.
2. These values are compliant with JESD8C.01.
3. Measured at V CROSS (abs). Target values are 85Ω ±20% (64Ω to 102Ω) or 100Ω ±20% (80Ω to 120Ω).

Table 28. Power Supply Current [1][2][3] terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. Table 27. I/O Electrical Characteristics (Cont.)

terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. Table 28. Power Supply Current [1][2][3] (Cont.)

terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency. terminated load at maximum output frequency.

terminated load at maximum output frequency. terminated load at maximum output frequency.

1. For more information, see Test Loads.
2. Output voltage set to 800mV. Slew rate has negligible effect on current consumption, so only fast is listed.
3. Total operating current is obtained by adding IDDCLK + IDDDIG, or IDDCLK + IDDR for a particular device and operating mode. Power down

current is obtained by adding IDDCLK_PD + IDDDIG_PD, or IDDCLK_PD + IDDR_PD for a particular device.

2.4.8 CLKIN AC/DC Characteristics

Figure 10. Clock Input Bias Network

2.4.9 SMBus Electrical Characteristics

This section applies to all devices except the RC19002 because the RC19002 does not have an SMBus interface. Figure 11. SMBus Target Timing Diagram Table 29. CLKIN AC/DC Characteristic

1. For values required for performance, see the Phase Jitter tables.
2. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero-crossing. Table 30. SMBus DC Electrical Characteristics [1]

1. V OH is governed by the VPUP, the voltage rail to which the pull-up resistors are connected.
2. For more information, see I/O Electrical Characteristics.

Table 31. SMBus AC Electrical Characteristics

1. Power must be applied and PWRGD_PWRDNb must be a 1 for the SMBus to be active.
2. A host should not drive the clock at a frequency below the minimum fSMB. Further, the operating clock frequency should not be reduced below the

so forth for longer than 100 µs in a non-periodic way.

1. A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the VIH,MIN of the SMBCLK signal) to bridge the

undefined region of the falling edge of SMBCLK.

1. Target devices may have caused other target devices to hold SDA low. This is the maximum time that a device can hold SMBDAT low after the
2. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of

than tTIMEOUT,MAX. Typical device examples include the host controller, and embedded controller, and most devices that can master the SMBus. a stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds the SMBCLK low for tTIMEOUT,MAX or longer.

1. The device has the option of detecting a timeout if the SMBDATA pin is also low for this time.
2. t HIGH,MAX provides a simple guaranteed method for hosts to detect bus idle conditions. A host can assume that the bus is free if it detects that the

clock and data signals have been high for greater than tHIGH,MAX.

1. tLOW:MEXT is the cumulative time a host device is allowed to extend its clock cycles within each byte of a message as defined from START-to-

time to be greater than tLOW:MEXT on a given byte. This parameter is measured with a full-speed target device as the sole target of the host.

1. The rise and fall time measurement limits are defined as follows:
2. Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

2.4.10 Side-Band Interface

Figure 12. Side-Band Interface Timing Figure 12 is the timing diagram and Table 32 provides the electrical characteristics for the Side-Band Interface. The SBI supports clock rates up to 25MHz. Table 32. Electrical Characteristics – Side-Band Interface

1. Refers to the output clock.
2. Control input must be monotonic from 20% to 80% of input swing.

Current O/P Config. Next O/P Config.

Figure 15. Test Load for PCIe Phase Jitter Measurements Table 35. Parameters for PCIe Gen5 Jitter Measurement

1. PCIe Gen6 specifies L = 0cm for 32 and 64 GT/s. L = 25.4cm is more conservative.

R31DS0016EU0128 Rev.1.28 Page 53 Nov 5, 2025 RC190xx Datasheet 4. General SMBus Serial Interface Information This section applies to all device except the RC19002 which does not have an SMBus interface.

4.1 How to Write

▪ Controller (host) sends a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) sends the byte count = X ▪ Renesas clock will acknowledge ▪ Controller (host) starts sending Byte N through Byte N+X-1 ▪ Renesas clock will acknowledge each byte one at a time ▪ Controller (host) sends a stop bit Index Block Write Operation Controller (Host) Renesas (Target/Receiver) T starT bit Target Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK P stoP bit

R31DS0016EU0128 Rev.1.28 Page 54 Nov 5, 2025 RC190xx Datasheet

4.2 How to Read

▪ Controller (host) will send a start bit ▪ Controller (host) sends the write address ▪ Renesas clock will acknowledge ▪ Controller (host) sends the beginning byte Location = N ▪ Renesas clock will acknowledge ▪ Controller (host) will send a separate start bit ▪ Controller (host) sends the read address ▪ Renesas clock will acknowledge ▪ Renesas clock will send the data byte count = X ▪ Renesas clock sends Byte N+X-1 ▪ Renesas clock sends Byte L through Byte X (if X(H) was written to Byte 7) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit Index Block Read Operation Controller (Host) Renesas (Target/Receiver) T starT bit Target Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Target Address RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not acknowledge P stoP bit

R31DS0016EU0128 Rev.1.28 Page 55 Nov 5, 2025 RC190xx Datasheet

4.3 SMBus Bit Types

4.4 Write Lock Functionality

4.5 SMBus Address Decode

Bit Description Definition RO Read-only RW Read-write RW1C Read/Write ‘1’ to clear RESERVED Undefined do not write WRITE_LOCK WRITE_LOCK RW1C SMBus Write Protect 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes Address Selection Binary Value Hex Value SADR_tri1 SADR_tri0 7 6 5 4 3 2 1 Rd/Wrt 0 1 1 0 1 1 0 0 0 D8 M 1 1 0 1 1 0 1 0 DA 1 1 1 0 1 1 1 1 0 DE M 0 1 1 0 0 0 0 1 0 C2 M 1 1 0 0 0 1 0 0 C4 1 1 1 0 0 0 1 1 0 C6 0 1 1 0 0 1 0 1 0 CA M 1 1 0 0 1 1 0 0 CC 1 1 1 0 0 1 1 1 0 CE

4.6 RC19024 SMBus Registers

Table 36. RC19024 SMBus Registers

0 OUTPUT_ENABLE_0

1 OUTPUT_ENABLE_1

2 OUTPUT_ENABLE_2

3 OEb_PIN_READBACK

4 SBEN_RDBK_

5 VENDOR_REVISION_ID

6 DEVICE_ID DEVICE_ID [7:0] RO 0x18 Device ID -

7 BYTE_COUNT

8 SBI_MASK_0

9 SBI_MASK_1

Table 36. RC19024 SMBus Registers (Cont.)

10 SBI_MASK_2

11 SBI_READBACK_0 [1]

12 SBI_READBACK_1 [1]

13 SBI_READBACK_2 [1]

14 OEb_ASSIGNMENT_0

15 OEb_ASSIGNMENT_1

16 OEb_ASSIGNMENT_2

17 LPHCSL_AMP_CTRL

18 PD_RESTORE_LOSb

19 Reserved RESERVED [7:0] RW 0x07 RESERVED -

20 OUTPUT_SLEW_

21 OUTPUT_SLEW_

22 OUTPUT_SLEW_

38 WRITE_LOCK_NCLEAR

39 WRITE_LOCK_CLEAR_

1. Register only valid when the Side-Band Interface is enabled (SBI_ENQ = 1).

4.7 RC19020 SMBus Registers

Table 37. RC19020 SMBus Registers

0 OUTPUT_ENABLE_2

1 OUTPUT_ENABLE_0

2 OUTPUT_ENABLE_1

6 DEVICE_ID DEVICE_ID [7:0] RO 0xC9 Device ID -

Table 37. RC19020 SMBus Registers (Cont.)

11 OUTPUT_SLEW_

12 OUTPUT_SLEW_

13 OUTPUT_SLEW_

20 LPHCSL_AMP_CTRL

21 PD_RESTORE_LOSb

33 SBI_READBACK_0 [1]

34 SBI_READBACK_1 [1]

35 SBI_READBACK_2 [1]

1. Register only valid when the Side-Band Interface is enabled (SBI_ENQ = 1).

4.8 RC19020A072 SMBus Registers

Table 38. RC19020A072 SMBus Registers

6 DEVICE_ID DEVICE_ID [7:0] RO 0xC8 Device ID -

8 OEb_Configuration_A

9 OEb_Configuration_B

10 OEb_Configuration_C_

Table 38. RC19020A072 SMBus Registers (Cont.)

22 SBI_MASK_0 [2]

23 SBI_MASK_1 [2]

24 SBI_MASK_2 [2]

33 SBI_READBACK_0 [2]

34 SBI_READBACK_1 [2]

35 SBI_READBACK_2 [2]

4.9 RC19016/013/008/004 SMBus Registers

1. Register is only valid when the Side-Band Interface is not enabled (SBI_ENQ = 0).
2. Register only valid when the Side-Band Interface is enabled (SBI_ENQ = 1).

Table 39. RC19016/013/008/004 SMBus Registers

2 OEb_PIN_READBACK_0

3 OEb_PIN_READBACK_1

5 VENDOR_REVISION_

6 DEVICE_ID DEVICE_ID [7:0] RO 0x18

Table 39. RC19016/013/008/004 SMBus Registers (Cont.)

10 RESERVED Reserved [7:0] - - - -

18 PD_RESTORE_LOSb_

19 RESERVED Reserved [7:0] - - - -

37 Reserved Reserved [7:0] - - - -

38 WRITE_LOCK_

39 WRITE_LOCK_

be cleared by writing a 1 to it.

5.1 Inputs, Outputs, and Output Enable Control

5.1.1 Recommendations for Unused Inputs and Outputs

5.1.1.1 Unused Differential CLKIN Inputs

floating input clock condition.

5.1.1.2 Unused Single-ended Control Inputs

change the pin state or are desired for design robustness, 10kohm is the recommended value.

5.1.1.3 Unused Differential CLK Outputs

5.1.1.4 Unused SMBus Clock and Data Pins

may be used for debug, separate resistors should be used. 10kohm is the recommended value.

5.1.2 Differential CLKIN Configurations

This feature is enabled by the AC_IN bit. ▪ Internal pull-down resistors (Rp) to terminate the clock input at the receiver. This feature is enabled by the Rx_TERM bit. and transmission line length vary from the 100MHz PCIe standard. Figure 16 through Figure 19 illustrate the above items. Figure 16. HCSL Input Levels (PCIe Standard) Figure 17. LVDS Input Levels

5.1.3 Differential CLK Output Configurations

5.1.3.1 Direct-Coupled HCSL Loads

5.1.3.2 AC-Coupled non-HCSL Loads

terminating the RC19xxx CLK outputs to other logic families such as LVDS, LVPECL, or CML, see AN-891. Figure 20 to Figure 22 show the various CLK output configurations. Figure 20. Direct-Coupled Source-Terminated HCSL Figure 21. Direct-Coupled Double-Terminated HCSL Figure 22. AC-Coupled Figure 18. External AC-Coupling Figure 19. Receiver Termination

5.2 Power Down Tolerant Pins

before it has received power. Figure 23 provides an example of a PDT call-out in a data sheet.

5.3 Flexible Startup Sequencing

Figure 23. Example: Power Down Tolerant Pin Descriptions CLKIN running before VDD is applied, and can have VDD applied and sit for extended periods with no input clock.

5.4 Loss of Signal and Automatic Clock Parking

the LOS_EVT bit in the SMBus register space. There are two slightly different LOSb pin behaviors at power up. differentially in Figure 24 and Figure 25. Table 40. Flexible Startup Sequences

Figure 24. LOSb De-assert Timing, RC19004, RC19008, RC1901x, RC19024 after power up. So, the LOSb pin will be high until the first clock edge after power up. Figure 25. LOSb De-assert Timing RC19002, RC19020 Devices Figure 26. LOSb Assert Timing

5.5 Output Enable Control

when all three mechanisms indicate “enabled.” The following sections describe the three mechanisms.

5.5.1 SMBus Output Enable Bits

This section does not apply to the RC19002 because it does not have an SMBus. between the enable and disable states are glitch-free in both directions.

5.5.2 Output Enable (OEb) Pins

low/low state. All OEb pins enable and disable the controlled outputs in a glitch-free, synchronous manner.

5.5.3 RC19024/020 Clock Buffer OEb Pins

outputs, and defaults to controlling one output. The RC19024 output enable mapping is described in Table 41. The RC19020 and the RC19020A072 each have 8 OEb pins. Some of the pins are muxed with SBI functions. Table 41. RC19024 OEb Mapping

1. See the OEb_ASSIGNMENT registers in Table 36.

Table 42. RC19020 OEb Mapping

used for the SBI interface when SBI_ENQ = 1 (for more information, see Table 44). The RC19002 has single function dedicated OEb pins. For more information, see Figure 9. Table 43. RC19020A072 OEb Mapping[1]

1. See the OEb_ASSIGNMENT registers in Table 38.

Table 44. RC19016, RC19013, RC19008, RC19004 Buffer OEb Mapping Table 42. RC19020 OEb Mapping (Cont.)

5.5.4 Side-Band Interface (SBI)

This section does not apply to the RC19002 because it does not have a side-band interface. individual clock output. As buffers grow in output count, dedicated OEb pins become problematic for two reasons. First, the clock buffer pin count becomes much larger than it otherwise would be, resulting in a larger package. outgrows the GPIO pins of an FPGA or micro-controller. simple 3-wire (4-wire if the SBI_OUT pin is used) interface that can control all outputs across multiple devices. pins per output. It is protocol-free, hardware-oriented and runs at speeds up to 25MHz, much faster than SMBus. device operation. The SBI can make the adjustments much more rapidly than SMBus. interface. The exact pins that are multiplexed vary with device (for more information, see Table 44). PWRGD_PWRDNb to 1. Because of this, the SBI_ENQ must be static and cannot change once power is applied. If SBI_ENQ is 0 when power is applied, the SBI is disabled and has no impact on enabling or disabling outputs. an output and a 0 disables an output. All shift-register bits default to 1 at power up, indicating an enabled state. This means that the SBI can be used to disable outputs at power up because the default is enabled. Table 44. RC19016, RC19013, RC19008, RC19004 Buffer OEb Mapping (Cont.)

enabling or disabling clock outputs. turning off a critical output. using the SMBus; the SMBus cannot be used to load it. Figure 27 shows the high-level functional description of SBI. Figure 27. Side-band Interface High-Level Functional Diagram (RC19024 shown)

5.5.4.1 Using the SBI

Byte 2 bit 7. The last bit shifted in would be the output enable/disable for CLK0, which is in Byte 0, bit 0.

Figure 31. RC19013 Side-Band Shift Order Figure 32. RC19008 Side-Band Shift Order Figure 33. RC19004 Side-Band Shift Order

5.5.4.2 Side-Band Interface Timing

Characteristics, see Table 32.

Figure 34. Side-Band Interface Functional Timing

5.5.4.3 Side-Band Interface Connection Topologies

any activity on the SBI_CLK and SBI_IN pins. controlled at the cost of an additional GPIO per device. Figure 35. Side-Band Interface Star Topology controller. It uses the SBI_OUT pin of one device to drive the SBI_IN pin of the next device in the daisy chain.

the SBI bit stream consists of 48 bits. Figure 36. Side-Band Interface Daisy-Chain Topology

5.5.5 Output Enable/Disable Priority

order for the output to be enabled. A logical representation of the priority logic is shown in Figure 37. Figure 37. Output Enable/Disable Priority (Logical)

5.6 PCB Layout Recommendations

Buffer-Mux Layout Recommendations Application Note. available and is subject to change without revision of this document.

R31DS0016EU0128 Rev.1.28 Page 89 Nov 5, 2025 RC190xx Datasheet 7. Marking Diagrams

7.1 RC1901xA/RC1900xA Marking Diagrams

▪ Lines 1 and 2: part number. ▪ Line 3:

• “#” indicates stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled.
• “$” indicates the mark code. ▪ Lines 1 and 2 (for 85Ω); 1, 2, and 3 (for 100Ω): part number. ▪ Line 3 (for 85Ω) or 4 (for 100Ω):
• “#” indicates stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled. ▪ “$” indicates the mark code. ▪ Lines 1 and 2: part number. ▪ Line 3:
• “#” indicates stepping number.
• “YYWW” indicates the last two digits of the year and work week the part was assembled. ▪ “$” indicates the mark code. ▪ Line 1: truncated part number. ▪ Line 2:
• “YYWW” indicates the last two digits of the year and work week the part was assembled. ▪ “$” indicates the mark code. RC19016A 64-VFQFPN 85Ω RC19016A 64-VFQFPN 100Ω RC19013A 56-VFQFPN 85Ω RC19013A 56-VFQFPN 100Ω RC19008A 40-VFQFPN 85Ω RC19008A 40-VFQFPN 100Ω RC19004A 28-VFQFPN 85Ω RC19004A 28-VFQFPN 100Ω ▪ Line 1 is the part number ▪ Line 2 “A” is part of the part number and “***” is the sequential code ▪ Line 3:
• “$” denotes the mark location code.
• “YWW” denotes the assembly date: “Y” is the last digit of the year and “WW” are the last two digits of work week. RC19002A 20-VFQFPN

R31DS0016EU0128 Rev.1.28 Page 90 Nov 5, 2025 RC190xx Datasheet

7.2 RC1902xA Marking Diagrams

▪ Lines 2 and 3: part number ▪ Line 4:

• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. ▪ “LOT” denotes the lot number
• “COO” denotes country of origin. ▪ Lines 2: part number ▪ Line 3:
• $” denotes the mark code.
• “#” denotes the stepping number.
• “YWW” denotes the last digit of the year and the work week the part was assembled. RC19024A 100-VFQFPN 85Ω RC19020A 80-VFQFPN 85Ω ▪ Lines 2 and 3: part number ▪ Line 4:
• “#” denotes the stepping number.
• “YYWW” denotes the last two digits of the year and the work week the part was assembled.
• “$” denotes the mark code. ▪ “LOT” denotes the lot number
• “COO” denotes country of origin.RC19020A072 72-VFQFPN 85Ω

Table 45. Ordering Information

R31DS0016EU0128 Rev.1.28 Page 92 Nov 5, 2025 RC190xx Datasheet 9. Revision History Revision Date Description

1.28 Nov 5, 2025

▪ Deleted non-applicable parameter description information from Table 12 and Table 13 ▪ Changed references to PCIe Base Specification, Revision 6.0 to PCIe Base Specification, Revision 7.0 ▪ Replaced SMBus “master/target” terminology with “host/target”

1.26 Jun 27, 2025 Added PCB Layout Recommendations

1.25 Jun 16, 2025 Updated footnote 3 in Table 13

1.24 May 12, 2025 Updated Figure 32

1.23 Mar 28, 2025 Changed the Pin Type for pin M6 in Table 2

1.22 Jan 14, 2025 Updated Output Impedance parameter for CLK outputs in Table 27

1.21 Nov 5, 2024 ▪ Added PCIe Gen7 specifications to Table 12 and Table 13

▪ Updated front page text.

1.20 Oct 2, 2024

▪ Updated the Type and Description for pin 55 in Table 4 ▪ Updated the Type and Description for pin 46 in Table 5 ▪ Updated the Type and Description for pin 34 in Table 6 ▪ Updated the Type and Description for pin 11, 14, 21, and 22 in Table 7 1.19 Jul 30, 2024 ▪ Updated references to the 6 x 6 package to 80-VFQFPN. No technical changes were made

1.18 Nov 1, 2023 ▪ Changed the description of “O” to Output in Signal Types

1.17 Oct 25, 2023 ▪ Updated RC19002 pin descriptions for pins 6 and 7 in Table 8

1.16 Sep 12, 2023 ▪ Updated the RC19020AGN6 marking diagram (see RC1902xA Marking Diagrams)

1.15 Jul 25, 2023

▪ Updated descriptive text for Figure 25 in section 5.4 ▪ Updated part number to RC190xxA from RC19xxxA in section 5.5.4.3 ▪ Updated Figure 36

1.14 Jun 29, 2023

▪ Updated RC19002 Pin Information for pins 3, 6, 7, and 8 ▪ Updated various device specifications:

• V MAX, VMIN, VLOW, and ΔTR/F in Table 20
• V OL and tDC in Table 21
• V OH, VOL, VCROSS, and ΔVCROSS, tF in Table 22
• V OH, VCROSS, tR, and tDC in Table 23
• V OL, VCROSS, ΔVCROSS, ΔVCROSS, and tR in Table 24
• V OH, VOL, VCROSS, ΔVCROSS, tR, tF in Table 25
• Added V DDCLK Operating Current 100Ω impedance values for RC19002 in Table 28 ▪ Completed other minor changes

1.13 Jun 2, 2023

▪ Added missing slew rate control bytes 20 and 21 to Table 39 ▪ Renamed various tables to list the parts they apply to instead of using “x” wildcard. ▪ Removed “A” suffix from generic part number references throughout the document; left A100 and A072 suffixes.

1.12 May 10, 2023

▪ Updated the Type information for OEb pins in Pin descriptions tables ▪ Updated the Applications Information ▪ Completed other minor changes 1.11 Mar 10, 2023 ▪ Added RC19002A to data sheet, moved back to Preliminary pending production release of the RC19002A.

1.10 Dec 1, 2022 ▪ Fixed the link for the 40-VFQFPN package in Table 45

1.09 Nov 17, 2022 ▪ Changed t SLEW to 6 from 4 in Table 32

1.08 Nov 15, 2022 ▪ Updated the description of RC19024 pin A7 in Table 1

R31DS0016EU0128 Rev.1.28 Page 93 Nov 5, 2025 RC190xx Datasheet

1.07 Apr 11, 2022

▪ For all devices except RC19020A072:

• Updated Pin Type of all pins beginning with OEb to properly indicate internal pull-down (PD) resistors. ▪ For all devices except RC19020A072 and RC19024A:
• Removed Power-Down Tolerant indicator from multiplexed OEb SBI_OUT pins, they are not PDT. ▪ Minor reformatting of Pin Descriptions to reduce required space in Pin Description tables and to provide consistency across devices.

1.06 Apr 4, 2022

▪ Updated Loss of Signal and Automatic Clock Parking to change all CLK_IN to CLKIN for consistency. ▪ Inserted LOSb De-assert Timing RC19002, RC19020 Devices figure to distinguish the LOSb start- up behavior of those devices from the other devices. 1.05 Mar 23, 2022 Updated pins B10 and B43 from Do Not Connect (DNC) to GND on RC19024 Pin Assignments to tie off floating pins used for test. 1.04 Mar 15, 2022 Updated the PCI Express Base Specification 6.0 revision reference to 1.0 in footnotes 1 and 7 in Table 12 and Table 13. 1.03 Mar 3, 2022 ▪ Corrected pin 10 of RC19008A from NC to VDDCLK (see RC19008 Pin Assignments). 1.02 Feb 24, 2022 ▪ Completed minor updates to titles of CLK AC/DC Characteristics Tables for clarity. ▪ Completed other minor changes

1.01 Feb 1, 2022

▪ Added RC19020A072 pin out and pin descriptions to data sheet. ▪ Updated Figure 10 for RC19020A and RC19020A072. ▪ Updated Figure 2 title to reference correct package type (VFQFPN) and updated “100-VFQFPN” references to “100-VFQFPN” throughout the document. ▪ Added RC19020A072 marking diagram to RC1902xA Marking Diagrams and updated marking descriptions of RC19020A and RC19020A072. 1.00 Jan 18, 2022 Initial release. Revision Date Description

© Integrated Device Technology, Inc.

© Integrated Device Technology, Inc. Package Revision HistoryRev No.Date CreatedDescriptionAugust 12, 2019Rev 00Initial Release

M

12 BCDEFGHJKL

Ø0.225 6.00 ±0.10 SIDE VIEW 6.00 ±0.10Pin 1Index 0.50 5.50 Ref0.25 ±0.10 0.352.80 ±0.10 0.80 ±0.10C 5.500.50 5.500.500.352.80 2.80RECOMMENDED LAND PATTERN(PCB Top View, NSMD Design) 0.08C © Renesas Electronics Corporation

10.00 ±0.15 10.00 ±0.15 Pin 1 ID SIDE VIEW 1725554 1936 18 0.35 0.40 ±0.10 0.50 BOTTOM VIEWTOP VIEW 0.255.95 ±0.10 5.95 ±0.1037 (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN (1.65) Package Outline 172 5554 19 3618 0.35 10.309.20 10.300.250.50 5.95 5.95 9.20 © Renesas Electronics Corporation

TOP VIEWBOTTOM VIEW2x 2x0.10C 0.10C SIDE VIEW 48641 1617 32 9.00Index AreaAB 9.00 5.20 ±0.10 5.20 ±0.10 C0.3549 (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN 9.308.200.50 0.25 0.555.20 5.20C0.35 © Renesas Electronics Corporation

(PCB Top View, NSMD Design) 0.35 0.35 5.00 ±0.10 5.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW0.40 ±0.10 3.50 ±0.10 3.50 ±0.10 0.40 SIDE VIEW RECOMMENDED LAND PATTERN 0.20 (0.35) 0.200.40Package Outline 3.50 3.50 4.20 5.30 5.30 © Renesas Electronics Corporation

2.60 4.303.20 4.30 2.60 (PCB Top View, NSMD Design) 0.35 Seating Plane Package Outline 4.00 ±0.10 4.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW SIDE VIEW0.08C 0.200.40 RECOMMENDED LAND PATTERN 0.90 ±0.10 C(0.20)0.05 Max 781415 2122 28 0.35 (0.30) 0.40 ±0.10 2.60 ±0.10 2.60 ±0.10 0.40 0.20 © Renesas Electronics Corporation

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