RC18016 RENESAS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 2.1 Pin Assignments
- 2.2 Pin Descriptions
- 3.1 Absolute Maximum Ratings
- 3.2 Recommended Operating Conditions
- 3.3 Thermal Specifications
- 3.4 Pin Characteristics
- 3.5 DC Characteristics
- 3.6 AC Characteristics
- 3.6.1 Additive Clock Phase Noise Characteristics
- 4.1 Overview
- 4.2 Signal Flow
- 4.3 Clock Channel Divider
- 4.4 Phase Delay
- 4.4.1 Delay Calibration Block (DCB)
- 4.5 QCLK_y to SYSREF Phase Alignment
- 4.5.1 QCLK_y and QREF_r Phase Alignment Across Multiple Devices
- 4.6 Differential Outputs
- 4.7 Device Startup, Reset, and Synchronization
- 4.7.1 Changing Frequency Dividers and Phase Delay Values
- 4.8 SPI Interface
- 5.1 Fail-safe Inputs
- 5.2 Input Interface Circuits
- 5.3 Termination for QCLK_y, QREF_r LVDS Outputs
- 5.4 AC Termination for QCLK_y, QREF_r LVDS Outputs
- 5.5 Termination for QCLK_y, QREF_r LVPECL Outputs
- 5.6 Termination for QCLK_y, QREF_r AC-HCSL Outputs
- 5.7 AC Termination for QCLK_y, QREF_r AC-HCSL Outputs
- 5.8 Package Exposed Pad Thermal Release Path
- 5.8.1 Case Temperature Considerations
- 5.8.2 Example Calculation for Junction Temperature
- 6.1 Register Descriptions
- 6.2 Channel and Clock Output Registers
- 6.3 QREF_r Output State Registers
- 6.4 SYSREF, DCB, and Phase Alignment Control Registers
- 6.5 General Control Registers
Features
▪ Distribution, fanout, phase-delay of clock, and SYSREF signals ▪ Low output noise floor: -163dBc/Hz (245.76MHz) ▪ Supports clock frequencies up to 3GHz, including clock output frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and 122.88MHz ▪ Phase alignment mode across multiple buffers with any frequency divider setting ▪ Configuration through 3-wire SPI interface ▪ Supply voltage:
- 3.3V core and signal I/O
- 1.8V digital control SPI I/O (3.3V-tolerant inputs) ▪ Reference inputs are fail-safe ▪ Provides four output channels with a total of 16 differential outputs ▪ Outputs channels include:
- Dedicated clock outputs
- Outputs configurable as SYSREF outputs with individual phase delay stages, or configurable as additional clock outputs
- Clock outputs are powered-on/enabled at startup
- QREF_r (SYSREF) outputs disabled at startup ▪ Each clock channel contains:
- Frequency Dividers: ÷1, ÷2, ÷3, ÷4, ÷6, ÷8, ÷12, ÷16, ÷24
- Clock phase delay circuits, delay unit is the clock period; 256 steps ▪ SYSREF: Configurable precision phase delay circuits: 8 steps of 131ps, 262ps, 393ps, or 524ps ▪ Flexible differential outputs:
- LVDS/LVPECL/AC-HCSL
- Amplitude configurable for LVDS and LVPECL
- Power-down modes for unused outputs
- Supports DC and AC coupling
- QREF_r (SYSREF) output pre-bias feature to prevent glitches when turning output on or off ▪ Package: 64-VFQFPN (9.0 × 9.0 × 0.85 mm) ▪ Ambient temperature range: -40°C to +105°C (case) RC18016 JESD204B/C Compliant Fanout Buffers and Dividers
Figure 1. Block Diagram
2.1 Pin Assignments
Figure 2. Pin Assignments, 64-VFQFPN Package (Top View)
2.2 Pin Descriptions
Table 1. Pin Descriptions LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. 5 VDD_QREFB Power Positive supply voltage (3.3V) for the QREF_B[1:0] outputs. 6 VDD_QCLKB Power Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs. 11 VDD_QCLKB Power Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs. 12 VDD_QREFC Power Positive supply voltage (3.3V) for the QREF_C[1:0] outputs. LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. 17 VDD_QREFC Power Positive supply voltage (3.3V) for the QREF_C[1:0] outputs. 18 VDD_QCLKC Power Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs. 23 VDD_QCLKC Power Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs. 24 VDD_QREFD Power Positive supply voltage (3.3V) for the QREF_D outputs. LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. 27 VDD_QREFD Power Positive supply voltage (3.3V) for the QREF_D outputs. 28 VDD_QCLKD Power Positive supply voltage (3.3V) for the QCLK_D outputs. nQCLK_D Output Differential clock output QCLK_D. Configurable LVPECL/LVDS/AC-HCSL style and amplitude. 32 VDD_QREFA01 Power Positive supply voltage (3.3V) for the QREF_A[1:0] outputs. LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. 37 VDD_QREFA01 Power Positive supply voltage (3.3V) for the QREF_A[1:0] outputs. 38 VDD_QCLKA Power Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs. 45 VDD_QCLKA Power Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs. 46 VDD_QREFA2 Power Positive supply voltage (3.3V) for the QREF_A2 output.
LVPECL/LVDS/AC-HCSL style and amplitude for clock operation. 49 VDD_QREFA2 Power Positive supply voltage (3.3V) for the QREF_A2 output. 50 VDD_REF Power Positive supply voltage (3.3V) for the differential SYSREF input REF, nREF. signals. REF and nREF are internally 50terminated to the VTR pin. Fail-safe input.
53 VTR -
Information. Fail-safe input. 55 RES_CAL Analog Connect a 2.8 k (1%) resistor to GND for output current calibration. 56 VDD_CLK Power Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.
57 VTC -
Information. Fail-safe input. LVDS signals. CLK and nCLK are internally terminated to VTC through 50. Fail-safe input. 60 VDD_CLK Power Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.
61 SDAT Input/
Serial Control Port SPI Mode Data Input and Output. 1.8V LVCMOS/LVTTL interface levels. 64 VDD_SPI Power Positive supply voltage (3.3V) for the SPI interface. Pad (EP) GND Power Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
- Internal pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. See Table 5 for values.
Table 1. Pin Descriptions (Cont.)
3.1 Absolute Maximum Ratings
conditions can adversely impact product reliability and result in failures not covered by warranty.
3.2 Recommended Operating Conditions
3.3 Thermal Specifications
Table 2. Absolute Maximum Ratings
- According to JEDEC JS-001-2012/JESD22-C101.
Table 3. Recommended Operating Conditions
- 125°C/10year lifetime is based on the evaluation of intrinsic wafer process technology reliability metrics. The limiting wafer level reliability factor
temperature through simulation. Table 4. Thermal Resistance for 64-VFQFPN Package [1]
3.4 Pin Characteristics
3.5 DC Characteristics
- Standard JEDEC 2S2P multilayer PCB.
Table 5. Pin Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +105°C Table 6. Power Supply DC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions. Table 7. Typical Power Supply Current Characteristics, VDD_V = 3.3V, TA = 25°C [1][2]
- QCLK_y and QREF_r outputs unloaded.
Table 4. Thermal Resistance for 64-VFQFPN Package [1] (Cont.)
Table 8. LVCMOS DC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions. Table 9. LVCMOS (JESD8-7A, 1.8V) DC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1][2]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions.
- Table is valid for the SPI interface pins nCS, SCLK and SDAT. SPI inputs have hysteresis.
Table 10. Differential Input DC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions. Table 11. LVPECL DC Characteristics VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions.
- Outputs terminated with 50Ωto VT = VDD_V – 1.6V (350mV amplitude setting), VDD_V – 2.0V (750mV amplitude setting), VDD_V – 2.25V
3.6 AC Characteristics
Table 12. LVDS DC Characteristics VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1][2]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions.
- Outputs are terminated 100Ω
Table 13. AC-HCSL DC Characteristics VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1][2]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions.
- Outputs are terminated 50Ω to ground
Table 14. AC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted
reached under these conditions.
- The CLK, nCLK input supports 0Hz if the applied static signal has a minimum amplitude as specified by VIN, VDIFF_IN.
- Only applicable to a multi-device phase alignment procedure as a max frequency for applying multiple edges to the REF input. This specification
is not applicable if a single REF edge is used for multi-device phase alignment.
- VIL should not be less than -0.3V and VIH should not be greater than VDD_V.
- Common Mode Input Voltage is defined as the cross-point voltage.
Table 14. AC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1] (Cont.)
3.6.1 Additive Clock Phase Noise Characteristics
effect of additive phase noise is not measurable.
- LVPECL outputs terminated with 50Ω to VT = VDD_V – 1.6V (350mV amplitude setting), VDD_V – 2.0V (750mV amplitude setting), VDD_V – 2.25V
- LVDS outputs terminated 100Ω across Q, nQ.
- This parameter is defined in accordance with JEDEC standard 65.
- Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
- All frequency dividers N are in ÷1, ÷2, ÷4 or ÷8; output amplitude setting 750mV.
- Failure to meet CLK/REF setup and hold time can result in a failure to align output phases across multiple devices.
- Output amplitudes set to 350mV or 750mV.
Table 15. DCB and Phase Delay Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +105°C [1]
- Electrical parameters are confirmed over the specified ambient operating temperature range, which is established when the device is mounted in
reached under these conditions.
- CLK_x clock channel delay unit is equal to 1 ÷ fIN.
dominates the characteristics. Figure 3. Additive Clock Phase Noise Characteristics (85°C, Worst Case Simulation Model) Table 16. Additive Clock Phase Noise Characteristics (Simulation [1]), VDD_V = 3.3V ±5% [2]
- Ideal input signal: rectangular clock signal with a slew rate of 5V/ns and without phase noise.
- Phase noise and spurious specifications apply for device operation with QREF_r outputs inactive (no SYSREF pulses generated). Phase noise
specifications are applicable for all outputs active, Nx not equal, process and voltage variations included.
Table 17. Additive Clock Phase Noise Characteristics (Measured), VDD_V = 3.3V ±5%, TA = -40°C to +105°C [1][2]
- Phase noise and spurious specifications apply for device operation with QREF_r outputs inactive (no SYSREF pulses generated). Phase noise
specifications are applicable for all outputs active, Nx not equal.
- Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
reached under these conditions.
- Measured results at the maximum temperature of 85°C using an input source with a phase noise characteristics of:
- De-rating factor applied to the characterized data at 85°C to account for worst-case process variation.
Figure 6. Additive Clock Phase Noise Characteristics (Measured), fOUT = 983.04MHz Table 18. SYSREF Phase Noise Characteristics (Measured)
- Measured results with DLC[1:0] = 00 and REF_r = 3.
4.1 Overview
independent and are organized in channels, with each channel consisting of several clock and SYSREF outputs. through a SPI interface with read-back capability, controls the main device settings.
4.2 Signal Flow
a minimum of signal crosstalk and spurious signals.
4.3 Clock Channel Divider
and D is ÷1, the default divider value for channel B and C are set by the state of pin 31 (NBC_DEF). See Table 20. Table 19. NA-D Frequency Divider Settings
4.4 Phase Delay
of the clock channel phase-delay circuits ΦCLK_x is a function of the frequency fIN applied to CLK input: 1 ÷ fIN.
4.4.1 Delay Calibration Block (DCB)
Table 20. Frequency Divider Default Settings
- NBC_DEF can be left open (reads logic 1).
Table 21. Delay Circuit Characteristics
- SYSREF phase delay supports ≥ 8 delay stops within one input reference period for fIN = 254.76MHz to fIN = 983.04MHz.
f1 = f2 = 10.24MHz, fDCO = 983.04MHz. This example configuration results in a delay unit of measured: 131ps. Table 23 shows more configuration examples. Figure 7. DCB Functional Diagram Table 22. DCB Delay Unit at fDCO = 983.04MHz Table 23. DCB Divider Configuration Examples [1]
4.5 QCLK_y to SYSREF Phase Alignment
outputs, the CLK and REF input signals must be phase aligned or have a known, deterministic phase relationship. recommended phase delay setting several device configurations. Figure 8. QCLK_y to QREF Phase Alignment
4.5.1 QCLK_y and QREF_r Phase Alignment Across Multiple Devices
Table 24. Recommended Delay Settings for Closest Clock-SYSREF Output Phase Alignment [1]
- QCLK_y and QREF outputs are aligned on the incident edge.
REF inputs (see setup and hold time specification). ▪ The frequency on the REF input must be smaller than any QCLK_y output frequency. ▪ A valid input frequency must be applied to the CLK input (e.g., 491.52MHz). longer periods until output alignment is achieved.
- Example: Input CLK frequency is 491.52MHz, output divider is ÷4, output frequency is 122.88MHz. During the alignment procedure started by REF, the QCLK_y output period changes from 8.138ns to 10.172ns for multiple cycles. The device facilitates the period of the input signal (2.034ns) to “stretch” the output period: 8.138ns + 2.034ns = 10.172ns. Alignment Procedure 1. Set the MD_ALIGN_Φ bit to enable the alignment procedure. ▪ Wait for > 5μs before applying a signal to the REF input. 2. Apply an alignment signal (rising edge) to the REF input. ▪ Place the rising edge REF signal before the rising edge of the CLK signal that is shared between all participating buffers. ▪ REF to CLK setup and hold time specification must be met. ▪ A single REF rising edge is sufficient for starting the alignment. 3. Output behavior during alignment: ▪ QCLK_y outputs in ÷1 divider mode work normally as expected without cycle slips or period increases. ▪ QCLK_y outputs in ÷2, ÷3, ÷4, ÷6, ÷8, ÷12, ÷16 or ÷24 divider mode expose longer periods as described above. ▪ REF outputs always buffer out the REF input signal (when QREF_r outputs are powered on and are enabled). Result ▪ The procedure aligns the output phases (rising incident edge) of all QCLK_y output signals across participating buffers. This includes the output phases of the frequency-divided clock signals and the outputs divided by 1. ▪ The input to output delay is the same across all participating buffer devices (measured on the incident edge). ▪ The alignment procedure has a maximum duration of 48x (1 ÷ fIN). ▪ After alignment is achieved, the device auto-clears the MD_ALIGN_Φ register bit. The alignment procedure can be repeated at any time after setting the MD_ALIGN_Φ bit.
Table 25. MD_ALIGN_Φ Multi-Device Phase Alignment Function Table SYSREF outputs when output buffers are enabled.
1 A rising edge at the REF input will start an
output phase alignment procedure. auto-clears after alignment is achieved.
4.6 Differential Outputs
Table 26. Output Features
- Amplitudes are measured single-ended. Differential amplitudes supported are 700mV, 1500mV and 2000mV.
- AC coupling and DC coupling supported.
- See Application Information for output termination information.
- AC-HCSL refers to an output type with voltage levels below 1.2V and AC characteristics similar to HCSL.
- In JESD204B/C applications, it is recommended to use QREF_r (SYSREF) outputs configured to LVDS and 350mV amplitude. AC-coupling and
Table 27. Individual Clock Output (QCLK_y) Settings [1]
- Applicable to clock outputs: QCLK_y and QREF_r outputs in clock mode (MUX_r = 0).
- See Application Information for output termination information.
1 X X X X Off 100 differential (LVDS) or no termination Off X
- Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.
1 Enable 500
4.7 Device Startup, Reset, and Synchronization
input (the CLK input is internally turned off during that time). In the default configuration the QCLK_y outputs are enabled, QREF outputs are disabled at startup.
- (Optional) Set the value of the CPOL register bit to define the SPI read mode so that SPI settings can be
validated by subsequent SPI read accesses.
- Verify the completion of internal power-up by reading the ST_READY status bit in register 0x6E, bit D1.
Table 28. Individual SYSREF Output (QREF_r) Settings [1]
- Applicable QREF_r outputs when configured as SYSREF output (MUX_r = 1).
- See Application Information for output termination information.
1 X X X X X Off 100 differential or no termination Off X
0 XX 0
- Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.
0 See
1 Enabled
0 On 50 to VT (LVPECL)
Table 29. QREF_r Setting for JESD204B/C Applications
0 Static low [1]
1 Static low [1]
0 Static LVDS
- This is the state after setting the PD_S bit to 1 and then setting it to 0 as described in step 3 of Device Startup, Reset, and Synchronization.
1 Static LVDS crosspoint level [2][3]
R31DS0170EU0101 Rev.1.01 Page 24 Oct 11, 2024 RC18016 Datasheet 3. Configure the channel circuits and the outputs to the desired values and configure the DCB: ▪ For synchronization between multiple devices (see QCLK_y and QREF_r Phase Alignment Across Multiple Devices). Write a 1 to MD_ALIGN_ Φ to start the multi-buffer phase alignment process. This will cause the st_any_ALIGN status bit to be set to 1, then the MD_ALIGN_ Φ bit will automatically clear. The st_any_ALIGN status bit can be used to monitor the multi-buffer alignment process. When st_any_ALIGN reports 1, the device is either waiting for a rising edge on REF, or the alignment is in progress. When st_any_ALIGN reports 0, the alignment is complete. The multi-device alignment requires a valid clock signal to be applied to the CLK input. ▪ Output source MUX_r, output divider NA-D, clock delay ΦA-D; MUX-output style, amplitude and power down mode for QCLK_y and QREF_r outputs ▪ (Optional) In preparation for JESD204B/C SYSREF operation, configure the global BIAS_TYPE bit and the BIAS_r bit for each QREF_r. Further, for AC coupling applications (BIAS_TYPE = 1) after setting BIAS_TYPE to 1, set the PD_S bit to 1 and then set it to 0; this will set QREF_r and nQREF_r to the LVDS crosspoint level (VOS). If SYSREF generation is started and halted, then repeat the process of setting the PD_S bit to 1 and then setting it to 0; this will set QREF_r and nQREF_r to the LVDS crosspoint level (VOS). ▪ Phase delay for ΦREF_r values for the QREF_r outputs. ▪ Setup the DCB settings DLC, PDCB and MDCB as described in the paragraph “Configuration”, see Delay Calibration Block (DCB) 4. If not already applied: apply a valid input frequency to CLK. Set the PB_CAL bit and the DCB_CAL bit to start the calibration of the precision bias current circuit and the DCB calibration. Both bits will auto-clear. See paragraph “Configuration” in Delay Calibration Block (DCB). ▪ (Optional): verify the success of the DCB calibration by reading the DAC_CODE value. See paragraph “Verification” in Delay Calibration Block (DCB) 5. (Only for using the clock delay circuits): Set the initialization bit INIT_CLK to initiate the ΦCLK_x delay circuits. The INIT_CLK bit will self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state. 6. Enable or disable outputs as desired by accessing the output-enable registers 0x74 and 0x76. 7. At this point, the configuration of the registers should be completed and the SPI transfer ended. Set nCS to high level. Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to 0xFF range.
4.7.1 Changing Frequency Dividers and Phase Delay Values
Clock Frequency Divider and Delay The following procedure must be applied for a change of a clock divider and phase delay value NA-D, and ΦCLKA- 1. (Optional) Set the value of the CPOL register to define the SPI read mode so that SPI settings can be validated by subsequent SPI read accesses. 2. (Optional) Disable outputs that will experience a frequency divider or delay value change. 3. Configure the NA-D dividers and the delay circuits ΦCLKA-D to the desired new values. 4. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits, and synchronize them to each other. The INIT_CLK bit will self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state. 5. (Optional) Enable the outputs whose frequency divider was changed.
R31DS0170EU0101 Rev.1.01 Page 25 Oct 11, 2024 RC18016 Datasheet SYSREF Delay The following procedure must be applied for a change of any SYSREF phase delay value ΦREF_r: 1. (Optional) Set the value of the CPOL register to define the SPI read mode so that SPI settings can be validated by subsequent SPI read accesses. 2. Configure any delay circuits ΦREF_r to their desired new values. During configuration of ΦREF_r outputs are not stopped or interrupted.
4.8 SPI Interface
The RC18016 has a 3-wire serial control port capable of responding as a slave in an SPI configuration to allow read and write access to any of the internal registers for device programming or read back. The SPI interface consists of the SCLK (clock), SDAT (serial data input and output), and nCS (chip select) pins. A data transfer consists of any integer multiple of 8 bits and is always initiated by the SPI master on the bus. Internal register data is organized in SPI bytes of 8 bits each. If nCS is at logic high, the SDAT data I/O is in high-impedance state and the SPI interface of the RC18016 is disabled. In a write operation, data on SDAT will be clocked in on the rising edge of SCLK. In a read operation, data on SDAT will be clocked out on the falling or rising edge of SCLK depending on the CPOL setting (CPOL = 0: output data changes on the falling edge, CPOL = 1: output data changes on the rising edge). Starting a data transfer: Requires nCS to set and hold at logic low level during the entire transfer. Setting nCS = 0 will enable the SPI interface with SDAT in data input mode. The master must initiate the first 8-bit transfer. The first bit presented to the slave is the direction bit R/nW (1 = Read, 0 = Write) and the following seven bits are the address bits A[0:6] pointing to an internal register in the address space 0 to 127. Data is presented with the LSB (least significant bit) first. Read operation: Read from an internal register. A read operation starts with an 8-bit transfer from the master to the slave. SDAT is clocked on the rising edge of SCLK. The first bit is the direction bit R/nW which must be to 1 to indicate a read transfer, followed by 7 address bits A[0:6]. After the first 8 bits are clocked into SDAT, the SDAT I/O changes to output: the register content addressed by A[0:6] is loaded into the shift register and the next 8 SCLK falling clock cycles (if CPOL = 0) will then present the loaded register data on the SDAT output and transfer these to the master. Transfers must be completed by de-asserting nCS after any multiple 8 SCLK cycles. If nCS is de- asserted at any other number of SCLKs, the SPI behavior is undefined. SPI byte (8 bit) and back-to-back read transfers of multiple registers are supported with an address auto-increment. During multiple transfers, nCS must stay at logic low level and SDAT will present multiple registers (A), (A+1), (A+2), etc. with each 8 SCLK cycles. During SPI Read operations, the user may continue to hold nCS low and provide further bytes in a single block read. Write operation: Write to an RC18016 register. During a write transfer, a SPI master transfers one or more bytes of data into the internal registers of the RC18016. A write transfer starts by asserting nCS to low logic level. The first bit presented by the master must set the direction bit R/nW to 0 (Write) and the 7 address bits A[0:6] must contain the 7-bit register address. Bits D0 to D7 contain 8-bit of payload data, which is written into the register addressed by A[0:6] at the end of a 8-bit write transfer. Multiple, subsequent register transfers from the master to the slave are supported by holding nCS asserted at logic low level during write transfers. The 7-bit register address will auto-increment. Transfers must be completed by de-asserting nCS after any multiple 8 SCLK cycles. If nCS is de-asserted at any other number of SCLKs, the SPI behavior is undefined. End of transfer: After de-asserting nCS, the SPI bus is available to transfers to other slaves on the SPI bus. See also the READ diagram (Figure 9) and WRITE diagram (Figure 10) displaying the transfer of two bytes of data from and into registers. Registers 0x78 to 0xFF: Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in this range.
Figure 11. SPI Timing Diagram
5.1 Fail-safe Inputs
when the device is powered down.
5.2 Input Interface Circuits
Figure 12. LVDS Output Drives RC18016 Input with Integrated Termination Resistor (DC-Coupled) Figure 13. LVPECL Output Drives RC18016 Input with Integrated Termination Resistor (DC-Coupled)
5.3 Termination for QCLK_y, QREF_r LVDS Outputs
amplitude setting specified in Table 26. Table 31. Termination Resistors
Figure 14. LVDS Output Termination
5.4 AC Termination for QCLK_y, QREF_r LVDS Outputs
Figure 15. LVDS AC Output Termination – with Rebiased input Figure 16. LVDS AC Output Termination
5.5 Termination for QCLK_y, QREF_r LVPECL Outputs
amplitude setting defined in Table 26. The termination resistors must be placed close at the line end. Figure 17. LVPECL Output Termination
5.6 Termination for QCLK_y, QREF_r AC-HCSL Outputs
(50Ω) should be located close to the driver. Figure 18. AC-HCSL Output Termination
5.7 AC Termination for QCLK_y, QREF_r AC-HCSL Outputs
Figure 19. AC-HCSL Output Termination
5.8 Package Exposed Pad Thermal Release Path
between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Figure 20. Assembly for Exposed Pad Thermal Release Path – Side View (Drawing not to Scale)
5.8.1 Case Temperature Considerations
the maximum allowed operating junction temperature listed in Absolute Maximum Ratings. TJ = Junction temperature at steady state condition in (oC). TCB = Case temperature (Bottom) at steady state condition in (oC). temperature of the board measured at the top surface of the board. PD = Power dissipation (W) in desired operating configuration.
performance. In addition, there could be long-term reliability issues and increased failure rate.
5.8.2 Example Calculation for Junction Temperature
The following table is an example calculation for Junction Temperature (TJ): TJ = TCB + JB x PD. For the variables above, the junction temperature is TJ = TCB + YJB × PD = 105oC + 1.1oC/W × 2.76W = 108°C. Table 32. Thermal Resistance for 64-VFQFPN Package [1]
- Standard JEDEC 2S2P multilayer PCB.
- See Table 7, test case 7.
6.1 Register Descriptions
meaning, they are described only once, but with an additional table to indicate their addresses and default values. altered by values loaded from non-volatile storage during the initialization sequence. Table 33. Configuration Registers
Table 33. Configuration Registers (Cont.)
6.2 Channel and Clock Output Registers
down state, enable state and the clock phase delay. Table 34. Channel and Clock Output Register Bit Field Locations
1 A_A0A1[1:0] QCLKA0_A1
1 A_B0B1[1:0] QCLKB0_B1
Table 35. Channel and Clock Output Register Descriptions [1] The default value of the N_B and N_C divider is set by pin 31 (NBC_DEF). CLK_x[7:0] Phase Delay in units of the input period: CLK_x[7:0] ÷ fIN (256 steps). HSTL_y STYLE_y QCLK_y Output Format.
6.3 QREF_r Output State Registers
the style, the amplitude, the power state, the enable state and the output bias. Table 36. QREF_r Output State Register Bit Field Locations [1]
2 MUX_A2 REF_A2[2:0]
Table 37. QREF_r Output State Register Descriptions [1] QREF_r delay = REF_r[2:0] · TDCB. Delay values for fDCO = 983.04MHz. Delay values are a function of TDCB. BIAS_TYPE BIAS_r QREF_r output operation if set to LVDS. input. Use in DC-coupled applications. HSTL_r STYLE_r QREF_x Output Format.
6.4 SYSREF, DCB, and Phase Alignment Control Registers
- For AC coupling applications (BIAS_TYPE = 1) after setting BIAS_TYPE to 1, set the PD_S bit to 1 and then set it to 0; this will set QREF_r and
and then setting it to 0; this will set QREF_r and nQREF_r to the LVDS crosspoint level (VOS). Table 38. SYSREF, DCB and Phase Alignment Control Register Bit Field Locations Table 39. SYSREF, DCB, and Phase Alignment Control Register Descriptions BIAS_TYPE BIAS_r QREF_r output operation if set to LVDS. the REF input. Use in DC-coupled applications. edge of the REF input. Use in AC-coupled applications. Table 37. QREF_r Output State Register Descriptions [1] (Cont.)
6.5 General Control Registers
Effective delay unit for the SYSREF outputs is (1 + DLC[1:0]) ÷ (8 · fDCO). achieve a DCO frequency of 983.04±20MHz: fDCO = fIN ÷ PDCB · MDCB.
- For AC coupling applications (BIAS_TYPE = 1) after setting BIAS_TYPE to 1, set the PD_S bit to 1 and then set it to 0; this will set QREF_r and
and then setting it to 0; this will set QREF_r and nQREF_r to the LVDS crosspoint level (VOS). Table 40. General Control Register Bit Field Locations
18016 Reserved Reserved Reserved Reserved
Table 41. General Control Register Descriptions Table 39. SYSREF, DCB, and Phase Alignment Control Register Descriptions (Cont.)
Multi-buffer phase alignment status. 1 = Completed and device is ready for operation. PBIAS[5:0] R only X BIAS level. Clock divider and phase clock phase delay initialization. the calibration completed. Required to set as part of the startup procedure. startup procedure. The result of the calibration routine is stored in the DAC_CODE register. 0 = Data bits on MISO are output at the falling edge of SCLK edge. 1 = Data bits on MISO are output at the rising edge of SCLK edge. st_any_ALIGN bit to be set to 1. This bit will auto-clear. Table 41. General Control Register Descriptions (Cont.) ▪ Line 1 indicates the manufacturer. ▪ Line 2 indicates the part number.
- “Y” is the last digit of the year; “WW” is the work week number when the part was assembled.
- “$” denotes the mark code.
- “***” denotes the last three characters of the assembly lot number.
Table 42. Pin 1 Orientation in Tape and Reel Packaging Index x Denominates a channel, channel frequency divider and the associated configuration bits. Range: A, B, C, D. Index y Denominates a QCLK output and associated configuration bits. Range: A0, A1, A2, B0, B1, C0, C1, D. Index r Denominates a QREF output and associated configuration bits. Range: A0, A1, A2, B0, B1, C0, C1, D. VDD_QCLKC, VDD_QREFC, VDD_QCLKD, VDD_QREFD, VDD_CLK, VDD_REF. [...] Index brackets describe a group associated with a logical function or a bank of outputs. {…} List of discrete values.
1.01 Oct 11, 2024
▪ Updated item 3 in Device Startup, Reset, and Synchronization. ▪ Changed EN_REF_D to EN_QREF_D for register 0x76 in Table 36. ▪ Added st_any_ALIGN to Table 40 and Table 41. ▪ Updated the description of MD_ALIGN_Φ in Table 41. 1.00 Jul 19, 2024 Initial release.
SIDE VIEW0.08CSeating Plane A 9.00 ±0.15 BIndex Area (PCB Top View, NSMD Design)RECOMMENDED LAND PATTERN 0.20 Ref 0.05 Max 0.90 ±0.10 9.308.200.25 0.55 Package Outline 6.00 6.00 16173233 4647 640.40 ±0.100.24 ±0.06 6.00 ±0.10 6.00 ±0.101.10 Ref 8 x C0.113 9.00 ±0.15 C 0.50 0.505 © Renesas Electronics Corporation
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