SIC462 VISHAY | Alldatasheet

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www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 1 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

4.5 V to 60 V Input, 6 A Synchronous Buck Regulator

DESCRIPTION

The SiC462 is a wide input voltage high efficiency synchronous buck regulator wi th integrated high-side and low-side power MOSFETs. Its power stage is capable of supplying 6 A continuous current at up to 2 MHz switching frequency. This regulator produces an adjustable output voltage down to 0.8 V from 4.5 V to 60 V input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. SiC462’s architecture delivers ultra-fast transient response with minimum output capacitance and tight ripple regulation at very light load. The device is stable with any capacitor and no external ESR network is required for loop stability. The device also incorporates a power saving scheme that significantly increases light load efficiency. The regulators integrates a full protection feature set, including over current protection (OCP), output overvoltage protection (OVP), short circuit protection (SCP), output undervoltage protection (UVP) and thermal shutdown (OTP). It also has UVLO for input rail and a user programmable soft start. The SiC462 is available in le ad (Pb)-free power enhanced MLP55-27L package.

FEATURES

  • Single supply operation from 4.5 V to 60 V input voltage
  • Adjustable output voltage down to 0.8 V
  • 6 A continuous output current
  • Adjustable switching frequency from 100 kHz to 2 MHz
  • Adjustable current limit and soft start
  • 98 % peak efficiency
  • Ultra-fast transient response
  • ± 1 % output voltage accuracy
  • Normal, ultrasonic or pulse skipping operation
  • 5 μA shutdown current
  • 250 μA operating current
  • Cycle-by-cycle current limit
  • Output overvoltage protection
  • Output undervoltage / short circuit protection
  • Output voltage tracking and sequencing
  • Scalable family of output current:

3 A (SiC463), 6 A (SiC462), 10 A (SiC461)

APPLICATIONS

  • POLs for telecom
  • Industrial and automation
  • Industrial computing
  • Consumer electronics TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS Fig. 1 - Typical Application Circuit for SiC462 VIN PGOOD EN VDD SW PGND AGND PGOOD ENABLE VOUT VFB BOOT SS VSNS fSW ILIMIT Phase COMP VCIN VDRV MODE ULTRASONIC INPUT 4.5 V DC to 60 VDC SiC462

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 2 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PIN CONFIGURATION Fig. 2 - SiC462 Pin Configuration PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION 1V CIN Supply voltage for internal regulators VDD and VDRV. This pin should be tied to VIN, but can also be connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators 2P GOOD Open-drain power good indicator - high impedance indicates power is good. An external pull-up resistor is required

3 EN Enable pin

4 BOOT High-side driver bootstrap voltage

5, 6 PHASE Return path of high-side gate driver 7, 8, 29 V IN Power stage input voltage. Drain of high-side MOSFET 9, 10, 11, 17, 30 P GND Power ground 12, 13, 14 SW Power stage switch node

15 GL Low-side MOSF ET gate signal

16 V DRV

Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, VDRV is the LDO output. Connect a 4.7 μF decoupling capacitor to PGND

18 ULTRASONIC

Float to disable ultrasonic mode, connect to VDD to enable. Depending on the operation mode set by the MODE pin, power save mode or forced continuous mode will be enabled when the ultrasonic mode is disabled 19 SS Set the soft start ramp by connecting a capacitor to AGND. An internal current source will charge the capacitor

20 V SNS Power inductor signal feedback pin for system stability compensation

21 COMP Output of the internal error amplifier. The feedback loop compensation network is connected from this pin to the V FB pin

22 V FB

Feedback input for switching regulator used to program the output voltage - connect to an external resistor divider from VOUT to AGND 23, 28 A GND Analog ground 24 f SW Set the on-time by connecting a resistor to AGND

25 I LIMIT Set the current limit by connecting a resistor to AGND

26 V DD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND 27 MODE Set various operation modes by connecting a resistor to A GND. See specification table for details SS 19 ULTRASONIC 18 PGND 17 VDRV 16 GL 15 SW 14 SW 13 SW 12 PGND 11 PGND 10 PGND 9 VIN 8 VIN 7

1 VCIN

2 PGOOD

4 BOOT

5 PHASE

6 PHASE

20 VSNS

21 COMP

23 AGND

25 ILIM

26 VDD

27 MODE

28 AGND

17 PGND

16 VDRV

22 VFB

28 A GND

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 3 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PART MARKING INFORMATION Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. Note (1) For input voltages below 5 V, provide a separate supply to VCIN of at least 5 V to prevent the internal VDD rail UVLO from triggering.

ORDERING INFORMATION

PART NUMBER PACKAGE MARKING CODE SiC462ED-T1-GE3 PowerPAK ® MLP55-27L SiC462 SiC462EVB Reference board ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) ELECTRICAL PARAMETER CONDITIONS LIMITS UNIT EN, V CIN, VIN Reference to PGND -0.3 to +63 V SW / PHASE Reference to P GND -0.3 to +66 VDRV Reference to PGND -0.3 to +6 VDD Reference to AGND -0.3 to +6 SW / PHASE (AC) 100 ns -4 to +72 BOOT -0.3 to V PHASE + VDRV AGND to PGND -0.3 to +0.3 All other pins Re ference to AGND -0.3 to VDD + 0.3 Temperature Junction temperature T J -40 to +150 °CStorage temperature T STG -65 to +150 Power Dissipation Thermal resistance from junction to ambient 12 °C/WThermal resistance from junction to case 2 ESD Protection Electrostatic discharge protection Human body model, JESD22-A114 2000 VCharged device model, JESD22-A101 750 RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V) PARAMETER MIN. TYP. MAX. UNIT Input voltage (V IN)4 . 5 - 6 0 V Control input voltage (VCIN) (1) 4.5 - 60 Enable (EN) 0 - 60 Bias supply (V DD) 4.75 5 5.25 Drive supply voltage (VDRV) 4.75 5.3 5.5 Output voltage (VOUT) 0.8 - 0.8 x V IN Temperature Recommended ambient temperature -40 to +105 °COperating junction temperature -40 to +125 = pin 1 indicator P/N = part number code = Siliconix logo =E SD symbol F = assembly factory code Y = year code WW = week code LL = lot code F Y W W P/N LL

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 4 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, TJ = -40 °C to +125 °C, unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Power Supplies V DD supply V DD VIN = VCIN = 6 V to 60 V, VEN = 5 V, not switching -5- V VIN = VCIN = 5 V, VEN = 5 V, not switching -4 . 9 6- VDD dropout V DD_DROPOUT VIN = VCIN = 5 V, IVDD = 1 mA - 60 - mV VDD UVLO threshold V DD_UVLO -4 . 2 5- V VDD UVLO hysteresis V DD_UVLO_HYST - 250 - mV Maximum VDD current I DD VIN = VCIN = 6 V to 60 V 3 - - mA VDRV supply V DRV VIN = VCIN = 6 V to 60 V, VEN = 5 V, not switching -5 . 3- V VIN = VCIN = 5 V, VEN = 5 V, not switching -5- VDRV dropout V DRV_DROPOUT VIN = VCIN = 5 V, IVDD = 10 mA - 160 - mV Maximum VDRV current I DRV VIN = VCIN = 6 V to 60 V 50 - - mA VDRV UVLO threshold V DRV_UVLO -4 . 2 5- V VDRV UVLO hysteresis V DRV_UVLO_HYST - 275 - mV Input current IV CIN Non-switching, VFB > 0.8 V - 245 - μA Shutdown current IV CIN_SHDN VEN = 0 V - 5 10 Controller and Timing Feedback voltage V FB TJ = 25 °C 796 800 804 m/V TJ = -40 °C to +125 °C (1) 792 800 808 VFB input bias current I FB -2- n A Transconductance g m -0 . 3-m S COMP source current I COMP_SOURCE -2 0- μA COMP sink current I COMP_SINK -2 0- Minimum on-time t ON_MIN. - 100 - ns tON accuracy t ON_ACCURACY -1 0-% On-time range t ON_RANGE 100 - 8000 ns Frequency range f kHz Ultrasonic mode enabled 20 - 2000 kHz Ultrasonic mode disabled - - 2000 Minimum off-time t OFF_MIN. - 250 - ns Soft start current I SS -5- μ A Soft start voltage V SS When VOUT reaches regulation - 1.5 - V Power MOSFETs High-side on resistance R ON_HS VGS = 5.3 V -2 5- Low-side on resistance R ON_LS -1 1- Fault Protections Current limit accuracy I LIM_ACCURACY 1 % resistor used for RLIM -20 - 20 %Output OVP threshold OVP VFB with respect to 0.8 V reference -2 0- Output UVP threshold UVP - -80 - Over temperature protection OTP R Rising temperature - 150 - OTPHYST Hysteresis - 35 -

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 5 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Note (1) Guaranteed by design Power Good Power good output threshold VFB_RISING_VTH_OV VFB rising above 0.8 V reference - 20 - VFB_FALLING_VTH_UV VFB falling below 0.8 V reference - -10 - Power good hysteresis P GOOD_HYST -5 5- m V Power good on resistance R ON_PGOOD -8-  Power good delay time t DLY_PGOOD -2 5-μ s EN / MODE / Ultrasonic Threshold EN logic high level V EN_H 1.4 - - V EN logic low level V EN_L -- 0 . 4 EN pull down resistance R EN -5- M  Ultrasonic mode high Level U HIGH 2-- V Ultrasonic mode low level U LOW -- 0 . 8 Mode pull up current I MODE -5- μ A MODE1 Power save mode enabled, VDD, VDRV Pre-reg on 0- 0 . 7 V MODE2 Power save mode disabled, VDD, VDRV Pre-reg on 1.3 - 1.7 MODE3 Power save mode disabled, VDRV Pre-reg off, VDD Pre-reg on, provide external VDRV 2.3 - 2.7 MODE4 Power save mode enabled, VDRV Pre-reg off, VDD Pre-reg on, provide external VDRV 3.3 - V DD ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, TJ = -40 °C to +125 °C, unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 6 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 FUNCTIONAL BLOCK DIAGRAM Fig. 3 - SiC462 Functional Block Diagram VIN VFB PGOOD 5 μA Current source 0.8 V I LIMIT MODE EN Bandgap Ref Driver LDO 25 kHz DC Restore Control logic and driver VDRV VCIN On timer fsw VCIN Error Amp Over temp Internal LDO Current sense COMP VSNS SW SS Comp Zero current DET Sync. rectifier Off timer VDRV VDD GL UVLO VDD5 μA Ref MODE BOOT Over voltage PWM Comp Ref Ramp Ultrasonic PHASE PGND Under voltage AGND 5 μA Ref VFB SW SW

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 7 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 OPERATIONAL DESCRIPTION Device Overview SiC462 is a high-efficiency synchronous buck regulator capable of delivering up to 6 A continuous current. The device has programmable swit ching frequency of 100 kHz to 2 MHz. The control scheme is based on voltage mode constant on time. It delivers fast transient response and minimizes external component s. It also enables loop stability regardless of the type of output capacitor used, including low-ESR ceramic capa citors. This device also incorporates a power saving feature by enabling diode emulation mode and frequency fold back as the load decreases. SiC462 has a full set of protection and monitoring features:

  • Over current protection in pulse-by-pulse mode
  • Output overvoltage protection
  • Output undervoltage protection with device latch
  • Over temperature protection with hysteresis
  • Dedicated enable pin for easy power sequencing
  • Power good open drain output
  • This device is available in MLP55-27L package to deliver high power density and minimize PCB area. Power Stage SiC462 integrates a high-performance power stage with a 25 m n-channel high side MOSFET and a 11 m n-channel low side MOSFET. The MOSFETs are optimized to achieve up to 98 % efficiency. The power input voltage (V IN) can go up to 60 V and down as low as 4.5 V for power conversion. Control Scheme SiC462 employs a voltage - mode COT control mechanism in conjunction with adaptive zero current detection which allows precise power saving feature. The switching frequency, f SW, is set by an external resistor to AGND, Rfsw. Note, that there is no V IN dependency on fSW as the on time adjusts as V IN is varied. During st eady-state operation, VCOMP is generated from the fee dback voltage and internal 0.8 V reference inputs to the er ror amplifier. An internally generated ramp signal and VCOMP are fed into a comparator. Once VRAMP crosses VCOMP, a single shot ON-time pulse is generated for a fixed time, programmed by the external RFSW. During the On-time pulse, the high side MOSFET will be turned ON. Once the ON-time pulse expires, the high side MOSFET is turned off and the low side MOSFET will be turned ON after a break-befo re-make period. The low side MOSFET will be on for duration of minimum OFF-time pulse until V RAMP crosses VCOMP. The cycle is then repeated. Fig. 4 illustrates the basic bl ock diagram for voltage mode constant on time architecture with external ripple injection.
  • The reference of a basic vo ltage mode COT regulator is replaced with a high gain e rror amplifier loop. This loop ensures the DC component of the output voltage follows the internal accurate reference voltage provides excellent regulation
  • A second voltage feedback path via the V SNS with a ripple injection scheme ensures rapid correction of the transient perturbation
  • This establishes two parallel voltage regulating feedback paths, a ripple injection path , and a steady accurate dc reference path Fig. 4 - SiC462 Control Block Diagram For stability purposes the SiC462 requires 200 mV of ripple injection. C X, CY, and RX are selected to achieve the desired ripple injection. Typically C y i s c h o s e n t o b e  2 nF to meet the internal impedance of the VSNS pin. CX is chosen to be 10 times greater than CY, CX = 10 x CY. Fig. 5 demonstrates the basic operational waveforms: Fig. 5 - SiC462 Operational Principle Typically, the frequency of R COMP and CCOMP is chosen to be around the resonance frequency of LOUT and COUT. In this case, set For good slew rate / transi ent load response, pick C COMP  1 nF, R COMP can be calculated according the formula above. Rfsw VOUT fsw 190 10 12– V1 Q1 Ripple based controller CY RCOMP 1 nF CCOMP + Ref. Erroramp RX CX LOUT C OUT Load RX VIN - VOUT x V OUT /V IN fSW x CX x VRIPPLE= Fixed on-time VRAMP VCOMP PWM RCOMP x CCOMP LOUT x COUT=

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 8 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Power-Save Mo de, MODE Pin, an d Ultrasonic Pin Operation To improve efficiency at light-loads, SiC462 provides a set of innovative implementations to eliminate LS re-circulating current and switching losses. The internal zero crossing detector (ZCD) monitors SW node voltage to determine when inductor current starts to flow negatively. In power saving mode, as soon as in ductor valley current crosses zero, the device first deploys diode emulation mode by turning off the LS FET. If load further decreases, switching frequency is reduced proportional to the load condition to save switching losses while keeping output ripple within tolerance. If the ultrasonic pin is tied to V DD, the minimum switching frequency in the discontinuous mode is 25 kHz to avoid switching frequencies in the audible range. If this feature is not required this ultrasonic mode can be disabled by floating the ultrasonic pin. When the ultrasonic mode is disabled, the regulator will either operate in forced continuous mode or in a power save mode where there is no limit to the lower frequency limit. In this state, at zero load switching frequency can go as low as hundreds of Hz. To improve the converter efficiency, the user can choose to disable the internal V DRV regulator by picking either Mode 3 or Mode 4 and connecting a 5 V supply to the VDRV pin. This reduces power dissipation in the SiC462 by eliminating the VDRV linear regulator losses. The MODE pin supports several modes of operation as shown in table 1. An internal current source is used to set the voltage on this pin using an external resistor: Note (1) Connect a 5 V (± 5 %) supply to the VDRV pin The mode pin is not latche d to any state and can be changed on the fly. OUTPUT MONITORING AND PROTECTION Output Over-Current Protection (OCP) SiC462 has cycle by cycle current limiting. The inductor valley current is monitored du ring LS FET turn-on period through R DS(on) sensing. After a pre-d efined blanking time, the valley current is compared wi th an internal threshold. If monitored current is higher than threshold, HS turn-on pulse is skipped and LS FET is kept on until the valley current returns below OCP limit. In a short circuit or a severe over-current condition, output undervoltage protection (UVP) will result in both the HS and LS FET turning off. See output undervoltage protection (UVP) section for more details. OCP is enabled immediately after V CC passes UVLO level. OCP is set by an external resistor to AGND, RLIM. Fig. 6 - Over-Current Protection Illustration Output Undervoltage Protection (UVP) UVP is implemented by monitoring output through VFB pin. If the voltage level at V FB goes below 0.16 V (V OUT is 20 % of V OUT set point) for more than 25 μs a UVP event is recognized and both HS and LS MOSFETs are turned off. After a time-out period equal to 20 soft start cycles, the IC attempts to re-start by going through a soft start cycle. If the fault condition still exists, the above cycle will be repeated. UVP is only active after th e completion of soft-start sequence. Output Over-Voltage Protection (OVP) For OVP implementation, output is monitored through FB pin. After soft start, if the voltage level at FB is above 0.96 V (typ.) (V OUT is 120 % of VOUT set point), OVP is triggered with both the HS and LS MOSFETs turned off. Normal operation is resumed once FB voltage drops back to 0.96 V. OVP is active immediately after V CC passes UVLO level. Over-Temperature Protection (OTP) SiC462 has internal thermal monitor block that turns off both HS and LS FETs when junction temperature is above 150 °C (typ). A hysteresis of 35 °C is implemented, so when junction temperature drops below 115 °C, the device restarts by initiating soft-start sequence again. Sequencing of Input / Output Supplies SiC462 has no sequencing requirements on any of its input / output (V IN, VDRV, VDD, VCIN, EN) supplies or enables. Enable The SiC462 has an enable pin to turn the part on and off. Driving this pin high enables the device, while grounding it turns it off. The SiC462 enable has a weak pull down to prevent unwanted turn on due to a floating GPIO. There are no sequencing requirements w.r.t other input / output supplies. TABLE 1 - OPERATION MODES MODE RANGE (V) POWER SAVE MODE INTERNAL VDRV REGULATOR 1 0 to 0.7 Enabled ON 2 1.3 to 1.7 Disabled ON 3 2.3 to 2.7 Disabled OFF (1) 4 3.3 to V DD Enabled OFF (1) RLIM 480k / I OUT max.= Iload OCPthreshold Iinductor GH

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 9 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Soft-Start SiC462 soft-start time is adjustable by selecting a capacitor value from the following equation. Once V CC is above UVLO level (2.55 V typ.), V OUT will ramp up slowly, rising monotonically to the programmed output voltage. There is an internal 5 μA current source tied to the soft start pin which charges the external soft start cap. During soft-start period, OCP is activated. Short-circuit protection is not active until soft-start is complete. Pre-Bias Start-Up In case of pre-bias startup, output is monitored through FB pin. If the sensed voltage on FB is higher than the internal reference ramp value, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. Fig. 7 - Pre-Bias Start-Up Fig. 8 - PGOOD Window and Timing Diagram Power Good SiC462’s power good is an open-drain output. Pull P GOOD pin high up to 5 V through a 10K resistor to use this signal. Power good window is shown in the diagram above. If voltage level on FB pin is out of this window, PG signal is de-asserted by pulling down to GND. To prevent false triggering during transient events, P GOOD has a 25 μs blanking time. SS time Cext x 0.8 V Vref (0.8 V) VFB VFB_Rising_Vth_OV (typ. = 0.96 V) VFB_Falling_Vth_OV (typ. = 0.91 V) VFB_Falling_Vth_UV (typ. = 0.72 V) VFB_Rising_Vth_UV (typ. = 0.77 V) PG Pull-high Pull-low

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 10 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 REFERENCE BOARD SCHEMATIC C10 DNP R10 40kC11 1n TP1 Vin1 TP2 GND 1 TP5 Vout1 TP6 GND TP4 TP3 PGD J11 GND VO_GND EN C142.2n C134.7u GL 0C1 100n J10 EN 100k C25 POSCAP PGD PGD R15 100 JUMPER 1 2 JUMPER 1 2 JUMPER 1 2 JUMPER 1 2 R3500K R4750K R110k R2300K C12 4.7nF Mode 82k Ilim 126k VDD1 CON4 0.1uF COMP VDRV 2.2uF 2.2uF 56u R12 Open Vdrv 56u VO JUMPER 1 2 Ultra VDD1 VO_GND 2.2uF C21 22uF C22 22uF C23 22uF VO C24 22uF Vin 0.1uF DNP VIN R14 R16 DNP C16 DNP C15 22nF L1 15uH EN R13 9.50k C18 22uF C17 0.1u C19 22uF C20 22uF R11 679 IC1 SiC462 VCIN PGOOD EN BOOT Phase1 Phase2 VIN1 VIN2 PGND1 PGND2 PGND3 SW1 SW2 SW3 VDRV SS Ultrasonic MODE VSNS COMP PGND VFB AGND FSW ILIM VDD GND-PAD GL

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 11 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Note (1) These two large Aluminium Electrolytic caps are included in case the customers evaluation set up has long leads. They are not n eeded for SiC462 operation. BILL OF MATERIAL QTY REFERENCE DESIGNATOR DESCRIPTION PART NUMBER MANUFACTURER 1 C1 Capacitor ceramic 0.1 μF 100 V X5R 0402 GRM155R62A104ME14D Murata Electronics

1 C3 Capacitor ceramic 1 μF 35 V X5R 0402 C1005X5R1V105M050BC TDK Corporation

1 C11 Capacitor ceramic 1000 pF 100 V X7R 04 02 GRM155R72A102KA01D Murata Electronics

1 C12 Capacitor ceramic 10000 pF 100 V X7S 0402 C1005X7S2A103K050BB TDK Corporation

2 C2, C9 Capacitor ceramic 0.1 μF 100 V X7 R 0603 GRM188R72A104KA35D Murata Electronics 1 C15 Capacitor ceramic 0.022 μF 100 V X7R 0603 C0603C223K1RACTU Kemet

1 C14 Capacitor ceramic 2200 pF 100 V X7R 0603 C0603C222K1RACTU Kemet

1 C17 Capacitor ceramic 0.1 μF 35 V X5R 0603 GMK107BJ104KAHT Taiyo Yuden 1 C13 Capacitor ceramic 4.7 μF 35 V X5R 080 5 GRM219R6YA475KA73D Murata Electronics 3 C6, C7, C8 Capacitor ceramic 2.2 μF 100 V X7R 1210 HMK325B7225KN-T Taiyo Yuden

7 C18, C19, C20, C21,

C22, C23, C24 Capacitor ceramic 22 μF 25 V X5R 1210 GR M32ER61E226KE15L Murata Electronics 1 J5 Terminal block 5.08 mm VERT 4POS ED120/4DS On Shore Technology Inc. 2C 4 , C 5 (1) Capacitor aluminum 56 μF 20 % 100 V radial UHE2A560MPD Nichicon

1 L1 Inductor 10 μH IHLP4040DZER100M11 Vishay

5 J1, J2, J3, J4, J9 B/S II HDR. SR 68000-402 Amphenol FCI 1C 2 5 D N P - -

1 R1 Resistor 10K 1 % 1/16 W 0402 RC0402FR-0710KL Yageo

1 R2 Resistor 300K 1 % 1/16 W 0402 RC0402FR-07300KL Yageo

1 R3 Resistor 499K 1 % 1/16 W 0402 RC0402FR-07499KL Yageo

1 R4 Resistor 750K 1 % 1/16 W 0402 RC0402FR-07750KL Yageo

2 R5, R7 Resistor 100K 1 % 1/16 W 0402 RC0402FR-07100KL Yageo

1 R6 Resistor 0.0 Jumper 1/16 W 0402 RC0402JR-070RL Yageo 1 R8 Resistor 48.7K 1 % 1/16 W 0402 RC0402FR-0748K7L Yageo

1 R9 Resistor 210K 1 % 1/16 W 0402 RC0402FR-07210KL Yageo

1 R10 Resistor 56K 5 % 1/16 W 0402 RC0402JR-0756KL Yageo

1 R11 Resistor 10K 5 % 1/10 W 0603 RC0603FR-0710KL Yageo

1 R14 Resistor 6.8K 5 % 1/10 W 0603 RC0603JR-076K8L Yageo

1 R13 Resistor 140K 1 % 1/10 W 0603 RC0603FR-07140KL Yageo

1 R15 Resistor 100 1 % 1/10 W 0603 RC0603FR-07100RL Yageo

1 IC1 IC SiC462 SiC462 Vishay

10 J7, J8, J10, J11, TP,

TP2, TP3, TP4, TP5, TP6 BERGSTIK II 0.100" SNGL ST 68002-401HLF Amphenol FCI

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 12 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 EXTERNAL COMPONENT SELECTION FOR THE SiC462 A reference design has been developed to illustrate how to choose component values for proper operation of the SiC462. The schematic for the demo board is shown in Fig. 9 and Table 2. Demo Board Connection and Signal / Test Points Power Sockets V IN, GND (P1): input voltage source with VIN to be positive. Connect to a voltage source: V OUT, GND (P3): output voltage with V OUT to be positive. Connect to a load that draws no more than:

5 V, GND (P10): external 5 V MOSFET gate voltage source

with 5 V to be the positive input. Apply 5 V when Mode 3 or Mode 4 is selected. Selection Jumpers Mode Select P7: this is an 8 way header which allows the user to select one of four modes of operation. MODE1 - SHORT PIN 1 to 2 Power save, V DRV and Pre-reg on MODE2 - SHORT PIN 3 to 4 Forced PWM, V DRV and Pre-reg on MODE3 - SHORT PIN 5 to 6 Forced PWM, V DRV and Pre-reg off - external 5 V supply MODE4 - SHORT PIN 7 to 8 Power save, V DRV and Pre-reg off - external 5 V supply V DRV External Supply P10: this is a 2 way header that will enable the user to supply an external MOSFET gate driv er supply if an external 5 V supply is available. This should only be used in MODES 3 and 4. ENABLE P9: this is a 2 way header that will enable the part if left open. When shorted the part is disabled. OPEN Pin 1-2 - automatic enable on power up SHORT Pin 1-2 - IC disabled. Ultrasonic P8: this is a 2 way header that will enable the user to select the ultrasonic mode of operation. In ultrasonic mode the minimum frequency of operation is 20 kHz, above the audible range. When not in ul trasonic mode the frequency can drop below 20 kHz. OPEN Pin 1-2 - ultrasonic disabled SHORT Pin 1-2 - ultrasonic enabled SIGNALS AND TEST LEADS Input Voltage Sense V IN_SENSE, GND IN_SENSE (P2): this allows the user to measure the voltage at the input of the regulator and remove any losses generated due to the, connections from the measurement. This can also be used by a power source with sense capability. Output Voltage Sense V OUT_SENSE, GND OUT_SENSE (P4): this allows the user to measure the voltage at the output of the regulator and remove any losses generated due to the connections, from the measurement. This can also be used by an active load with sense capability. POWER GOOD INDICATOR P GOOD (P11): is an open drain output and is pulled up with a 10 k resistor to VIN. When FB or VOUT are within -10 % to +20 % of the set voltage this pin will go HI to indicate the output is okay. POWER UP PROCEDURE To turn-on the reference board, apply 12 V to V IN with the P7 jumper is in position 1. If the P7 jumper is in place 1 the board will come up in power sa ve mode, if in place 2 then constant PWM will be observed. When applying higher than 12 V to the input it is reasonable to install a RC snubber from SW to GND if needed however this will affect efficiency. Th ere are place holders on the reference board, R 11 and C 12 for the snubber. Values of 4  and 1 nF are a reasonable starting point. ADJUSTMENTS TO THE REFERENCE BOARD OUTPUT VOLTAGE ADJUSTMENT If a different output voltage is needed, simply change the value of V OUT and solve for R 12 based on the following formula: Where V FB is 0.8 V for the SiC46X. RBOTTOM (R13) should be a maximum of 10 k to prevent VOUT from drifting at no load. CHANGING SWITCHING FREQUENCY The following equation illustrates the relationship between on-time, V IN, VOUT, and Rfsw value: OUTPUT RIPPLE VOLTAGE There is no requirement for th is converter to see output capacitor ripple voltage in the control loop as a voltage injection circuit is employed; the voltage injection ramp is used to alert the converter to the next switch event. Output ripple voltage is meas ured with a tip and barrel measurement across C OUT; the barrel of the probe is the GND / 0 V connection and this removes the effect of the long GND / 0 V leads of the probe. Typically output ripple voltage R12 R13 VOUT - VFB VFB Rfsw R7 VOUT fsw 190 10 12–

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 13 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 is set to 3 % to 5 % of the output voltage, but an all ceramic output solution can bring output ripple voltage to a much lower level since the ESR of ceramics can be in the range of m’s. VOLTAGE INJECTION NETWORK This is the network seen placed across the output inductor in the schematic consisting of R 10, C 10 and C 11. A quick method to add or remove inject ion is to reduce or increase R10. The time constant of the voltage injection network is as follows: In order to set a correct magn itude, the SiC46x requires around 200 mV, the following equation is used: Where V INJECTION = 200 mV is the midpoint of the ripple injection RC circuit. Fig. 9 - Voltage Injection Circuit In fig. 9 the recommended value of C X = C 10 ( a o r b )  22 nF and CY = C11  2.2 nF. The reference design allows placement of C X in two positions as shown in fig. 9, “a” and “b”. The “b” option removes the output ripple and transient response voltage from the injection signal. Th e effect of connecting the C X capacitor to GND / 0 V is the same as removing the output information from the fast loop. The output will be very stable in this setup when large transient loads are experienced at the output; in any case you will notice that the effective impedance of the output node is very small and the FB loop will react quickly enough for all loads. Another key aspect of using the GND / 0 V connection for the injection circuit is the ability to use a smaller output capacitance. Be aware that the b) option is should only be used with forced PWM operation. Where t is the ON period. The required magnitude is ~ 100 mVpp for stable operation. Compensation The COT loop uses a transconductance amplifier to convert a proportional current from the output voltage, V FB. This has the effect of offering a high impedance at the V FB node, however this circuitry is left with a wide bandwidth to accommodate the different switching frequencies. This will require rolling off with an RC circuit, use the following equation: C COMP w i l l b e s e t t o 1 n F . T h i s p r o v i d e s a f r e q u e n c y breakpoint around the LC filter peak. It may be necessary to reduce the roll off further, this can be a choice of the designer but an example might be to start at 1/2 the LC filter peak frequency. This will affect the transient response time, something to note is the minimal phase delay in the COT topology and its fast re sponse compared to PWM converters. INDUCTOR SELECTION The choice of inductor is specific to each application and quickly determined with the following equations: and Where K is a percentage of maximum output current ripple required. The designer can quickly make a choice of inductor if the ripple percentage is decided, usually no more than 30 % however higher or lower percentages of I OUT can be acceptable depending on application. This device allows choices larger than 30 %. Other than the inductance th e DCR and satura tion current parameters are key values. The DCR causes an I 2R loss which will decrease the system efficiency and generate heat. The saturation current has to be higher than the maximum output current plus ½ of the ripple current. In an over current condition the inductor current may be very high. All this needs to be considered when selecting the inductor. On this board Vishay IHLP series inductors are used to meet cost requirement and high efficiency, a part that utilizes a material that has incredible saturation behaviour compared to competing products. INJECTION RX x CX= RX VIN - VOUT x VOUT VIN x fsw x CX x VINJECTION = VOUT VINJ L RX CX CY a b VINJECTION VIN_min. - VOUT x 1 - 1 e t INJ RCOMP L x C OUT CCOMP tON VOUT VIN_max. x fsw L VIN - VOUT x tON

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 14 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 OUTPUT CAPACITOR SELECTION Voltage rating, ESR, transient response, overall PCB area and cost are requirements for selecting output capacitors. The types of capacitors and there general advantages and disadvantages are covered next. Electrolytic have high ESR, dry out over time so ripple current rating must be examined and have slower transient response, but are fairly inexpensive for the amount of overall capacitance. Tantalums can come in low ESR varieties and high capacitance value for its overall size, but they fail short when damaged and also have slower transient response. Ceramics have very low ESR, fast transient response and overall small size, but come in low capacitance values compared to the others types. A combination of technology is sensible, however these co nverters suit an ceramic solution also. The output capacitance will be determined by the ripple voltage requirement. Voltage mode COT topology can work with very small values of capacitor ESR. The following equations are used to calculate the size needed to meet a transient load response: and Where I LPK is the peak inductor current, I MAX. is the maximum output current, dILOAD is the current step in μs and VPK is the peak voltage, the output voltage summed with the specified over and under shoot. The evaluation PCB is fitter with 66 μF. ENABLE PIN VOLTAGE The EN pin has an internal pull down resistor and only requires an enable voltage. This needs to be greater than 1.4 V. An input voltage or a resistor connected across V IN and EN can be used. The intern al pull down resistance is 5 M. SOFT START SETTING Soft start is a useful function helping to limit the current magnitude from the source at switch on. This is simply set with a ceramic capacitor using the following equation: A 100 nF capacitor will provide ~ 16 ms soft start time. V DD pin will need to be decoupled in order to provide a stable voltage internally and externally. The value for this capacitor is recommended as  1 μF. CURRENT LIMIT RESISTOR The current limit is set by placing a resistor between I LIM and AGND. The values can be found using the following equation: INPUT CAPACITANCE In order to keep the design compact and minimize parasitic elements, ceramic capacitors will be chosen. The initial requirement for the input capacitance is decided by the maximum input voltage, 60 V in this case however a 100 V rated capacitor will be chosen of the X7R variety. The footprint will be a compact 1206. In order to determine the mi nimum capacitance the input voltage ripple needs to be specified; V CINPP  500 mV is a suitable starting point. This magnitude is determined by the final application specification. The input current needs to be determined for the lowest operating input voltage, The minimum input capacitance can then be found, For output voltage greater than 5 V the input capacitance should be increased accordi ngly. As the output power increases so does the input voltage ripple, the evaluation PCB has 4.4 μF. Note

  • If the input voltage becomes very small then extra capacitance needs adding to the input as the ripple will affect the duty cycle calculation when larger current is required. ILPK Imax. + 0.5 x I RIPPLE_max.= COUT_min. ILPK x L x ILPK VOUT Imax 2 x dt dlLOAD tSS CSS x 0.8 RLIM 480 000 IOUT_max. ICIN RMS = IO x D x 1 D – 1 V OUT CIN_min. IOUT x D - 1 - D VCINPKPK x fsw

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 15 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) Fig. 10 - Efficiency vs. Output Current (VOUT = 12 V, fsw = 500 kHz) Fig. 11 - Efficiency vs. Output Current (VOUT = 5 V, fsw = 300 kHz) Fig. 12 - On Resistance vs. Junction Temperature Fig. 13 - Efficiency vs. Output Current (VOUT = 12 V, fsw = 500 kHz) Fig. 14 - Efficiency vs. Output Current (VOUT = 5 V, fsw = 300 kHz) Fig. 15 - Input Current vs. Junction Temperature 100 Efficiency (%) Output Current, IOUT (A) Complete converter efficiency P IN = [(VIN x IIN) + (VCIN x ICIN)] POUT = VOUT x IOUT, measured at output capacitor VIN = 36 V, L = 15 μH VIN = 48 V, L = 15 μH VIN = 24 V, L = 10 μH 100 Efficiency (%) Output Current, IOUT (A) Complete converter efficiency P IN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor Complete converter efficiency P IN = [(VIN x IIN) + (VCIN x ICIN)] POUT = VOUT x IOUT, measured at output capacitor VIN = 48 V, L = 8.2 μH VIN = 24 V, L = 10 μH VIN = 12 V, L = 8.2 μH VIN = 36 V, L = 15 μH -60 -40 -20 0 20 40 60 80 100 120 140 On-State Resistance, RDSON (mΩ) Temperature (°C) High side Low side 100 0.01 0.1 1 Efficiency (%) Output Current, IOUT (A) Complete converter efficiency P IN = [(VIN x IIN) + (VCIN x ICIN)] POUT = VOUT x IOUT, measured at output capacitor VIN = 36 V, L = 15 μH VIN = 48 V, L = 15 μH VIN = 24 V, L = 10 μH 100 0.01 0.1 1 Efficiency (%) Output Current, IOUT (A) Complete converter efficiency P IN = [(VIN x IIN) + (VCIN x ICIN)] POUT = VOUT x IOUT, measured at output capacitor VIN = 48 V, L = 8.2 μH VIN = 24 V, L = 10 μH VIN = 12 V, L = 8.2 μH VIN = 36 V, L = 15 μH 140 160 180 200 220 240 260 280 300 -60 -40 -20 0 20 40 60 80 100 120 140 Input Current, IVCIN + IVIN (μA) Temperature (°C)

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 16 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) Fig. 16 - Shutdown Current vs. Input Voltage Fig. 17 - Load Regulation, VOUT = 12 V Fig. 18 - EN Logic Threshold vs. Junction Temperature Fig. 19 - Shutdown Current vs. Junction Temperature Fig. 20 - Line Regulation, VOUT = 12 V Fig. 21 - EN Current vs. Junction Temperature 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 6 12 18 24 30 36 42 48 54 60 Shutdown Current, IVCIN_SHDN + IVIN_SHDN (μA) Input Voltage, VCIN / VIN (V) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 Load Regulation (%) Output Current (A) 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 EN Logic Threshold, VEN (V) Temperature (°C) VIH_EN VIL_EN 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 -60 -40 -20 0 20 40 60 80 100 120 140 Shutdown Current, IVCIN_SHDN + IVIN_SHDN (μA) Temperature (°C) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 20 25 30 35 40 45 50 55 60 Line Regulation (%) Input Voltage (V) 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -60 -40 -20 0 20 40 60 80 100 120 140 EN Current, IEN (μA) Temperature (°C) VEN = 5 V

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 17 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) Fig. 22 - Voltage Reference vs. Junction Temperature Fig. 23 - Start-Up with EN, Time = 1 ms/div Fig. 24 - Start-Up with VIN, Time = 5 ms/div Fig. 25 - Load Transient (3 A to 6 A), (6 A to 3 A), Time = 100 μs/div Fig. 26 - Line Transient (8 V to 48 V), Time = 10 ms/div Fig. 27 - Output Ripple 2 A, Time = 5 μs/div 792 794 796 798 800 802 804 806 808 -60 -40 -20 0 20 40 60 80 100 120 140 Voltage Reference, VFB (mV) Temperature (°C)

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 18 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) Fig. 28 - Output Ripple 300 mA, Time = 5 μs/div Fig. 29 - Output Ripple PSM, Time = 10 ms/ div

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 19 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PCB LAYOUT RECOMMENDATIONS Step 1: VIN/GND Planes and Decoupling Fig. 30 1. Layout VIN and PGND planes as shown above. 2. Ceramic capacitors shou ld be placed between V IN and PGND, and very close to the de vice for best decoupling effect. 3. Different values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210 and 0603. 4. Smaller capacitance values, placed closer to device’s V IN pin(s), is better for high frequency noise absorbing. Step 2: VCIN Pin Fig. 31 1. VCIN (pin 1) is the input pin for both internal LDO and tON block. T ON time varies based on input voltage. It’s necessary to put a decouplin g capacitor close to this pin. 2. The connection can be made through a via and the cap can be placed at bottom layer. Step 3: VSWH Plane Fig. 32 1. Connect output inductor to SiC462 with large plane to lower the resistance. 2. If any snubber network is required, place the components on the bottom side as shown above. Step 4: VDD/VDRV Input Filter Fig. 33 1. CVDD cap should be placed be tween pin 26 and pin 23 (the AGND of driver IC) to achieve best noise filtering. 2. CVDRV cap should be placed close to V DRV (pin 16) and PGND (pin 17) to reduce effe cts of trace impedance and provide maximum instantane ous driver current for low side MOSFET during switching cycle. VIN VSWH VIN Plane PGND Plane Vcin decouple cap AGND Plane PGND Plane VSWH Snubber AGND P G N D CVDD Cvdrv

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 20 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Step 5: BOOT Resistor and Capacitor Placement Fig. 34 1. These components need to be placed very close to SiC462, right between PHASE (pin 5, 6) and BOOT (pin 4). 2. In order to reduce para sitic inductance, it is recommended to use 0402 chip size for the resistor and the capacitor. Step 6: Signal Routing Fig. 35 1. Separate the small analog signal from high current path. As shown above, the high current paths with high dv/dt, di/dt are placed on the left side of the IC, while the small control signals are placed on the right side of the IC. All the components for small analog signal should be placed closer to IC with minimum trace length. 2. Pin 23 is the IC analog ground, which should have a single connection to power ground. The A GND ground plane connected with pin 23 helps keep AGND quiet and improve noise immunity. 3. Feedback signal can be routed through inner layer. Make sure this signal is far away from VSWH node and shielded by inner ground layer. 4. Ripple injection circuit can be placed next to inductor. Kelvin connection as shown above is recommended. CbootRboot PGND AGND plane F B s i g n a l Ripple injection circuit

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 21 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Step 7: Adding Thermal Relief Vias and Duplicate Power Path Plane Fig. 36 1. Thermal relief vias ca n be added on the V IN and P GND pads to utilize inner layers for high-current and thermal dissipation. 2. To achieve better thermal perf ormance, additional vias can be put on V IN and PGND plane. Also, it is necessary to duplicate the VIN and ground planes at bottom layer to maximize the power dissipation capability from PCB. 3. VSWH pad is a noise source and not recommended to put vias on this pad. 4. 8 mil drill for pads and 10 mils drill for plane are optional via sizes. The vias on pads may drain solder during assembly and cause assembly issues. Please consult with the assembly house for guidelines. Step 8: Ground Layer Fig. 37 1. It is recommended to make the entire inner layer (next to top layer) ground plane. 2. This ground plane provide s shielding between noise source on top layer and signal trace within inner layer. 3. The ground plane can be broken into two sections as PGND and AGND. VIN Plane PGND Plane VSWH PGND Plane AGND Plane

www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 22 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PACKAGE OUTLINE DRAWING PowerPAK® MLP55-27 Notes 1. Use millimeters as primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M - 1994 3. N is the number of terminals, Nd is the number of terminals in x-direction, and Ne is the number of terminals in y-direction 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals Vishay Siliconix maintains worldw ide manufacturing ca pability. Products may be manufactured at one of several qualified locatio ns. Reliability da ta for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / ta pe drawings, part marking, and reliability data, see www.vishay.com/ppg?65124. DIM. MILLIMETERS INCHES A1 0.00 - 0.05 0.000 - 0.002 A2 0.20 ref. 0.008 ref. b D 5.00 BSC 0.196 BSC e 0.50 BSC 0.019 BSC e1 0.65 BSC 0.0256 BSC E 5.00 BSC 0.196 BSC N (3) 28 28 F1 0.20 - 0.25 0.008 - 0.010 F2 0.20 min. 0.008 min. K 0.40 BSC 0.016 BSC K1 0.70 BSC 0.028 BSC K2 0.70 BSC 0.028 BSC K3 0.30 BSC 0.012 BSC Top view Side view Bottom view B A D E 2 x A 1 19 6 12 C x 7 119 C 1.225 1.000 D2-1 D2-3 D2-4 D2-2 E2-2 K2E2- E2-4 x 3 x 4 e e1 E2-1

0.080.10 C A

e e e1 K x 2 b 0.10 CAB eMLP55-27L (5 mm x 5 mm) e1e x 2

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