RAA457100GBM

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Document overview

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Technical content

Features

• Wireless battery charging - DC power supply to application system by high efficiency DCDC converter - Monitoring some pin voltages such as rectified output voltage, battery voltage by 12bit A/D converter - Modulation/Demodulation function for bi-directional communication between transmitter and receiver - Transmitter system(RAA458100) can read and write RAA457100 registers for setting charge control parameters - Function which converts wireless communication to 2-wrie serial communication for communication between transmitter and receiver application system - Battery protection, Low battery voltage detection 2. Block Diagram ( Example for Application Circuit ) BATTERY LDD C DD Power Supply SCL SDA *C IVCC R IVCC C VDDW C VDDB C CP2 C CP1 C CM1 C CM2 C SP C SS C RECT R ICHG RAA457100 Rx Main System Rx Coil C BAT R SCL C VCC R THM Low Battery Voltage Detection Discharge Over Voltage Detection Discharge Over Current Detection & Short Circuit Current Detection Tj_max Detection Step-Down DCDC Converter Control Logic DDEN SYS SDA SCL LX VCC THM BAT MODE CHG/INT COM1 COM2 CLMP1 CLMP2 VIN1 VIN2 COM CLMP Driver VDDW VDDB RIMON REG OSC RGND TEST Full Wave Rectifier RICHG GND ADC Battery Charge Control VCC Regulator REG D 1 NTC VDDW *C ICHG to R THM *R CM1 *R CM2 *R CP1 *R CP2 VCC VDDB BUZ MS DDST0 DDST1 ATR ATCHG ATPC GND VDDB DFET SD R SDA R BUZ R INT RMODE GPIO1 GPIO2 WRC *C THM *R RECT *Optional Parts *R DD to Control Logic to ADC C SGND *C SCL *C SDA RECT SGND 1. Product Outline

Page 2 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 3. Pin Functions Pin No. Pin Name A/D I/O Function Remark A6,B6,F4 GND - - Ground Connect to minus terminal of battery A1,B1 RGND - - Ground for Rectifier, Load modulation driver, Clamp driver Connect to minus terminal of battery B7,C7 SGND - - Ground for DCDC converter, application system Connected to discharge control FET on chip A5,B5 BAT A I/O Battery terminal Connect to plus terminal of battery A2 VIN1 A I Input terminal 1 to rectifier - B2 VIN2 A I Input terminal 2 to rectifier - A3,B3 RECT A I/O Rectified output terminal Connect C RECT between RECT and RGND C1 COM1 A O Load modulation driver output terminal 1 Connect C CM1 between COM1 and VIN1 F1 COM2 A O Load modulation driver output terminal 2 Connect C CM2 between COM2 and VIN2 D1 CLMP1 A O Clamp driver output terminal 1 Connect C CP1 between CLMP1 and VIN1 E1 CLMP2 A O Clamp driver output terminal 2 Connect C CP2 between CLMP2 and VIN2 D4 VDDB A O Regulated 3.0V output (inside usage) Connect C VDDB between VDDB and GND D5 VDDW A O Regulated 2.7V output (inside usage, reference voltage for thermistor) Connect C VDDW between VDDW and GND Connect to pull up resistor R THM of NTC thermistor A4,B4 VCC A O VCC regulator output (Power supply for DCDC converter) Connect C VCC between VCC and GND C4 RIMON A O External resistor connection for output current limit Monitor of VCC regulator output current Connect R IVCC between RIMON and GND C5 RICHG A O External resistor connection for current setting of constant current charging Connect R ICHG between RICHG and GND D6 THM A I Thermistor voltage input terminal Divided VDDW volta ge by R THM and NTC thermistor A7 LX A O DCDC converter switching output terminal - C6 SYS A I DCDC converter output voltage feedback terminal - E7 DDEN D I DCDC converter enable control terminal - D7 SD D I Shut down control terminal - E5 MODE D O Operation mode notification output Open drain E6 CHG/INT D O Charging status notification output/ Interruption signal output for Rx application system Open drain F7 BUZ D O Low battery voltage notification Open drain F3 MS D I Master or slave setting for 2-wire serial interface Connect to VDDB or GND F6 SCL D I/O Clock input or output for 2-wire serial interface Connect pullup resistor R SCL F5 SDA D I/O Data input or output for 2-wire serial interface Connect pullup resistor R SDA E2 DDST0 D I DCDC converter output voltage setting 1 Connect to V DDB or GND F2 DDST1 D I DCDC converter output voltage setting 2 Connect to V DDB or GND D2 ATR D I Enable automatic control of rectifier Connect to VDD B or GND D3 ATCHG D I Enable automatic start of battery charging Connect to VDDB or GND E3 ATPC D I Enable automatic transmission power control function Connect to VDDB or GND C3 WRC D I Enable contact battery charging Connect to GND in wi reless charging system C2 TEST - - Test only Connect to GND *1 A : Analog signal including power supply, D : Digital signal *2 I : Input terminal, O : Output terminal, I/O : Input and Output terminal 3. Pin Functions

Page 3 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 4. Pin Configuration 5. Absolute Maximum Ratings ( Tj=25[degC] unless otherwise noted. ) Item Symbol Value Unit Remark Pin voltage VIN1, VIN2, CLMP1, CLMP2, COM1, COM2, RECT 18 V BAT, VCC, SD, DDEN, CHG/INT, MODE, SDA, SCL -0.3 to 5 V RIMON, RICHG, THM, WRC, ATR, ATCHG, ATPC DDST0, DDST1, MS, TEST -0.3 to VDDB + 0.3 V SYS, BUZ -0.3 to VCC + 0.3 V 5V maximum Operating temperature Ta -20 to 50 degC Junction temperature Tj -20 to 70 degC Storage temperature Tstg -20 to 70 degC 6. Recommended Operating Conditions Item Symbol Value Unit Remark RECT pin voltage V RECT 3.5 to 6.0 V BAT pin voltage V BAT 3.2 to 4.35 V Bottom View (Ball Side) LX GND BAT VCC RECT VIN1 RGND SGND GND BAT VCC RECT VIN2 RGND SGND SYS RICHG RIMON WRC TEST COM1 SD THM VDDW VDDB ATCHG ATR CLMP1 DDEN CHG /INT MODE ATPC DDST0 CLMP2 BUZ SCL SDA GND MS DDST1 COM2 Top View LX GND BAT VCC RECT VIN1 RGND SGND GND BAT VCC RECT VIN2 RGND SGND SYS RICHG RIMON WRC TEST COM1 SD THM VDDW VDDB ATCHG ATR CLMP1 DDEN CHG /INT MODE ATPC DDST0 CLMP2 BUZ SCL SDA GND MS DDST1 COM2 4. Pin Configuration, 5. Absolute Maximum Ratings, 6. Recommended Operating Conditions

Page 4 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 7. Electrical Characteristics Tj=25[degC] unless otherwise noted. Item Symbol Condition min typ max Unit Rectified output voltage detection Rectified output voltage lower limit V RECT_UVLO VRECT is raised (hysteresis voltage 100mV) 2.9 3.0 3.1 V Rectified output voltage upper limit V RECT_OVD VRECT is raised (hysteresis voltage 7V) 13 14 15 V Circuit current Current at charge mode I RECT_CM VRECT =5V, V CC =no load - 1.0 2.0 mA Current at discharge mode I BAT_DM VRECT =0V, V BAT =3.8V, V CC =no load, MS=H - 25 - uA Current at shut down mode I BAT_SD VRECT =0V, V BAT =3.0V - 1 - uA Regulator for on chip circuit 3.0V regulator output voltage V DDB VRECT =5V, I SOURCE =1mA 2.85 3.00 3.15 V 2.7V regulator output voltage V DDW VRECT =5V, I SOURCE =30uA 2.60 2.70 2.80 V VCC regulator VCC regulator output voltage V CC VRECT =V BAT +500mV, V BAT =3.8V V BAT +0.2 V BAT +0.3 V BAT +0.4 V Output current I LIM - - 80 mA Battery charging Charge start voltage V START VBAT is raised (hysteresis voltage 100mV) - 1.5 - V Fast charge start voltage V QCHGON VBAT is raised (hysteresis voltage 100mV) - 3.0 - V Charge control voltage range V CHG 4.05, 4.20, 4.35 V Charge control voltage error V CHG_ERR IBAT =0.2 x I CHGR , R ICHG =5.6k Ω -50 - +50 mV Trickle charge current I PRECHG 0.1 x I CHGR - Trickle charge current error I PRECHG_ERR IBAT =0.1 x I CHGR , R ICHG =5.6k Ω -50 - +50 % Fast charge current range I CHG - - 70 mA Fast charge current error I CHG_ERR IBAT =0.5 x I CHGR , R ICHG =5.6k Ω -30 - +30 % Charge complete current range I FC 0.05 x I CHGR to 0.20 x I CHGR (0.05 x I CHGR step) - Charge complete current error I FC_ERR IBAT =0.2 x I CHGR , R ICHG =5.6k Ω -60 - +60 % Trickle charge timer range T DCHG 60, 120, 180 min Trickle charge timer error T DCHG_ERR - 10 - % Fast charge timer range T CHG 180, 240, 300, 360 min Fast charge timer error T CHG_ERR - 10 - % Battery protection Charge overvoltage detection voltage *1 V COVD BAT to GND differential voltage - V CHG +0.1 - V Charge overvoltage detection delay time TCOVD - 256 - ms Discharge short circuit current detection voltage V DSCD SGND to GND differential voltage - 160 - mV Discharge short circuit current detection delay time T DSCD - 250 - us Discharge overcurrent detection voltage VDOCD SGND to GND differential voltage - 80 - mV Discharge overcurrent detection delay time TDOCD - 4 - ms Discharge overvoltage detection voltage VDOVD BAT to GND differential voltage - 2.8 - V Discharge overvoltage detection delay time TDOVD - 32 - ms *1 Detection voltage is set to suitable temperature charge control voltage(VCHG )+0.1[V] regardless of thermistor temperature. 7. Electrical Characteristics

Page 5 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 7. Electrical Characteristics (continued) Tj=25[degC] unless otherwise noted. Item Symbol Condition min typ max Unit Low battery voltage detection Low battery detection voltage H V FGHD V VSYS =3.0V 3.45 3.55 3.65 Low battery detection voltage L V FGLD V VSYS =3.0V 3.25 3.35 3.45 Low battery voltage detection delay time TFGD - 256 - ms DCDC converter UVLO release voltage CC is raised) VDCDC_UVLO VSYS =1.2V,or 1.5V,or 1.8V (hysteresis voltage 100mV) 2.80 2.90 3.00 V VSYS =3.0V (hysteresis voltage120mV) 3.20 3.30 3.50 Output voltage range V SYS 1.2, 1.5, 1.8, 3.0 V Output current range I SYS Discharge mode - - 100 mA A/D converter Resolution ADC RES - 12 - bit WPT communication Bit rate from RX to TX BR RX2TX - 250 - bps Bit rate from TX to RX BR TX2RX - 125 - bps COM, CLAMP driver ON resistance R ON_DRV - 0.5 - Ω Leak current I L_DRV Pin voltage=15V - - 10 uA Discharge control FET ON resistance R ON_DFET - 0.4 - Ω Resistance between SGND and GND R SG VDOCD or V DSCD detection condition - 5 - k Ω SDA, SCL High level input voltage V IH_I2C 1.0 - - V Low level input voltage V IL_I2C - - 0.3 V Low level output voltage V OL_I2C ISINK =2mA - - 0.2 V MODE, CHG/INT, BUZ Low level output voltage V OL_OD ISINK =2mA - - 0.2 V Leak current I L_OD Pin voltage=3V - - 5 uA DDEN High level input voltage V IH_DDEN 1.0 - - V Low level input voltage V IL_DDEN - - 0.3 V SD High level input voltage V IH_SD 2.6 - - V Low level input voltage V IL_SD - - 0.3 V 7. Electrical Characteristics

Page 6 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 SD pin function RAA457100 has current switch(BFET) from BAT pin to the circuit of this IC. The current supplies from BAT pin to this IC through BFET when high level voltage is applied to SD pin. RAA457100 selects higher voltage either V BAT or V RECT for operating power of this IC. Detection delay time of SD pin voltage level is 1 second. Mode transition of this IC is operated dependent on SD detection signal. 8. Functions Description (The values described in this chapter are reference values, not guaranteed values.) VRECT < V RECT_UVLO & SD=L Detection VRECT < V RECT_UVLO & SD=L Detection

8.1 Operation Mode and SD Pin Function

The RAA457100 have shut down mode and charge mode 1 and charge mode 2, and discharge mode. Table 8.1.1 shows outline of each operating mode, Table 8.1.1 Outline of each operation mode Operating mode Description Shut down mode Major functions stop in this mode. The conditions in this mode are no power feed by wireless power transmission and battery, or VDDB voltage is lower than 2.5V. In discharge mode, the current from BAT pin to the circuit of this IC is shut down when low level voltage longer than 1 second is input to SD pin. In this state, if V RECT is lower than V RECT_UVLO , the operating mode changes shut down mode. Charge mode 1 This IC operates by rectified voltage in this mode. In discharge mode if V RECT is higher than VRECT_UVLO and VRECT is higher than VBAT , or in shut down mode if V RECT is higher than VRECT_UVLO , the operating mode changes into charge mode 1. Charge mode 2 In this mode, battery charging and WPT communication are available. In charge mode 1, if VRECT is higher than 4.5V, and V RECT is higher than VBAT +100mV, the operating mode changes charge mode 2. VCC regulator starts to operate. After VCC regulator starts, VCC regulator continues to operate in condition VRECT > VRECT_UVLO , V RECT < V RECT_OVLO , V RECT > VBAT +50mV. The transmission power should be controlled so that the rectified voltage is 0.5V higher than battery voltage. It means that charge control circuit and receiver main system can operate well. Discharge mode In this mode, this IC operates by battery power. In shut down mode, if high level voltage longer than 1 second is input to SD pin, the operating mode changes into discharge mode. Or in charging mode 1, if VRECT is lower than VRECT_UVLO and VBAT is higher than VRECT , the operating mode changes into discharge mode. Table 8.1.2 Function of each operation mode Operating mode Battery Protection *1 ADC , VDDW VCC regulator Charge control *2 DCDC converter *3 Shut down mode stop Charge mode 1 operate operate stop stop available Charge mode 2 operate operate operate available available Discharge mode operate stop stop stop available *1 Discharge control FET (DFET) becomes off if battery protection level is detected. *2 Battery charging is started automatically when operating mode become charge mode 2 if ATCHG pin level is high(VDDB). Battery charging can be started by register setting (0x01 D[0]=1) if ATCHG pin level is low. *3 DCDC converter is started when DDEN pin is high level and VCC > V DCDC_UVLO , and discharge control FET is on. Shut down mode Charge mode 1 (VCC regulator stop) Discharge mode Figure 8.1.1 Mode transition and SD pin function Symbol Description & Logical AND | Logical OR VBAT Battery voltage (BAT pin voltage) VRECT Rectified voltage (RECT pin voltage) VRECT_UVLO Rectified output undervoltage detection voltage VRECT_OVLO Rectified output overvoltage detection voltage SD=H Detection *1 High level voltage longer than 1 second is input to SD pin. SD=L Detection *1 Low level voltage longer than 1 second is input to SD pin. *1 This detection is operated in all operation mode. Charge mode 2 (VCC regulator operate) (V RECT > V RECT_OVLO ) | (V RECT < V RECT_UVLO ) | (V RECT < V BAT +50mV) ( V RECT > V RECT_UVLO & V BAT < V RECT & SD=H Detection ) | ( V RECT > V RECT_UVLO & SD=L Detection ) Charge mode Remark: RAA457100 is initialized by power on reset when VDDB voltage becomes low (typ. less than 2.5V).The operation mode changes shut down mode if RAA457100 becomes power on reset in charge mode 1 or charge mode 2 or discharge mode. ShutDown Mode & SD=H Detection VRECT < V RECT_UVLO & V BAT > V RECT & SD=H Detection ShutDown Mode & V RECT > V RECT_UVLO VRECT > 4.5V & V RECT > V BAT +100mV OFF ON OFF ON OFF 1 second SD pin voltage BFET ON/OFF status Shut down mode Discharge mode Shut down mode Operation mode less than 1 second 1 second SD=H Detection SD=L Detection 8. Functions Description

Page 7 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28

8.2 Rectifier

Rectifier converts AC voltage (recommended frequency is 125[kHz]) induced at resonant circuit to DC voltage. Figure 8.2.1 shows rectifier circuit. Rectified output (RECT pin) voltage rises in asynchronous rectifying operation by body diode of switch MOSFET. When rectified output voltage lower limit is detected （V RECT > V RECT_UVLO ）, the gate control circuit controls the high side switch depending on VIN1, VIN2, RECT pin voltages (half synchronous rectifying operation). When a current of the high side switch increases, the gate control circuit controls the low side switch too (full synchronous rectifying operation). A current of the high side switch depends on VCC regulator output current(I VCC ). When the voltage level of ATR pin and ATPC pin are high voltage, the operation function control depending on VCC regulator current are available in battery charge, such as rectifying operation(half synchronous, half or full synchronous automatically changed) and on-resistance of the high side switch. The settings of the rectifying operation and the on-resistance of the high side switch are five, and the current threshold of the VCC regulator output to change these settings can be set by register (show the register map). When ATR pin level is low voltage, the rectifying operation is half synchronous rectifying operation, and the on- resistance of the high side switch is 1[ Ω]. When the settings of the current threshold is not appropriate, rectifying operation becomes unstable (a change of half synchronous rectifying operation and full synchronous rectifying operation becomes unstable), and then ripple voltage of rectified voltage is increased. If the settings of the appropriate current threshold is difficult, it is recommended to set ATR pin level to low voltage. RAA457100 Gate Control RECT VIN1 VIN2 RGND High-Side SW Low-Side SW Figure 8.2.1 Rectifier circuit, and Rectifier action on ATR pin and ATPC pin = high

8.3 A/D Converter

In charge mode, some pin voltages (RECT pin voltage, BAT pin voltage, etc) are monitored by 12bit A/D converter. Table 8.3.1 shows monitor items of A/D converter. These items are monitored in 4[ms] period. These items are used by calculating parameters for automatic transmission power control and charging control (battery temperature, battery voltage). 2-wire serial interface and WPT communication make it possible to read the A/D conversion results. A/D conversion results in register are not updated automatically. When 0x35 D[0] is 1, all registers of A/D conversion result are updated. Table 8.3.1 Monitor items of A/D converter Item monitor point Output code *1 Input voltage range *2 (Actual voltage range) Register(12bit) Rectified output voltage RECT pin voltage V RECT ( 4096 / 10.8 ) x V RECT 0 to 10.8V ( 3.2 to 10 V ) 0x36 D[7:4] 0x37 D[7:0] VCC regulator output current （I VCC ） RIMON pin voltage V RIMON ( 4096 / 2.7 ) x V RIMON ( V RIMON = ( I VCC x R IVCC ) / K IVCC ) 0 to 2.7 V ( 0 to 1.2 V ) 0x38 D[7:4] 0x39 D[7:0] Battery voltage BAT pin voltage V BAT ( 4096 / 5.4 ) x V BAT 0 to 5.0 V ( 0 to 4.35 V ) 0x3A D[7:4] 0x3B D[7:0] Charging current （I CHG ） RICHG pin voltage V RICHG ( 4096 / 2.7 ) x V RICHG ( V RICHG = ( I CHG x R ICHG ) / K ICHG ) 0 to 2.7V ( 0 to 1.2 V ) 0x3C D[7:4] 0x3D D[7:0] Thermistor temperature (Battery temperature) THM pin voltage V THM ( 4096 / 2.7 ) x V THM 0 to 2.7 V ( 0 to 2.7 V ) 0x3E D[7:4] 0x3F D[7:0] *1 Output code range is from 0 to 4095. *2 Each inputted voltage should be within input voltage range to avoid miss converting. The voltage range in the parenthesis shows a voltage range assumed in practical use. Rectifier operation /on-resistance of high side switch VCC regulator current changing VCC output current threshold Register settings Initial (mA) Half synch/1[ Ω] - - - decreasing 0x1B D[7:0] 3.868 Full synch/8[ Ω] increasing 0x1B D[7:0] + 0x1F D[6:0] 7.736 decreasing 0x1C D[7:0] 8.087 Full synch/4[ Ω] increasing 0x1C D[7:0] + 0x1F D[6:0] 11.96 decreasing 0x1D D[7:0] 16.17 Full synch/2[ Ω] increasing 0x1D D[7:0] + 0x1F D[6:0] 20.04 decreasing 0x1E D[7:0] 31.99 Full synch/1[ Ω] increasing 0x1E D[7:0] + 0x1F D[6:0] 35.86 - - - 8. Functions Description

Page 8 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28

8.4 Power Supply to VCC Pin

Figure 8.4.1 shows block diagram of VCC regulator and battery charge control and charge control FET(CFET). Charge control FET is conductive in discharge mode and charge mode 1, current from battery flows into VCC pin. VCC regulator operates in charge mode 2. Current from RECT pin flows into VCC pin. When battery charging does not operate, CFET is off. In battery charging, the battery charge control circuit controls the gate voltage of CFET, charging current from VCC pin flows into BAT pin. VCC regulator regulates the voltage which is 3.3V to 4.8V depending on BAT pin voltage. VCC regulator has current limit function showed in Table 8.4.1. VCC regulator output voltage is changed depending on current no limit state or current limit state when charge control operates (Table 8.4.2). If VCC regulator is in current limit state, battery charging current is adjusted depending on limiting current (load current dividing function of charge control circuit). To prevent the current limit by low RECT pin voltage, the transmission power has to maintain recommended RECT pin voltage showed in Table 8.4.2. Table 8.4.2 VCC pin voltage BAT pin voltage (V BAT ) VCC pin voltage in charge control circuit operating RECT pin recommended voltage(V RECT ) *1 Current no limit state Current limit state 3.0V < VBAT < VCHG VBAT + 0.3V V BAT + 0.1V VRECT > V BAT ＋0.5V VBAT < 3.0V 3.3V 3.1V V RECT > 3.5V *1 This is the condition in order to avoid limiting the output current of VCC regulator by decreasing RECT pin voltage. Table 8.4.1 Current limit function of VCC regulator Item Description Current limit by R IVCC The maximum output current of VCC regulator can be set by external resistor RIVCC between RIMON pin and GND. The relation of R IVCC and output limiting current Limiting current ILIM = K IVCC x (1.2 / R IVCC ) Parameter KIVCC = 80 R IVCC = 1.2k Ω, or 2.4k Ω, or 4.8k Ω (prohibit using except recommended value *1 ) Current limit by low RECT pin voltage When the differential voltage between RECT pin and BAT pin is low, VCC regulator output current is limited. The output current starts to be limited on V RECT – VBAT < 0.4V, the output current decreases depending on the differential voltage. The output current is limited so that VRECT does not decrease than below voltage. RECT pin voltage when output current of VCC regulator is 0mA. VBAT > 3.0V V RECT = V BAT + 0.2V VBAT < 3.0V V RECT = 3.2V RAA457100 RECT VCC BAT VIN1 VIN2 RIMON Full Wave Rectifier RICHG Battery Charge Control VCC Regulator R ICHG GND Battery R IVCC Figure 8.4.1 Block diagram of VCC regulator and battery charge control and charge control FET RECTGND CFET Operation mode

Description

Discharge mode, Charge mode 1 CFET is always conductive, the current from battery flows into VCC pin. Charge mode 2 The power at RECT pin supplies to VCC pin by VCC regulator. CFET is off when charge control circuit does not charge. The charge control circuit controls gate voltage of CFET and the current flows from VCC pin to BAT pin in battery charging. 8. Functions Description

Page 9 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Figure 8.5.3 Charging profile

8.5.3 Charge Current, Charge Complete Current, Charge Control Voltage, Charge Timer

The maximum charge current is 70[mA]. Reference fast charge current I CHGR is set by resistor R ICHG between RICHG pin and GND. Pre-charge current and trickle charge current are set to one tenth(1/10) of reference fast charge current I CHGR . In soft start of fast charge, charging current increases stepped by (1/60)*I CHGR . The transition time of 1 step can be set by register. The fast charge current and the charge control voltage can be set to 3 values in each shows the parameters of charge current and charge complete current and charge control voltage, and charge timer. Table 8.5.3 Charge control parameters Item Symbol Value Unit Remark Reference fast charge current I CHGR 1.2 x K ICHG / R ICHG A K ICHG =80 Pre-charge current Trickle charge current I PRECHG 0.1 x I CHGR A - Fast charge current range *1 ICHG ICHGR , 0.5 x I CHGR , 0.25 x I CHGR A Register 0x02 D[7:2] Charge current transition step in soft start of fast charge I CHG_SOFT (1 / 60) x I CHGR A - Transition time of one step in soft start of fast charge T CHG_SOFT 15.625, 7.8125, 3.125 ms Register 0x02 D[1:0] Charge control voltage *1 VCHG 4.05 , 4.20 , 4.35 V Register 0x03 D[7:2] Charge complete current I FC 0.20 x I CHGR , 0.15 x I CHGR , 0.10 x I CHGR , 0.05 x I CHGR A Register 0x03 D[1:0] Charge complete judgement voltage V FC 3.8 V - Trickle charge timer T DCHG 60, 120, 180 min Register 0x04 D[1:0] Fast charge timer T CHG 180, 240, 300, 360 min Register 0x04 D[3:2] *1 It can be set in each battery temperature(low, suitable, high).

8.5 Battery Charge Control

8.5.1 Battery Charge Method

This IC has the charge function for Li-ion battery (constant current - constant voltage charge method). Some charge control parameters can be set by the registers. Table 8.5.2 Charge start voltage, Trickle to fast charge transition threshold voltage, Charge overvoltage detection voltage Item Detection voltage Detection delay time Charge start voltage *1 1.5V (hysteresis voltage 100mV) 256ms Trickle to fast charge transition threshold voltage 3.0V (hysteresis voltage 100mV) 256ms Charge overvoltage detection voltage *2 Suitable temperature charge control voltage +100mV 256ms *1 RAA457100 can charge to zero V battery by setting register D[7] in address 0x04. Battery voltage IPRECHG ICHG Charge current Fast charge Time VQCHGON Rise ：3.0V IFC VCHG complete Time VFC Charge complete current detection time Charge complete judgement Step up by (1/60)*I CHGR in soft start start Constant voltage charge Pre-charge Trickle charge

8.5.2 Charge Start Voltage, Trickle to Fast Charge Transition Threshold Voltage

and Charge Overvoltage Detection Voltage Table 8.5.2 shows charge start voltage and trickle to fast charge transition threshold voltage and charge overvoltage detection voltage, and detection delay time. These voltages are judged by control circuit using A/D conversion result of BAT pin voltage. 8. Functions Description

Page 10 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Suitable temperature THM_M Battery temperature Charge control voltage Constant current charging current Charge control ICHGR 0.25*I CHGR Low temperature THM_L High temperature THM_H THM_TH_H_HE (initial 45 [degC]) Charge pending in high temperature THM_H_ERR Charge pending in low temperature THM_L_ERR No battery THM_ NO_BAT VCV_THM_L （ 0x03 D[3:2] ） VCV_THM_M （ 0x03 D[5:4] ） ICC_THM_L （ 0x02 D[3:2] ） Normal charge ICC_THM_H （ 0x02 D[7:6] ） Charge control voltage can be set 4.05V or 4.20V or 4.35V by register in each battery temperature range. 4.05V 4.20V VCV_THM_H （ 0x03 D[7:6] ） Constant current charging current can be set 0.25*I CHGR or 0.5*I CHGR or ICHGR by register in each battery temperature range. ICC_THM_M （ 0x02 D[5:4] ） Low rate charge Low rate charge THM_TH_M_H (initial 40 [degC]) THM_TH_M_L (initial 10 [degC]) THM_TH_L_LE (initial 0 [degC]) 0.5*I CHGR THM_TH_LE_NB (=THM_TH_NB_LE + THM_TH_HYS) 4.35V Charge pending Charge pending THM_TH_NB_LE （initial -20 [degC]） THM_TH_LE_L (=THM_TH_L_LE - THM_TH_HYS) THM_TH_L_M (=THM_TH_M_L - THM_TH_HYS) THM_TH_H_M (=THM_TH_M_H + THM_TH_HYS ) THM_TH_HE_H (=THM_TH_H_HE + THM_TH_HYS) Charge pending Charge pending Battery temperature Battery temperature Figure 8.5.4 Battery temperature threshold, Charge control voltage, Constant current charge current 8. Functions Description

8.5.4 Battery Temperature Monitor

RAA457100 controls the fast charging current and the charge control voltage depending on battery temperature. The fast charging current and the charge control voltage can be set by registers in each temperature range. But the charge control voltage of low and high temperature range needs to be lower than the charge control voltage of suitable temperature range. The battery temperature range threshold can be set by registers that are THM_TH_NB_LE(no battery and charge pending in low temperature threshold), THM_TH_L_LE(low rate charge in low temperature and charge pending in low temperature threshold), THM_TH_M_L(normal charge and low rate charge in low temperature threshold), THM_TH_M_H(normal charge and low rate charge in high temperature threshold), THM_TH_H_HE(low rate charge in high temperature and charge pending in high temperature threshold), THM_TH_HYS(hysteresis) in address 0x05 to 0x0A. THM_TH_LE_NB(charge pending in low temperature and no battery threshold), THM_TH_LE_L(charge pending in low temperature and low rate charge in low temperature threshold), THM_TH_L_M(low rate charge in low temperature and normal charge threshold), THM_TH_H_M(low rate charge in high temperature and normal charge threshold), THM_TH_HE_H(charge pending in high temperature and low rate charge in high temperature threshold) are calculated by the registers described above. These registers are written initially by the value for NTC thermistor NCP03WF104F05RL, NCP15WF104F03RC (Murata Manufacturing) or an equivalent device. (refer to register map)

Page 11 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 All State RESET TIMER RESET TIMER RESET TIMER RESET TIMER RESET TIMER RESET TIMER RESET TIMER RESTART TIMER RESTART TIMER HOLD TIMER RESET TIMER Remark 1) Notation in flow chart : Judgement after the detection delay time Under line : Register Remark 2) Priority of branch (1) : Initial (0x0) (2) : No battery (0x6) (3) : Charge error 1 (0x7) (4 ): Charge error 2 (0x8) (5 ): Charge error 3 (0x9) (6 ): Other condition (1) (2) (3) (4) (5) RESET TIMER RESET TIMER CHG_POK=H and Release charge stop (CHG_EN=1 or ATCHG pin=H) and THM_AREA = THM_L, THM_M, THM_H and VBAT > V START *2 and VBAT < V CC VBAT > VCOVD or TJ > TSD Initial (0x0) CHG_POK=L *1 or Charge stop (CHG_EN=0 and ATCHG pin =L) Pre charge (0x1) Charge current IPRECHG Charge time 640ms VBAT < V QCHGON And VBAT < V CC VBAT > V QCHGON and VBAT < V CC Trickle charge (0x2) Trickle charge timer start Charge current IPRECHG VBAT < V QCHGON And VBAT < V CC VBAT > V QCHGON and VBAT < V CC Fast charge (0x3) *3 Fast charge timer start Soft start control Charge current I CHG Charge error 1 (0x7) All State Time out IBAT < IFC and FULMD=0 and VBAT < V CC VBAT < V START or THM_AREA = THM_NO_BAT No battery (0x6) VBAT > V START and THM_AREA ≠ THM_NO_BAT 0x4, 0x5, 0x7, 0x8, 0x9 Charge error 3 (0x9) Charge error 2 (0x8) THM_AREA = THM_H_ERR, THM_L_ERR THM_AREA = THM_H_ERR, THM_L_ERR 0x2 0x1, 0x3 HOLD TIMER VBAT < V QCHGON and VBAT < V CC VBAT > V QCHGON and VBAT < V CC THM_AREA = THM_L, THM_M, THM_H 0x2 0x3 Parameter Description CHG_POK Charge control available for IC VCC VCC pin voltage VBAT BAT pin voltage (battery voltage) IBAT BAT pin current (battery current) VQCHGON Trickle to fast charge transition threshold voltage (hysteresis voltage 100mV) VCOVD Charge overvoltage detection voltage VSTART Charge start voltage IFC Charge complete current VFC Charge complete judgement voltage(3.8V) Trickle charge timer time out 00 ：60 minute 01 ：120 minute 10 ：180 minute 11 ：180 minute Fast charge timer time out 00 ：180 minute 01 ：240 minute 10 ：300 minute 11 ：360 minute THM_AREA (Battery temperature range) Symbol Description THM_H_ERR High temperature pending THM_H Low rate charge in high temperature THM_M Normal charge THM_L Low rate charge in low temperature THM_L_ERR Low temperature pending THM_NO_BAT No battery Charge control can be started by setting D[7] to 1 in address 0x04 in spite of V BAT < V START . If CHG_POK=L is detected, CHG_EN register 0x01 D[0] is reset forcibly. Charge complete judgement (0x4) judgement time 1s Charge complete (0x5) RESET TIMER VBAT > V FC and VBAT < V CC VBAT < V FC and VBAT < V CC RESET TIMER

8.5.5 Charge State Transition Diagram

Fast charge current and charge control voltage can be changed at each temperature range . (THM_H, THM_M, THM_L) 8. Functions Description

Page 12 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28

8.6 Power Supply to Application System (Buck DCDC Converter, Battery Protection)

8.6.1 Buck DCDC Converter

The buck DCDC converter supplies power to application system. The input voltage of DCDC converter is VCC pin voltage. DCDC converter starts of DCDC converter can be monitored by registers. When 2-wire serial interface set into slave device by setting MS pin to low, an application system capacitor C DD is small, the output ripple voltage might be increased. If the DCDC converter output is unstable, series resistance R DD should be connected to output capacitor C DD for improvement (Refer to Block Diagram). Table 8.6.1.2 Registers related to DCDC converter Item Register Description VCC pin voltage detection (UVLO detection) 0x33 D[4] DCDC converter is controlled depending on VCC pin voltage level. 0 : Stop (UVLO detected) V CC < 2.80V(Output voltage is 1.2V or 1.5V or 1.8V) VCC < 3.18V(Output voltage is 3.0V) 1 : Start (UVLO release) VCC > 2.90V(Output voltage is 1.2V or 1.5V or 1.8V) VCC > 3.30V(Output voltage is 3.0V) Start up complete 0x33 D[5] DCDC converter confirms the completion of start up by monitoring SYS pin voltage. 0 : Low voltage status of SYS pin (V SYS < Setting output voltage x 0.831) 1 : Start up complete (VSYS > Setting output voltage x 0.875) Overvoltage detection of SYS pin 0x33 D[6] DCDC converter stops switching MOSFET if overvoltage is detected at SYS pin. 0 : Not detected (V SYS < Setting output voltage x 1.207) 1 : Detected (V SYS > Setting output voltage x 1.250) Overcurrent detection 0x33 D[7] 0x30 D[2] If overcurrent condition of DCDC converter is detected continuously, the status register is 1(0x33 D[7]=1). The delay time of detection is 8ms. *1 Interruption signal is output from CHG/INT pin when MS pin level is low and register 0x2F D[2] is 0. Table 8.6.1.1 DCDC converter output voltage settings Voltage input Enable pin DDST1 pin DDST0 pin Output vol tage VCC DDEN *1 L L 1.2V L H 1.5V H L 1.8V H H 3.0V *1 DCDC converter starts when DDEN pin level is high. If battery protection and junction temperature error and UVLO(V CC < V DCDC_UVLO ) is detected, DCDC converter is stopped.

8.6.2 Battery Protection, Maximum Junction Temperature Protection

Battery protection functions are discharge overvoltage protection and discharge overcurrent protection and discharge short circuit current protection. Temperature protection is maximum junction temperature protection. Table 8.6.2 shows protection detection threshold and detection delay time and post-processing. Table 8.6.2 Protection detection threshold, Detection delay time, Post-processing Item (Voltage for detection) Detection voltage / temperature Detection delay time Post-processing Discharge control FET Resistor between SGND and GND DCDC Converter *2 Digital input / output pins *3 Charge control Discharge overvoltage (between BAT and GND) 2.8V 32ms off disconnect suspend suspend - Discharge overcurrent (between SGND and GND) 80mV 4ms off connect suspend suspend - Discharge short circuit current (between SGND and GND) 160mV 250us off connect suspend suspend - Maximum junction temperature 68 degree C 256ms off disc onnect suspend suspend suspend *1 DCDC converter, discharge control FET and digital input/output pins restart automatically from suspend when each protection is released. *2 DCDC converter is also suspended when VCC pin voltage is lower than UVLO voltage(VDCDC_UVLO ). *3 MODE, CHG/INT, BUZ, SCL and SDA pins are applicable. 8. Functions Description

Page 13 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28

8.8 Charge Status Notification / Interrupt Signal Output (CHG / INT pin)

CHG / INT pin(open drain output) function is changed by MS pin setting. Table 8.8.1 shows this function. CHG / INT pin outputs low level when interruption event showed in Table 8.8.2 occurs and MS pin is low level. These interruption events can be masked by setting mask register showed in Table 8.8.3. Table 8.8.3 Interruption signal output mask register Item Mask register Description WPT communication receive notification 0x2F D[0] 0 : Interruption output available, 1 : Interruption output unavailable If all mask register are set by 1, CHG / INT pin function is as same as MS pin=H . Charge state transition notification 0x2F D[1] DCDC converter overcurrent detection 0x2F D[2] VCC regulator current limit detection 0x2F D[3] Table 8.8.1 CHG / INT pin function description MS pin Description L (GND) CHG / INT pin outputs low level when interruption event occurs (refer to Table 8.8.2). Application system can confirm interruption event factor by reading factor register after receiving that CHG / INT pin is low level . H (VDDB) CHG / INT pin outputs low level when charge control circuit status is pre-charge or trickle charge or fast charge. Table 8.8.2 Interruption signal output event Item Factor register Description WPT communication receive notification 0x30 D[0] WPT communication data is received from transmitter. The register is clear after reading. Charge state transition notification 0x30 D[1] Charge state transition. (Refer to charge state transition diagram) The register is clear after reading. DCDC converter overcurrent detection 0x30 D[2] DCDC converter detects overcurrent. This register is always set by 1 in overcurrent. VCC regulator current limit detection 0x30 D[3] VCC regulator limits output current. This register is always set by 1 in limiting current.

8.9 Charge Mode or Discharge Mode Notification (MODE pin)

MODE pin level depends on charge mode or discharge mode. Table 8.9 MODE pin function description MODE pin Description L MODE pin outputs low level in charge mode 1 or 2. If MODE pin connects to DDEN pin and DDEN connects VCC or VDDB via external resistor, DCDC converter stops in charge mode (Refer to block circuit). When register 0x00 D[0] is 1, MODE pin level is always high (Open drain output is off). H Mode pin outputs high level in discharge mode (Open drain output is off). Table 8.7 Battery low voltage notification Item DCDC converter output voltage Detection voltage Detection delay time Post-processing Battery low voltage detection H (between BAT and GND) 256ms BUZ pin outputs low level. When battery voltage becomes higher than detection voltage, BUZ pin returns high level. BUZ pin outputs pulse, 256[ms] low level pulse width in 2560[ms] period. 3.0V 3.55V Battery low voltage detection L (between BAT and GND) 1.2V, 1.5V, 1.8V 3.05V BUZ pin outputs pulse, 128[ms] low level pulse width in 1280[ms] period. 3.0V 3.35V

8.7 Battery Low Voltage Notification (BUZ pin)

Battery low voltage notification has two threshold voltages depending on DCDC converter output voltage. There are two ways of notice. BUZ pin (open drain output) outputs low level when battery low voltage H or battery low voltage L is detected and register 0x34 D[2] is 0. BUZ pin outputs specified pulse (show Table 8.7) when register 0x34 D[2] is 1. Battery low voltage detection result is also stored in register 0x34 D[1:0]. 8. Functions Description

Page 15 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28

8.11 WPT Communication and Rectified Output Overvoltage Protection

8.11.1 Outline

RAA457100 and RAA458100(Transmitter IC) support a bidirectional communication by amplitude modulation on wireless power transmission carrier signal. In receiver to transmitter communication, RAA457100 changes transmitting antenna voltage by load modulation and then RAA458100 detects the voltage variation and demodulates data. In transmitter to receiver communication, RAA458100 changes rectified voltage of RAA457100 by changing transmission power and then RAA457100 detects the voltage variation and demodulates data.

8.11.3 Data Transfer Function

RAA457100 modulates transmitting antenna voltage by switching COM1, COM2 driver (NMOS open drain) depending on transmission data. C CM1 between VIN1 pin and COM1 pin, and C CM2 between VIN2 pin and COM2 pin are connected or disconnected to GND by COM1 and COM2 driver. If peak current of COM driver needs to suppress, series resistor R CM1 , R CM2 need to be inserted. (Refer to Block diagram)

8.11.4 Data Receive Function

RAA457100 demodulates data packet showed in Figure 8.11.2 . RAA457100 detects rectified voltage variation depending on modulated signal from transmitter and demodulates. RAA458100 can read and write the register of RAA457100 by using the specific header code. Preamble (11bit) St Header (8bit) Pr Sp St Message1 (8bit) Pr Sp St Message2 (8bit) Pr Sp St Checksum (8bit) Pr Sp St : Start bit(1bit), Pr : Parity bit(1bit), Sp : Stop bit(1bit) Figure 8.11.2 Data packet format

8.11.2 Packet Format in WPT Communication

The packet of WPT communication is consisted of fixed data length packet including Preamble, Header, Message1, Message2, Checksum showed in Figure 8.11.2. The Header, Message1, Message2 have 1 bit of odd parity bit respectively, and the check sum generated by exclusive OR is added to the last of the packet. When ATPC pin level of RAA458100 and RAA457100 is high, automatic transmission power control function is available (ATPC Mode). In ATPC Mode, the packet which includes a special header code (0x00 to 0x0F) is sent from RAA457100 to RAA458100 periodically, and RAA458100 adjusts transmission power based on the data included in packet.

8.11.6 Rectified Output Overvoltage Protection(Clamp function)

When rectified output overvoltage(V RECT_OVD ) is detected, rectified voltage is suppressed by clamp function. Connect C CP1 between VIN1 pin and CLMP1 pin, and C CP2 between VIN2 pin and CLMP2 pin. These capacitors are connected between VIN1 pin, VIN2 pin and GND by clamp driver of CLMP1pin and CLMP2 pin(NMOS open drain), then rectified voltage is suppressed. If peak current of clamp driver needs to suppress, series resistor R CP1 , R CP2 need to be inserted. (Refer to Block diagram)

8.11.5 Communication Bit Rate

Table 8.11.5 shows communication bit rate. The transmission data rate is 250[bps], the reception data rate is 125[bps]. Table 8.11.5 Communication bit rate Communication direction Bit rate Remark Data transmission (Receiver to transmitter) 250bps Data reception (Transmitter to receiver) 125bps Table 8.11.2 Header code Header code Description 0x00 to 0x0F Header code for automatic transmission power control function (ATPC Mode) 0x10 to 0xFF Header code for any user purpose

8.12 Wired Charging Function (WRC pin)

RAA457100 can charge not only by wireless but also by wire. Wireless or wired charging is selectable by voltage level of WRC pin. (Refer to Table 8.12) Table 8.12 WRC pin function WRC pin level Description L (GND) Wireless charging is selected using RAA457100 and RAA458100. H (VDDB) Wired charging is selected using RAA457100 only. 5 V DC should be supplied to RECT pin. 8. Functions Description

Page 16 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 9. Register Map (The values described in this chapter are reference values, not guaranteed values.) Address Bit No. Register Name Init R/W Description 0x00 D0 MODE_OFF 0 R/W MODE pin output disable 0 : Enable 1 : Disable(NMOS Tr OFF usually) D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x01 D0 CHG_EN 0 R/W Charge start enable 0 : Charge stop(Init ialize charging flow) 1 : Charge start D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x02 D0 TCC_SOFT[0] 0 R/W Trickle to fast charging transition time(per one step) 0 : 15.625[ms] 1 : 7.8125[ms] 2 : 3.125[ms] 3 : Unused D1 TCC_SOFT[1] 0 R/W D2 ICC_THM_L[0] 1 R/W Fast charge current setting of low temperature operation in battery temperature profile 0 : ICHGR 1 : 0.5*ICHGR 2 : 0.25*ICHGR 3 : 0.25*ICHGR D3 ICC_THM_L[1] 0 R/W D4 ICC_THM_M[0] 1 R/W Fast charge current setting of suitable temperature operation in battery temperature profile 0 : ICHGR 1 : 0.5*ICHGR 2 : 0.25*ICHGR 3 : 0.25*ICHGR D5 ICC_THM_M[1] 0 R/W D6 ICC_THM_H[0] 1 R/W Fast charge current setting of high temperature operation in battery temperature profile 0 : ICHGR 1 : 0.5*ICHGR 2 : 0.25*ICHGR 3 : 0.25*ICHGR D7 ICC_THM_H[1] 0 R/W 0x03 D0 ICV_FIN[0] 0 R/W Constant voltage charge complete current setting 0 : 0.1*ICHGR 1 : 0.05*ICHGR 2 : 0.15*ICHGR 3 : 0.2*ICHGR D1 ICV_FIN[1] 0 R/W D2 VCV_THM_L[0] 0 R/W Constant voltage charge control voltage setting of low temperature operation in battery temperature profile D4 VCV_THM_M[0] 1 R/W Constant voltage charge control voltage setting of suitable temperature operation in battery temperature profile D6 VCV_THM_H[0] 0 R/W Constant voltage charge control voltage setting of high temperature operation in battery temperature profile 0x04 D0 TIM_CHG_TRKL[0] 1 R/W Trickle charge timer setting 0 : 60[min] 1 : 120[min] 2 : 180[min] 3 : 180[min] D1 TIM_CHG_TRKL[1] 1 R/W D2 TIM_CHG_CCCV[0] 1 R/W Fast charge timer setting 0：180[min] 1：240[min] 2：300[min] 3：360[min] D3 TIM_CHG_CCCV[1] 1 R/W D4 TIM_CHG_STOP 0 R/W Charge control timer halt setting 0 : Count 1 : Halt D5 0 R D6 FULMD 0 R/W 0 : Normal operation 1 : Full charge mod e (Charge is continued in spite of detecting charge complete current) D7 VCHG_ST_0V 0 R/W Charge start threshold voltage 0 : 1 .5[V] 1 : 0[V] 0x05 D0 THM_TH_H_HE[0] 1 R/W Transition temperature setting of High temperature low rate charge to Charge pending in high temperature : THM_TH_H_HE 5.273[mV/code] { 0, THM_TH_H_HE[7:0], 000 } and 12 bit A/D convertedvalue of THM pin voltage are compared. The value higher than 25[degC] including hysteresis can be set (because of MSB=0 fixed) Initial value : 45[degC] at NTC thermistor NCP03WF104F05RL(Murata Manufacturing) (9bit resolution, 153 x 5.273=806.7[mV] at THM pin voltage ) Transition temperature of Charge pending in high temperature to High temperature low rate charge : THM_TH_HE_H is calculated by { 0, THM_TH_H_HE[7:0], 000 } + { 0000, THM_TH_HYS[4:0], 000 } Register value is applied by 0x0A D[7]=1 D1 THM_TH_H_HE[1] 0 R/W D2 THM_TH_H_HE[2] 0 R/W D3 THM_TH_H_HE[3] 1 R/W D4 THM_TH_H_HE[4] 1 R/W D5 THM_TH_H_HE[5] 0 R/W D6 THM_TH_H_HE[6] 0 R/W D7 THM_TH_H_HE[7] 1 R/W 0x06 D0 THM_TH_M_H[0] 1 R/W Transition temperature setting of Suitable temperature charge to High temperature low rate charge : THM_TH_M_H 5.273[mV/code] { 0, THM_TH_M_H[7:0], 000 } and 12 bit A/D converted value of THM pin voltage are compared. The value higher than 25[degC] including hysteresis can be set (because of MSB=0 fixed) Initial value : 40[degC] at NTC thermistor NCP03WF104F05RL(Murata Manufacturing) (9bit resolution, 177 x 5.273=933.3[mV] at THM pin voltage ) Transition temperature of High temperature low rate charge to Suitable temperature charge : THM_TH_H_M is calculated by { 0, THM_TH_M_H[7:0], 000 } + { 0000, THM_TH_HYS[4:0], 000 } Register value is applied by 0x0A D[7]=1 D1 THM_TH_M_H[1] 0 R/W D2 THM_TH_M_H[2] 0 R/W D3 THM_TH_M_H[3] 0 R/W D4 THM_TH_M_H[4] 1 R/W D5 THM_TH_M_H[5] 1 R/W D6 THM_TH_M_H[6] 0 R/W D7 THM_TH_M_H[7] 1 R/W 0x07 D0 THM_TH_M_L[0] 0 R/W Transition temperature setting of S uitable temperature charge to Low temperature low rate charge : THM_TH_M_L 5.273[mV/code] { 1, THM_TH_M_L[7:0], 000 } and 12 bit A/D converted value of THM pin voltage are compared. The value less than 25[degC] including hysteresis can be set (because of MSB=1 fixed) Initial value : 10[degC] at NTC thermistor NCP03WF104F05RL(Murata Manufacturing) (9bit resolution, (256+86) x 5.273=1803[mV] at THM pin voltage ） Transition temperature of Low temperature low rate charge to Suitable temperature charge : THM_TH_L_M is calculated by { 1, THM_TH_M_L[7:0], 000 } – { 0000, THM_TH_HYS[4:0], 000 } Register value is applied by 0x0A D[7]=1 D1 THM_TH_M_L[1] 1 R/W D2 THM_TH_M_L[2] 1 R/W D3 THM_TH_M_L[3] 0 R/W D4 THM_TH_M_L[4] 1 R/W D5 THM_TH_M_L[5] 0 R/W D6 THM_TH_M_L[6] 1 R/W D7 THM_TH_M_L[7] 0 R/W 9.1 Address 0x00 to 0x07 (Transmitter system can write to these register.) 9. Register Map

Page 17 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x08 D0 THM_TH_L_LE[0] 0 R/W Transition temperature setting of Low temperature low rate charge to Charge pending in low temperature : THM_TH_L_LE 5.273[mV/code] { 1, THM_TH_L_LE[7:0], 000 } and 12 bit A/D converted value of THM pin voltage are compared. The value less than 25[degC] including hysteresis can be set (because of MSB=1 fixed) Initial value : 0[degC] at NTC thermistor NCP03WF104F05RL(Murata Manufacturing) (9bit resolution, (256+140) x 5.273=2088[mV] at THM pin voltage ） Transition temperature of Charge pending in low temperature to Low temperature low rate charge : THM_TH_LE_L is calculated by { 1, THM_TH_L_LE[7:0], 000 } – { 0000, THM_TH_HYS[4:0], 000 } Register value applied by 0x0A D[7]=1. D1 THM_TH_L_LE[1] 0 R/W D2 THM_TH_L_LE[2] 1 R/W D3 THM_TH_L_LE[3] 1 R/W D4 THM_TH_L_LE[4] 0 R/W D5 THM_TH_L_LE[5] 0 R/W D6 THM_TH_L_LE[6] 0 R/W D7 THM_TH_L_LE[7] 1 R/W 0x09 D0 THM_TH_NB_LE[0] 0 R/W Transition temperature setting of No battery to Charge pending in low temperature : THM_TH_NB_LE 5.273[mV/code] { 1, THM_TH_NB_LE[7:0], 000 } and 12 bit A/D converted value of THM pin voltage are compared. The value less than 25[degC] including hysteresis can be set (because of MSB=1 fixed) Initial value : -20[degC] at NTC thermistor NCP03WF104F05RL(Murata Manufacturing) (9bit resolution, (256+212) x 5.273=2467[mV] at THM pin voltage) Transition temperature of Charge pending in low temperature to No battery : THM_TH_LE_NB is calculated by { 1, THM_TH_NB_LE[7:0], 000 } + { 0000, THM_TH_HYS[4:0], 000 } Register value applied by 0x0A D[7]=1. D1 THM_TH_NB_LE[1] 0 R/W D2 THM_TH_NB_LE[2] 1 R/W D3 THM_TH_NB_LE[3] 0 R/W D4 THM_TH_NB_LE[4] 1 R/W D5 THM_TH_NB_LE[5] 0 R/W D6 THM_TH_NB_LE[6] 1 R/W D7 THM_TH_NB_LE[7] 1 R/W 0x0A D0 THM_TH_HYS[0] 0 R/W Battery transition temperature sett ing : Hysteresis 5.273[mV/code] Initial value : 3[degC] around (Hysteresis depend on temperature because of non linearity of thermistor) (9bit resolution, 18 x 5.273=94.91[mV] at THM pin voltage) THM_TH_HE_H, THM_TH_H_M, THM_TH_L_M, THM_TH_LE_L, T HM_TH_LE_NB are calculated by adding this to 0x05 to 0x09 or subtracting this from 0x05 to 0x09. Register value applied by 0x0A D[7]=1. D1 THM_TH_HYS[1] 1 R/W D2 THM_TH_HYS[2] 0 R/W D3 THM_TH_HYS[3] 0 R/W D4 THM_TH_HYS[4] 1 R/W D5 0 R D6 0 R D7 THM_TH_UPLOAD 0 R/W 1 : Transition temperature register values (0x05 to 0x0A ) are applied. This register is reset after applying. 0x0B D0 I2C_TRIG 0 R/W 2-wire I/F communication trigger 0 : St and-by state 1 : Communication start (When MS pin is high level ) D1 I2C_READ 0 R/W 2-wire I/F Write/Read selection 0 : Writ e 1 : Read (When MS pin is high level ) D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x0C D0 I2C_SLV_ADRS[0] 0 R/W Slave address setting for 2-wire I/F of receiver application device (When MS pin is high level ) D1 I2C_SLV_ADRS[1] 0 R/W D2 I2C_SLV_ADRS[2] 0 R/W D3 I2C_SLV_ADRS[3] 0 R/W D4 I2C_SLV_ADRS[4] 0 R/W D5 I2C_SLV_ADRS[5] 0 R/W D6 I2C_SLV_ADRS[6] 0 R/W D7 0 R 0x0D D0 I2C_REG_ADRS[0] 0 R/W Register address setting for 2-wir e I/F of receiver application device (When MS pin is high level ) D1 I2C_REG_ADRS[1] 0 R/W D2 I2C_REG_ADRS[2] 0 R/W D3 I2C_REG_ADRS[3] 0 R/W D4 I2C_REG_ADRS[4] 0 R/W D5 I2C_REG_ADRS[5] 0 R/W D6 I2C_REG_ADRS[6] 0 R/W D7 I2C_REG_ADRS[7] 0 R/W 0x0E D0 I2C_W_DATA[0] 0 R/W Write data setting for 2-wire I/F o f receiver application device (When MS pin is high level ) D1 I2C_W_DATA[1] 0 R/W D2 I2C_W_DATA[2] 0 R/W D3 I2C_W_DATA[3] 0 R/W D4 I2C_W_DATA[4] 0 R/W D5 I2C_W_DATA[5] 0 R/W D6 I2C_W_DATA[6] 0 R/W D7 I2C_W_DATA[7] 0 R/W 0x0F D0 I2C_R_DATA[0] 0 R Read data for 2-wire I/F of receiver application device (When MS pin is high level) D1 I2C_R_DATA[1] 0 R D2 I2C_R_DATA[2] 0 R D3 I2C_R_DATA[3] 0 R D4 I2C_R_DATA[4] 0 R D5 I2C_R_DATA[5] 0 R D6 I2C_R_DATA[6] 0 R D7 I2C_R_DATA[7] 0 R 9.2 Address 0x08 to 0x0F (Transmitter system can write to these register.) 9. Register Map

Page 18 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x10 D0 ATPCRX_INTERVAL 0 R/W Rx to Tx WPT communication period( ATPC Mode) 0:1[s]/2[s] 1:2[s]/4[s] (Identification, Configuration / Battery Charge) D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x11 D0 ATPCRX_CTRL_ERR_OFS1[0] 0 R/W Control error calculatio n offset ΔV1 (ATPC Mode) ΔV1 is applied to offset voltage in condition of fast charge state and ICHG > 0.2C 10.547[mV/code] Initial value : 48 (48x10.547=506.26[mV]) D1 ATPCRX_CTRL_ERR_OFS1[1] 0 R/W D2 ATPCRX_CTRL_ERR_OFS1[2] 0 R/W D3 ATPCRX_CTRL_ERR_OFS1[3] 0 R/W D4 ATPCRX_CTRL_ERR_OFS1[4] 1 R/W D5 ATPCRX_CTRL_ERR_OFS1[5] 1 R/W D6 ATPCRX_CTRL_ERR_OFS1[6] 0 R/W D7 ATPCRX_CTRL_ERR_OFS1[7] 0 R/W 0x12 D0 ATPCRX_CTRL_ERR_OFS2[0] 0 R/W Control error calculatio n offset ΔV2 (ATPC Mode) ΔV2 is applied to offset voltage in condition of no fast charge state or (fast charge state & ICHG < 0.15C ) 10.547[mV/code] Initial value : 144 (144x10.547=1518.77[mV]) D1 ATPCRX_CTRL_ERR_OFS2[1] 0 R/W D2 ATPCRX_CTRL_ERR_OFS2[2] 0 R/W D3 ATPCRX_CTRL_ERR_OFS2[3] 0 R/W D4 ATPCRX_CTRL_ERR_OFS2[4] 1 R/W D5 ATPCRX_CTRL_ERR_OFS2[5] 0 R/W D6 ATPCRX_CTRL_ERR_OFS2[6] 0 R/W D7 ATPCRX_CTRL_ERR_OFS2[7] 1 R/W 0x13 D0 ATPCRX_CTRL_ERR_TH[0] 0 R/W Control error convergence judgement threshold (ATPC Mode) 10.547[mV/code] Initial value : 10 (10x10.547=105.47[mV]) D1 ATPCRX_CTRL_ERR_TH[1] 1 R/W D2 ATPCRX_CTRL_ERR_TH[2] 0 R/W D3 ATPCRX_CTRL_ERR_TH[3] 1 R/W D4 ATPCRX_CTRL_ERR_TH[4] 0 R/W D5 ATPCRX_CTRL_ERR_TH[5] 0 R/W D6 ATPCRX_CTRL_ERR_TH[6] 0 R/W D7 ATPCRX_CTRL_ERR_TH[7] 0 R/W 0x14 D0 ATPCRX_NCTRL_ERR_TH[0] 0 R/W Control error non-conver gence judgement threshold (ATPC Mode) 1[count/code] Initial value : 32 (32x1=32[count]) D1 ATPCRX_NCTRL_ERR_TH[1] 0 R/W D2 ATPCRX_NCTRL_ERR_TH[2] 0 R/W D3 ATPCRX_NCTRL_ERR_TH[3] 0 R/W D4 ATPCRX_NCTRL_ERR_TH[4] 0 R/W D5 ATPCRX_NCTRL_ERR_TH[5] 1 R/W D6 ATPCRX_NCTRL_ERR_TH[6] 0 R/W D7 ATPCRX_NCTRL_ERR_TH[7] 0 R/W 0x15 D0 WPT_R_CNT_OVER_ERR[0] 0 R/W Bit number threshold for error judgement when WPT data is received. (ATPC Mode) 0 : 4[bit] 1 : 1[bit] 2 : 2[bit] 3 : 8[bit] 4 : 16[bit] 5 : 32[bit] 6 : 48[bit] 7 : 63[bit] D1 WPT_R_CNT_OVER_ERR[1] 0 R/W D2 WPT_R_CNT_OVER_ERR[2] 0 R/W D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x16 D0 VRECT_CMP_TH[0] 0 R/W Differential value threshold of AD converted data(VRECT) (ATPC Mode) 2.637[mV/code] (RECT pin voltage, 12bit resolution) Initial value : 32 (32 x 2.637=84.38[mV]) D1 VRECT_CMP_TH[1] 0 R/W D2 VRECT_CMP_TH[2] 0 R/W D3 VRECT_CMP_TH[3] 0 R/W D4 VRECT_CMP_TH[4] 0 R/W D5 VRECT_CMP_TH[5] 1 R/W D6 VRECT_CMP_TH[6] 0 R/W D7 VRECT_CMP_TH[7] 0 R/W 0x17 D0 IVCC_CMP_TH[0] 0 R/W Differential value threshold of AD converted data(IVCC) (ATPC Mode) 43.945[uA/code] @ RIVCC=1.2[k Ω] (VCC regulator output current(IVCC), 12bit resolution) 21.972[uA/code] @ RIVCC=2.4[k Ω] (VCC regulator output current(IVCC), 12bit resolution) 10.986[uA/code] @ RIVCC=4.8[k Ω] (VCC regulator output current(IVCC), 12bit resolution) 0.6592[mV/code] (RIMON pin voltage, 12bit resolution) Initial value : 64 ( 64 x 43.945[uA/code]=2812[uA] @ RIVCC=1.2[kΩ], 64 x 21.972[uA/code]=1406[uA] @ RIVCC=2.4[kΩ], 64 x 10.986[uA/code]=703.1[uA] @ RIVCC=4.8[kΩ] ) D1 IVCC_CMP_TH[1] 0 R/W D2 IVCC_CMP_TH[2] 0 R/W D3 IVCC_CMP_TH[3] 0 R/W D4 IVCC_CMP_TH[4] 0 R/W D5 IVCC_CMP_TH[5] 0 R/W D6 IVCC_CMP_TH[6] 1 R/W D7 IVCC_CMP_TH[7] 0 R/W

9.3 Address 0x10 to 0x17

1. Register Map

Page 19 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x18 D0 VBAT_CMP_TH[0] 0 R/W Differential value threshold of AD converted data(VBAT) (ATPC Mode) 1.318[mV/code] (BAT pin voltage, 12bit resolution) Initial value : 32 (32 x 1.318=42.18[mV]) D1 VBAT_CMP_TH[1] 0 R/W D2 VBAT_CMP_TH[2] 0 R/W D3 VBAT_CMP_TH[3] 0 R/W D4 VBAT_CMP_TH[4] 0 R/W D5 VBAT_CMP_TH[5] 1 R/W D6 VBAT_CMP_TH[6] 0 R/W D7 VBAT_CMP_TH[7] 0 R/W 0x19 D0 RIMON_RESISTOR[0] 0 R Connected resistance detection result at RIMON pin 0 : 1.2[k Ω] 1 : 2.4[k Ω] 2 : 4.8[k Ω] 3 : Error D1 RIMON_RESISTOR[1] 0 R D2 0 R D3 0 R D4 ATPC_PHASE[0] 0 R ATPC Phase (operation status of ATPC Mode) monitor 0 : Ping 1 : Identification 2 : Configuration 3 : Battery Charge D5 ATPC_PHASE[1] 0 R D6 0 R D7 0 R 0x1A D0 RECT_PSA[0] 0 R/W On resistance setting of high side switch in rectifier (Available in 0x1A D[3]=1) D2 RECT_FULLSYNC_EN 0 R/W 0 : Half synchronous operation 1 : Half or full synchronous automatic change operation (Available in 0x1A D[3]=1) D3 RECT_SW_FORCE 0 R/W 1 : On resistance register setting mo de of high side switch in rectifier D4 ATR_RECT_PSA[0] 0 R On resistance setting monitor of rectifier high-side switch 0 : 1[ Ω] 1 : 2[ Ω] 2 : 4[ Ω] 3 : 8[ Ω]D5 ATR_RECT_PSA[1] 0 R D6 ATR_RECT_FULLSYNC_EN 0 R Rectifier operation monitor 0 : Half synchronous operation 1 : Half or full synchronous automatic change operation D7 0 R 0x1B D0 RECT_TH_FS8_HS1[0] 1 R/W VCC regulator output current threshold 1 (decreasing) for switching the rectifier operation in ATPC pin and ATR pin = H This value is compared by A/D converted result of RIMON pin voltage. 0.3516[mA/code] (VCC regulator output current(IVCC), not depending on RIMON resistance) 9bit resolution in setting of RIVCC=1.2[kΩ], 2.4[kΩ], 4.8[kΩ] Initial value : 11 (11 x 0.3516=3.868[mA]) Register value is applied by 0x1F D[7]=1. D1 RECT_TH_FS8_HS1[1] 1 R/W D2 RECT_TH_FS8_HS1[2] 0 R/W D3 RECT_TH_FS8_HS1[3] 1 R/W D4 RECT_TH_FS8_HS1[4] 0 R/W D5 RECT_TH_FS8_HS1[5] 0 R/W D6 RECT_TH_FS8_HS1[6] 0 R/W D7 RECT_TH_FS8_HS1[7] 0 R/W 0x1C D0 RECT_TH_FS4_FS8[0] 1 R/W VCC regulator output current threshold 2 (decreasing) for switching the rectifier operation in ATPC pin and ATR pin = H This value is compared by A/D converted result of RIMON pin voltage. 0.3516[mA/code] (VCC regulator output current(IVCC), not depending on RIMON resistance) 9bit resolution in setting of RIVCC=1.2[kΩ], 2.4[kΩ], 4.8[kΩ] Initial value : 23 (23 x 0.3516=8.087[mA]) Register value is applied by 0x1F D[7]=1. D1 RECT_TH_FS4_FS8[1] 1 R/W D2 RECT_TH_FS4_FS8[2] 1 R/W D3 RECT_TH_FS4_FS8[3] 0 R/W D4 RECT_TH_FS4_FS8[4] 1 R/W D5 RECT_TH_FS4_FS8[5] 0 R/W D6 RECT_TH_FS4_FS8[6] 0 R/W D7 RECT_TH_FS4_FS8[7] 0 R/W 0x1D D0 RECT_TH_FS2_FS4[0] 0 R/W VCC regulator output current threshold 3 (decreasing) for switching the rectifier operation in ATPC pin and ATR pin = H This value is compared by A/D converted result of RIMON pin voltage. 0.3516[mA/code] (VCC regulator output current(IVCC), not depending on RIMON resistance) 9bit resolution in setting of RIVCC=1.2[kΩ], 2.4[kΩ], 4.8[kΩ] Initial value : 46 (46 x 0.3516=16.17[mA]) Register value is applied by 0x1F D[7]=1. D1 RECT_TH_FS2_FS4[1] 1 R/W D2 RECT_TH_FS2_FS4[2] 1 R/W D3 RECT_TH_FS2_FS4[3] 1 R/W D4 RECT_TH_FS2_FS4[4] 0 R/W D5 RECT_TH_FS2_FS4[5] 1 R/W D6 RECT_TH_FS2_FS4[6] 0 R/W D7 RECT_TH_FS2_FS4[7] 0 R/W 0x1E D0 RECT_TH_FS1_FS2[0] 1 R/W VCC regulator output current threshold 4 (decreasing) for switching the rectifier operation in ATPC pin and ATR pin = H This value is compared by A/D converted result of RIMON pin voltage. 0.3516[mA/code] (VCC regulator output current(IVCC), not depending on RIMON resistance) 9bit resolution in setting of RIVCC=1.2[kΩ], 2.4[kΩ], 4.8[kΩ] Initial value : 91 (91 x 0.3516=31.99[mA]) Register value is applied by 0x1F D[7]=1. D1 RECT_TH_FS1_FS2[1] 1 R/W D2 RECT_TH_FS1_FS2[2] 0 R/W D3 RECT_TH_FS1_FS2[3] 1 R/W D4 RECT_TH_FS1_FS2[4] 1 R/W D5 RECT_TH_FS1_FS2[5] 0 R/W D6 RECT_TH_FS1_FS2[6] 1 R/W D7 RECT_TH_FS1_FS2[7] 0 R/W 0x1F D0 RECT_TH_HYS[0] 1 R/W VCC regulator output current thr eshold (hysteresis) for switching the rectifier operation in ATPC pin and ATR pin = H Increasing current threshold is calculated by decreasing current threshold + RECT_TH_HYS. 0.3516[mA/code] (VCC regulator output current(IVCC), not depending on RIMON resistance) 9bit resolution in setting of RIVCC=1.2[kΩ], 2.4[kΩ], 4.8[kΩ] Initial value : 11 (11 x 0.3516=3.868[mA]) Register value is applied by 0x1F D[7]=1. D1 RECT_TH_HYS[1] 1 R/W D2 RECT_TH_HYS[2] 0 R/W D3 RECT_TH_HYS[3] 1 R/W D4 RECT_TH_HYS[4] 0 R/W D5 RECT_TH_HYS[5] 0 R/W D6 RECT_TH_HYS[6] 0 R/W D7 RECT_TH_UPLOAD 0 R/W 1 : Load current threshold registe r values (0x1B to 0x1F ) are applied. This register is reset after applying.

9.4 Address 0x18 to 0x1F

1. Register Map

Page 20 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x20 D0 WPT_T_TRNS 0 R/W Data transmission trigger of WPT commun ication 0 : Complete 1 : Start (This register is reset after transmission) D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x21 D0 WPT_T_HDR[0] 0 R/W Transmission data Header of WPT commun ication D1 WPT_T_HDR[1] 0 R/W D2 WPT_T_HDR[2] 0 R/W D3 WPT_T_HDR[3] 0 R/W D4 WPT_T_HDR[4] 0 R/W D5 WPT_T_HDR[5] 0 R/W D6 WPT_T_HDR[6] 0 R/W D7 WPT_T_HDR[7] 0 R/W 0x22 D0 WPT_T_MSG1[0] 0 R/W Transmission data Message1 of WPT commu nication D1 WPT_T_MSG1[1] 0 R/W D2 WPT_T_MSG1[2] 0 R/W D3 WPT_T_MSG1[3] 0 R/W D4 WPT_T_MSG1[4] 0 R/W D5 WPT_T_MSG1[5] 0 R/W D6 WPT_T_MSG1[6] 0 R/W D7 WPT_T_MSG1[7] 0 R/W 0x23 D0 WPT_T_MSG2[0] 0 R/W Transmission data Message2 of WPT commu nication D1 WPT_T_MSG2[1] 0 R/W D2 WPT_T_MSG2[2] 0 R/W D3 WPT_T_MSG2[3] 0 R/W D4 WPT_T_MSG2[4] 0 R/W D5 WPT_T_MSG2[5] 0 R/W D6 WPT_T_MSG2[6] 0 R/W D7 WPT_T_MSG2[7] 0 R/W 0x24 D0 WPT_R_HDR[0] 0 R Received data Header of WPT communicati on This register is overwritten by next received data of WPT communication even if this register is not read. D1 WPT_R_HDR[1] 0 R D2 WPT_R_HDR[2] 0 R D3 WPT_R_HDR[3] 0 R D4 WPT_R_HDR[4] 0 R D5 WPT_R_HDR[5] 0 R D6 WPT_R_HDR[6] 0 R D7 WPT_R_HDR[7] 0 R 0x25 D0 WPT_R_MSG1[0] 0 R Received data Message1 of WPT communicat ion This register is overwritten by next received data of WPT communication even if this register is not read. D1 WPT_R_MSG1[1] 0 R D2 WPT_R_MSG1[2] 0 R D3 WPT_R_MSG1[3] 0 R D4 WPT_R_MSG1[4] 0 R D5 WPT_R_MSG1[5] 0 R D6 WPT_R_MSG1[6] 0 R D7 WPT_R_MSG1[7] 0 R 0x26 D0 WPT_R_MSG2[0] 0 R Received data Message2 of WPT communicat ion This register is overwritten by next received data of WPT communication even if this register is not read. D1 WPT_R_MSG2[1] 0 R D2 WPT_R_MSG2[2] 0 R D3 WPT_R_MSG2[3] 0 R D4 WPT_R_MSG2[4] 0 R D5 WPT_R_MSG2[5] 0 R D6 WPT_R_MSG2[6] 0 R D7 WPT_R_MSG2[7] 0 R 0x27 D0 WPT_T_RATE[0] 1 R/W WPT communication data rate setting (Receiver to Transmitter communication) 0 : 125[bps] 1 : 250[bps] 2 : 500[bps] 3 : 1000[bps]D1 WPT_T_RATE[1] 0 R/W D2 WPT_R_DIFF_OLD[0] 1 R/W Assigning data point to calculate the rectified output voltage variation for WPT communication packet demodulation. 0:Previous data 1:Data 2 times before 2:Data 3 times before 3:Data 4 times before D3 WPT_R_DIFF_OLD[1] 1 R/W D4 WPT_R_DIFF_WAIT[0] 1 R/W Timing to acquire the rectifi ed output voltage variation for WPT communication packet demodulation. Recommended value 125bps : 7 250bps : - 500bps : - 1000bps :-D5 WPT_R_DIFF_WAIT[1] 1 R/W D6 WPT_R_DIFF_WAIT[2] 1 R/W D7 WPT_R_DIFF_WAIT[3] 0 R/W

9.5 Address 0x20 to 0x27

1. Register Map

Page 21 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x28 D0 WPT_R_DIFF_TH[1] 0 R/W Threshold to detect the rectifie d output voltage variation for WPT communication packet demodulation. 5.273[mV/code] (RECT pin voltage, 11bit resolution) { 000, WPT_RDIFF_TH[8:1], 0 } and 12bit differential value of RECT pin voltage are compared. Recommended value 125bps : 32(168.7[mV]) 250bps : - 500bps : - 1000bps : - D1 WPT_R_DIFF_TH[2] 0 R/W D2 WPT_R_DIFF_TH[3] 0 R/W D3 WPT_R_DIFF_TH[4] 0 R/W D4 WPT_R_DIFF_TH[5] 0 R/W D5 WPT_R_DIFF_TH[6] 1 R/W D6 WPT_R_DIFF_TH[7] 0 R/W D7 WPT_R_DIFF_TH[8] 0 R/W 0x29 D0 WPT_R_CNT_TH[0] 1 R/W Counter timing to detect data 1 /0 for WPT communication packet demodulation. Recommended value 125bps : 11 250bps : - 500bps : - 1000bps : -D1 WPT_R_CNT_TH[1] 1 R/W D2 WPT_R_CNT_TH[2] 0 R/W D3 WPT_R_CNT_TH[3] 1 R/W D4 WPT_R_CNT_TH[4] 0 R/W D5 WPT_R_CNT_TH[5] 0 R/W D6 WPT_R_CNT_TH[6] 0 R/W D7 WPT_R_CNT_TH[7] 0 R/W 0x2A D0 WPT_R_CNT_TH_1CYC[0] 0 R/W Counter timing to detect da ta presence/absence for WPT communication packet demodulation. Recommended value 125bps : 20 250bps : - 500bps : - 1000bps : -D1 WPT_R_CNT_TH_1CYC[1] 0 R/W D2 WPT_R_CNT_TH_1CYC[2] 1 R/W D3 WPT_R_CNT_TH_1CYC[3] 0 R/W D4 WPT_R_CNT_TH_1CYC[4] 1 R/W D5 WPT_R_CNT_TH_1CYC[5] 0 R/W D6 WPT_R_CNT_TH_1CYC[6] 0 R/W D7 WPT_R_CNT_TH_1CYC[7] 0 R/W 0x2B D0 0 R D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x2C D0 0 R D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x2D D0 0 R D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x2E D0 0 R D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x2F D0 INT_WPT_CM_RCV_MASK 0 R/W Notification setting of WPT data receiving (Tx to Rx) 0 : Notify 1 : Do not notify (flag is masked) D1 INT_CHG_STAT_CNG_MASK 0 R/W Notification setting of bat tery charge state transition 0 : Notify 1 : Do not notify (flag is masked) D2 INT_DD_OCP_DET_MASK 0 R/W Notification setting of DCDC overcurrent detection 0 : Notify 1 : Do not notify (flag is masked) D3 INT_VCCREG_CLDET_MASK 0 R/W Notification setting of VCC regulator current limit 0 : Notify 1 : Do not notify (flag is masked) D4 0 R D5 0 R D6 0 R D7 0 R

9.6 Address 0x28 to 0x2F

1. Register Map

Page 22 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x30 D0 INT_WPT_CM_RCV 0 R Interruption notification of WPT d ata receiving (Tx to Rx) 1 : Data is received (return 0 after register read) D1 INT_CHG_STAT_CNG 0 R Interruption notification of batt ery charge state transition 1 : State is transited (return 0 after register read) D2 INT_DD_OCP_DET 0 R Interruption notification of DCDC overcurrent detection 1 : Detected D3 INT_VCCREG_CLDET 0 R Interruption notification of VCC regulator current limit 1 : Current limiting D4 0 R D5 0 R D6 0 R D7 0 R 0x31 D0 MCTRL_STATE_MON[0] 0 R Operation mode 0,1 : Shut down mode 2 to 7 : Charge mode 1 8 : Charge mode 2 9 : Discharge mode D1 MCTRL_STATE_MON[1] 0 R D2 MCTRL_STATE_MON[2] 0 R D3 MCTRL_STATE_MON[3] 0 R D4 VCCREG_CLDET 0 R Notification of VCC regulator current limit 0 : Normal condition 1 : Current limiting D5 CHG_LDDET 0 R Notification that load current automatic d ividing function is operated 0 : OFF 1 : ON D6 BAT_ASSISTDET 0 R Notification that assist function by ba ttery is operated 0 : OFF 1 : ON D7 0 R 0x32 D0 CHG_STATE_MON[0] 0 R Battery charging status 0 : Initial 1 : Pre-charge 2 : Trickle charge 3 : Fast charge 4 : Charge complete judging 5 : Charge complete 6 : No battery 7 : Charge error 1 8 : Charge error 2 9 : Charge error 3 D1 CHG_STATE_MON[1] 0 R D2 CHG_STATE_MON[2] 0 R D3 CHG_STATE_MON[3] 0 R D4 THM_AREA[0] 0 R Charge control profile for battery te mperature 0 : No battery 1 : Charge pending in low temperature 2 : Low temperature low rate charge 3 : Suitable temperature charge 4 : High temperature low rate charge 5 : Charge pending in high temperature D5 THM_AREA[1] 0 R D6 THM_AREA[2] 0 R D7 0 R 0x33 D0 WPT_R_ERR 0 R WPT communication error 0 : Undetected 1 : Detected D1 I2C_WR_ERR 0 R 2-wire interface communication error 0 : Undetected 1 : Detected D2 RIMON_DET_ERR 0 R RIMON connected resistance value error 0 : Undetected 1 : Detected D3 0 R D4 DD_DDIN_OK 0 R DCDC converter UVLO detection 0 : Dete cted(DCDC stop) 1 : UVLO release(DCDC start) D5 DD_SYS_OK 0 R DCDC converter SYS voltage detection 0 : Low voltage condition 1 : Normal voltage condition (start up complete) D6 DD_OVP_DET 0 R DCDC converter overvoltage detection 0 : OVP release(DCDC start) 1 : Detected(DCDC stop) D7 DD_OCP_DET 0 R DCDC converter overcurrent detection 0 : Normal current 1 : Detected 0x34 D0 FGH_DET 0 R Battery low voltage detection H (First step ) 0 : Undetected 1 : Detected D1 FGL_DET 0 R Battery low voltage detection L (Second ste p) 0 : Undetected 1 : Detected D2 BUZ_MODE 0 R/W BUZ output setting 0 : Level output 1 : Pulse output D3 0 R D4 DSCP_DET 0 R Battery discharge short circuit current detect ion 0 : Undetected 1 : Detected D5 DOCP_DET 0 R Battery discharge overcurrent detection 0 : Undetected 1 : Detected D6 DOVP_DET 0 R Battery discharge overvoltage detection 0 : Undetected 1 : Detected D7 TJMAX_DET 0 R Maximum junction temperature detection 0 : Undetected 1 : Detected 0x35 D0 ADC_UPLOAD 0 R/W 1 : A/D converted results are fetched an d 0x36 to 0x3F registers are updated. (return 0 after update) D1 0 R D2 0 R D3 0 R D4 0 R D5 0 R D6 0 R D7 0 R 0x36 D0 ADC_RECTCLIPDET 0 R RECT pin voltage detection. RECT p in voltage is higher than ADC input voltage range. 0 : Undetected 1 : Detected D1 0 R D2 0 R D3 0 R D4 ADC_VRECT_I2C[0] 0 R A/D converted result of rectified voltage (RECT pin voltage) 2.637[mV/code] (RECT pin voltage, 12bit resolution)D5 ADC_VRECT_I2C[1] 0 R D6 ADC_VRECT_I2C[2] 0 R D7 ADC_VRECT_I2C[3] 0 R 0x37 D0 ADC_VRECT_I2C[4] 0 R D1 ADC_VRECT_I2C[5] 0 R D2 ADC_VRECT_I2C[6] 0 R D3 ADC_VRECT_I2C[7] 0 R D4 ADC_VRECT_I2C[8] 0 R D5 ADC_VRECT_I2C[9] 0 R D6 ADC_VRECT_I2C[10] 0 R D7 ADC_VRECT_I2C[11] 0 R

9.7 Address 0x30 to 0x37

1. Register Map

Page 23 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x38 D0 0 R D1 0 R D2 0 R D3 0 R D4 ADC_IVCC_I2C[0] 0 R A/D converted result of VCC regula tor output current (RIMON pin voltage) 0.6592[mV/code] (RIMON pin voltage, 12bit resolution) RIMON pin voltage is limited in 1.2V(Current limit function) (1.2[V]/0.6592[mV/code] = 1820 [code]) 43.94[uA/code] @ RIVCC=1.2[k Ω] (VCC regulator output current(IVCC), 12bit resolution) 21.97[uA/code] @ RIVCC=2.4[k Ω] (VCC regulator output current(IVCC), 12bit resolution) 10.98[uA/code] @ RIVCC=4.8[k Ω] (VCC regulator output current(IVCC), 12bit resolution) D5 ADC_IVCC_I2C[1] 0 R D6 ADC_IVCC_I2C[2] 0 R D7 ADC_IVCC_I2C[3] 0 R 0x39 D0 ADC_IVCC_I2C[4] 0 R D1 ADC_IVCC_I2C[5] 0 R D2 ADC_IVCC_I2C[6] 0 R D3 ADC_IVCC_I2C[7] 0 R D4 ADC_IVCC_I2C[8] 0 R D5 ADC_IVCC_I2C[9] 0 R D6 ADC_IVCC_I2C[10] 0 R D7 ADC_IVCC_I2C[11] 0 R 0x3A D0 0 R D1 0 R D2 0 R D3 0 R D4 ADC_VBAT_I2C[0] 0 R A/D converted result of battery vol tage (BAT pin voltage) 1.318[mV/code] (BAT pin voltage, 12bit resolution)D5 ADC_VBAT_I2C[1] 0 R D6 ADC_VBAT_I2C[2] 0 R D7 ADC_VBAT_I2C[3] 0 R 0x3B D0 ADC_VBAT_I2C[4] 0 R D1 ADC_VBAT_I2C[5] 0 R D2 ADC_VBAT_I2C[6] 0 R D3 ADC_VBAT_I2C[7] 0 R D4 ADC_VBAT_I2C[8] 0 R D5 ADC_VBAT_I2C[9] 0 R D6 ADC_VBAT_I2C[10] 0 R D7 ADC_VBAT_I2C[11] 0 R 0x3C D0 0 R D1 0 R D2 0 R D3 0 R D4 ADC_ICHG_I2C[0] 0 R A/D converted result of charging cur rent (RICHG pin voltage) 0.6592[mV/code] (RICHG pin voltage, 12bit resolution) RICHG pin voltage is limited in 1.2V(1C) (1.2[V]/0.6592[mV/code] = 1820 [code]) 9.417[uA/code] @ RICHG=5.6[k Ω] (charge current(ICHG), 12bit resolution) 1C=17.14[mA] 35.16[uA/code] @ RICHG=1.5[k Ω] (charge current(ICHG), 12bit resolution) 1C=64.00[mA] D5 ADC_ICHG_I2C[1] 0 R D6 ADC_ICHG_I2C[2] 0 R D7 ADC_ICHG_I2C[3] 0 R 0x3D D0 ADC_ICHG_I2C[4] 0 R D1 ADC_ICHG_I2C[5] 0 R D2 ADC_ICHG_I2C[6] 0 R D3 ADC_ICHG_I2C[7] 0 R D4 ADC_ICHG_I2C[8] 0 R D5 ADC_ICHG_I2C[9] 0 R D6 ADC_ICHG_I2C[10] 0 R D7 ADC_ICHG_I2C[11] 0 R 0x3E D0 0 R D1 0 R D2 0 R D3 0 R D4 ADC_VTHM_I2C[0] 0 R A/D converted result of battery tem perature (THM pin voltage) 0.6592[mV/code] (THM pin voltage, 12bit resolution) D5 ADC_VTHM_I2C[1] 0 R D6 ADC_VTHM_I2C[2] 0 R D7 ADC_VTHM_I2C[3] 0 R 0x3F D0 ADC_VTHM_I2C[4] 0 R D1 ADC_VTHM_I2C[5] 0 R D2 ADC_VTHM_I2C[6] 0 R D3 ADC_VTHM_I2C[7] 0 R D4 ADC_VTHM_I2C[8] 0 R D5 ADC_VTHM_I2C[9] 0 R D6 ADC_VTHM_I2C[10] 0 R D7 ADC_VTHM_I2C[11] 0 R

9.8 Address 0x38 to 0x3F

1. Register Map

Page 24 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 Address Bit No. Register Name Init R/W Description 0x40 D0 I2C_WRITE_EN 0 R/W Write enable to registers of 0x00 to 0x0F by 2-wire I/F. 0 : Write disable 1: Write enable D1 0 R/W D2 0 R/W D3 0 R/W D4 I2C_RSET[0] 0 R/W Pull up resistance setting for SDA, SCL I/O circuit.(Thisresistance does not mean the pull up resistance of bus line.) 0 : 250k Ω 1 : 500kΩ 2 : 1000kΩ 3 : 2000kΩD5 I2C_RSET[1] 0 R/W D6 Test Register 0 R/W Setting 0 only. Setting 1 is forbidden. D7 Test Register 0 R/W 0x41 to 0x6F Test registers ( Unavailable for user )

9.9 Address 0x40 to 0x6F

1. Register Map

Page 25 of 25 R19DS0094EJ0100 Rev.1.00 2017.02.28 10. Package Dimensions 10. Package Dimensions

Rev. Date 1.00 2017.02.28 - First Edition issued REVISION HISTORY RAA457100GBM Datasheet All marks and registered trademarks are the property of their respective owners.

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