RAA305350MGBM

RAA305350MGBM RENESAS | Alldatasheet

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Technical content

( 1 / 25 ) RAA305350MGBM General purpose 3CH Driver IC Rev.1.06 2021.2.17 R19DS0112EJ0106 Rev.1.06 RAA305350MGBM is general-purpose 3CH H-bridge driver IC .This is a small size single chip IC constituted by the control block built in 32 bits RISC microcomputer and DSP, and by the driver block built in hall signal processing circuit.

Applications

Smart phone, Tablet, Camera, Sensing and Actuator Control Driver Block [CH1/CH2/CH3] (1)Built-in 3 channels H-bridge drivers Composition : CH1, CH2, CH3 (2)Built-in 3 channels Hall signal processing circuits Composition : Constant Current Bias --- 3 channels Gain Amp --- 3 channels (with gain resistor) (3)Built-in 12bit-ADC with 6 channels input selector (4)Configurable for VCM/Piezo/SMA/BLDC motor drive (5)PWM/Linear drive (6)Other CH3（AF Control case）；Supports open/closed loop control Controller (1)Built-in 32bit RISC CPU (2)Built-in Code Flash ROM(48KB) (3)Built-in RAM(8KB) for program (4)Built-in DSP 2 channels (GREEN_DSP_V2) (5)Built-in SPI 2 channels (6)Built-in Timer (16bit) 4 channels (7)Built-in IIC serial interface 1 channel (8)Built-in General purpose I/O 8lines (with interruption function) (9)Clock frequency : Built-in PLL (x4, x6, x8, x12, x16) Others (1)Built in POR(power on reset), TSD(thermal shut down) (2)Built in Power save mode (3)Built in IS/AF Driver control synchronized signal from Image Sensor ( OIS case)

1 Over View

2 Features

(40pin 2.17mm x 3.60mm 0.4mm pitch square grid array) （t=0. 26±0.04mm） bottom view WLBGA

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 ABSOLUTE MAXIMUM RATING (Ta=25 degrees C) ITEM SYMBOL RATING UNIT NOTES Power dissipation Pd （1330） mW note1 (Ta=25 degrees C) Thermal derating Kθ （-13.3） mW/degrees C note1 (Ta=25 degrees C) Maximum junction temperature Tj 125 degrees C Storage temperature Tstg -40 to 125 degrees C Power supply 1 VDD 4.6 V note2 Power supply 2 VCC 4.6 V note2 Power supply 3 VM 6.5 V note2 Input voltage of terminals Vin -0.3 to VDD + 0.3 V note3 DC output current Iout +/- 600 mA note4 Peak output current Iop +/- 800 mA note5 pulse width<10ms,Duty<=20% Notes note1 : note2 : note3 : note4 : note5 : Glass epoxy board: 76mm×114mm×1.6mm 4layers board(Cu cover rate:1-layer 20%,2-layer 100%,3-layer 100%,4-layer 20%) Don't impress a power supply conversely in principle. Don't impress more than power supply voltage and below GND voltage in principle. Don’t exceed +/-200mA per channel. Don't exceed the specification of output current, when more than one CH use them, turning on at the same time. Notes The power consumption of this IC has the dominant electric power which each output transistor consumes. Output transistor power consumption formula (Output current)2 x Ron (ex.) (400mA)2 x 3.3 ohm=528mW When ambient air temperature is 25 degrees C or more, please install a heat sink with reference to the above figure if needed. To continue operating a long-time at high temperature impacts a product life. 0 20 40 60 80 140 1200 800 400 Operating temperature Ta(degrees C) 200 600 1000 1400 100 120 160 Pd (mW) （-13.3mW/ degrees C） （1330） （665） Power dissipation 1600

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 RECOMMENDED OPERATING CONDITIONS (Ta=25 degrees C) ITEM SYMBOL RATING UNIT NOTES Power supply 1 VDD 1.7 to 3.3 V Power supply 2 VCC 2.7 to 3.3 V Power supply 3 VM 2.7 to 3.3 V Linear drive mode Power supply 4 VM 2.7 to 5.5 V PWM drive mode RATED POWER SUPPLY VOLTAGE (Ta=25 degrees C) ITEM SYMBOL RATING UNIT NOTES Power supply 1 VDD 1.8 V Power supply 2 VCC 2.8 V Power supply 3 VM 2.8 V Linear / PWM drive mode Power supply 4 VM 5.0 V PWM drive mode OPERATING TEMPERATURE ITEM SYMBOL RATING UNIT NOTES Operating temperature Topr -30 to 85 degrees C note1 note1 : Flash write / erase : -10 to 50 degrees C

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 1 2 3 4 5 A SPI_MISO0 SPI_DAT0 GPIO11 GPIO10 RESET_N B SPI_SCK0 VDD REGM IMGHD EXCLK C SPI_CS1 SPI_CS0 TEST SWCLK SWDIO D SPI_DAT1 SPI_SCK1 MON (analog monitor) SDA SCL E HD1_OUT HA1_INN HA1_INP AD2 VSS F HD2_OUT HA2_INN HA2_INP HA3_INP VCC G HD3_OUT OUT2_B OUT1_B OUT3_A HA3_INN H PGND OUT2_A OUT1_A OUT3_B VM PIN LOCATION Bottom View Controller Power Supply GND Driver TopView Sensing circuit RENESAS TEST (Don’t Connect) 5 4 3 2 1 A RESET_N GPIO10 GPIO11 SPI_DAT0 SPI_MISO0 B EXCLK IMGHD REGM VDD SPI_SCK0 C SWDIO SWCLK TEST SPI_CS0 SPI_CS1 D SCL SDA MON (analog monitor) SPI_SCK1 SPI_DAT1 E VSS AD2 HA1_INP HA1_INN HD1_OUT F VCC HA3_INP HA2_INP HA2_INN HD2_OUT G HA3_INN OUT3_A OUT1_B OUT2_B HD3_OUT H VM OUT3_B OUT1_A OUT2_A PGND

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Pin Functions *1 Open *2 Connect to VSS *3 ‘Connect to VSS’or ‘Pin is Open, ,Pin enbled in PORTSEL register ,Switch to GPIO in PNMOD register ,Output Enable in GPIO0OE register and output data fixed to '0' in GPIO0DT register.' *4 An initial value is not influenced by the RESET_N terminal. *5 Pull-up can be turned off by register setting. *6 Pull-up can be turned on/off by register setting. Land IN/OUT Initial Address GPIO CPU INT DSP INT Power/GND Condition *4

1 F5 VCC Power supply for analog block and flash -

2 B2 VDD Power supply for I/O and digital block -

3 H5 VM Power supply for CH1,CH2,CH3 driver -

4 H1 PGND Power system GND -

5 E5 VSS Digital and analog GND -

6 H3 OUT1_A - - - OUT Hi-Z CH1 driver output A *1

7 G3 OUT1_B - - - OUT Hi-Z CH1 driver output B *1

8 H2 OUT2_A - - - OUT Hi-Z CH2 driver output A *1

9 G2 OUT2_B - - - OUT Hi-Z CH2 driver output B *1

10 G4 OUT3_A - - - OUT Hi-Z CH3 driver output A *1

11 H4 OUT3_B - - - OUT Hi-Z CH3 driver output B *1

12 D3 MON - - - OUT Hi-Z To Monitor Loop Gain *1

13 E1 HD1_OUT - - - OUT Hi-Z Hall CH1 constant current output *1

14 E3 HA1_INP - - - IN Hi-Z Hall amplifier CH1 non-inverting input

15 E2 HA1_INN - - - IN Hi-Z Hall amplifier CH1 inverting input

16 F1 HD2_OUT - - - OUT Hi-Z Hall CH2 constant current output *1

17 F3 HA2_INP - - - IN Hi-Z Hall amplifier CH2 non-inverting input

18 F2 HA2_INN - - - IN Hi-Z Hall amplifier CH2 inverting input

19 G1 HD3_OUT - - - OUT Hi-Z Hall CH3 constant current output *1

20 F4 HA3_INP - - - IN Hi-Z Hall amplifier CH3 non-inverting input

21 G5 HA3_INN - - - IN Hi-Z Hall amplifier CH3 inverting input

22 E4 AD2 - - - IN Hi-Z ADC input *2

23 A5 RESET_N - - - IN Hi-Z Reset -

24 D5 SCL GPIO00 INTIN0 INT IN0 IN/OUT Hi-Z SCL for I2C Interface / GPIO port GPIO00 / UART RXD00 /

CPU INTIN0 / DSP INT IN0 *3

25 D4 SDA GPIO01 - - IN/OUT Hi-Z SDA for I2C Interface / GPIO port GPIO01 / UART TXD00 *3

26 B1 SPI_SCK0 GPIO02 - - IN/OUT Hi-Z CLOCK input or output for SPI (SCK) / GPIO port GPIO02 *3

27 A2 SPI_DAT0 GPIO03 - - IN/OUT Hi-Z Data input or output for SPI (DAT) /

Data output for SPI (MOSI) / GPIO port GPIO03 *3

28 A1 SPI_MISO0 GPIO07 INTIN7 - IN/OUT Hi-Z Data input for SPI (MISO) / GPIO port GPIO07 /

CPU INTIN7 *3

29 C2 SPI_CS0 GPIO04 INTIN4 - IN/OUT Hi-Z Chip select input or output for SPI (CS) /

GPIO port GPIO04 / TAU TO0, TO1, TO2 / CPU INTIN4 *3

30 B5 EXCLK - - - IN Hi-Z External CLOCK input -

31 D2 SPI_SCK1 GPIO08 - - IN/OUT*6 Hi-Z CLOCK input for SPI (SCK) *3

32 D1 SPI_DAT1 GPIO09 - - IN/OUT*6 Hi-Z Data input or output for SPI (DAT) *3

33 C1 SPI_CS1 GPIO12 - - IN/OUT*6 Hi-Z Chip select input or output for SPI (CS) / GPIO port GPIO12 *3

34 C4 SWCLK GPIO05 INTIN5 - IN/OUT*6 Hi-Z

(Pull-up)*5 Clock input for Debugger / GPIO port GPIO05 / UART RXD00 / TAU TI2 / CPU INTIN5 *3

35 C5 SWDIO GPIO06 INTIN6 - IN/OUT*6 Hi-Z

(Pull-up)*5 Data input/output for Debugger / GPIO port GPIO06 / UART TXD00 / TAU TI1 / CPU INTIN6 *3

36 B4 IMGHD - INTIN3 INT IN3 IN*6 Hi-Z CPU INTIN3 / DSP INT IN3 (Image Sencor Sync signal) *2

37 A4 GPIO10 GPIO10 INTIN1 INT IN1 IN/OUT*6 Hi-Z GPIO port GPIO10 / TAU TO2 / CPU INTIN1 / DSP INT IN1 *3 38 A3 GPIO11 GPIO11 INTIN2 INT IN2 IN/OUT*6 Hi-Z GPIO port GPIO11 / TAU TO3 / CPU INTIN2 / DSP INT IN2 *3

39 C3 TEST - - IN Pull-up TEST for RENESAS *1

40 B3 REGM - - OUT - TEST for RENESAS *1

• - - - GND - - - - - Power supply - No. Pin Sub Function I/O Level Function Termination of unused pin

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 TOTAL BLOCK TSD Bias circuit HD1_OUT HA1_INP HA1_INN GREEN_DSP_V2 2SPI VSS SPI_CS1 SPI_SCK1 SPI_DAT1 SWCLK SWDIO SPI_SCK0 SPI_CS0 SPI_DAT0 SPI_MISO0 CLKC OUT1_A OUT1_B OUT2_A OUT2_B < CH1 > Hall amp 8bitDAC 2ch VM PGND EXCLK 12bit ADC RAM DATA (4KB) CODE (4KB) RAM 8KB SCL SDA RESET_N 6CH_SW Flash 48KB CPU Bus DSP Bus 1 HD2_OUT HA2_INP HA2_INN VCC VDD TEST AD2 TEMP MON REGM UART(SAU) TAU ROM 4KB FLC PLL WDT < CH2 > Hall amp 8bitDAC 2ch ANACNT SYSCON CH1,2 CNT PWM / Linear 2chIIC 1.3V OUT3_A MUXHall ch2 Hall ch3 OUT3_B Hall ch1 CH3 driver IMGHD HA3_INN HA3_INP CH1 driver CH2 driver (master) (slave) SLAVE SPI (from VSYNC) GPIO10 Reg HD3_OUT < CH3 > Hall amp 8bitDAC 2ch ARM CPU PORT GREEN_DSP_V2 RAM DATA (4KB) CODE (4KB) DSP SMEM DSP Bus 2 CH3 CNT PWM / Linear GPIO11 PORT 40Pin

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 POWER SUPPLY SEQUENCE Notes at the time of power-on *1 Please apply VDD at the same time or before VCC. *2 Please apply VCC at the same time or before VM. (Please apply all powers with a stable voltage.) Notes at the time of power-down *1 Please power down VCC and VM at the same time. *2 Please power down VDD at the same time or after power VCC. Notes at the time of FW Initialization *3 The periods of FW Initialization is depend on FW. CPU initialize the registers of IIC during the periods of FW Initialization. RESET_N VM(*2) 0ms or more Setup time before RESET_N de -assert 100us or more Setup time before RESET_N de -assert 100us or more 0ms or more 0ms or more Available CLK min 0ms EXCLK FW Initialize (*3) Capable periods of communication After Initialization was completed, The communication is enabled and IIC is Fast mode (Not Fast mode+). When reset is canceled, there is the necessity that EXCLK is carrying out operational stability. IIC/SPI VDD(*1) VCC(*1*2) 0ms or more 0ms or more Setup time before RESET_N de -assert 100us or more until 40ms

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Consumption current Electrical characteristics (POR threshold) If not specified, Ta=25degreeC min typ max PVO Check on VCC >Vcore 1.30 1.55 1.67 V LVI Check on VCC level 2.35 - - V *1 POR Check on VDD 1.30 1.60 1.68 V Note *1: These are reference , not guaranteed. LVI detect level POR detect level Remarks UVP (Under Voltage Protect) PVO detect level Item Symbol Condition Standard Value Unit If not specified, VDD=1.8V,VCC=VM=2.8V Ta=25degreeC min typ max IVDln EXCLK=27MHz PLL=162MHz,System Clock=32.4MHz Linear mode - 10 - mA *1 IVCln All output function without ｌoad.HA* DAC setting code 80h,HB*DAC setting code 00h,BTL_IS*DAC & AF_BTL setting Default. - 4.7 7.05 mA IVMpw All output function without load.HA* DAC setting code 80h,HB*DAC setting code 00h PWM mode - 1.2 1.8 mA *2 IVMln All output function without load.HA* DAC setting code 80h,HB*DAC setting code 00h,BTL_IS*DAC & AF_BTL setting Default. - 7.6 11.4 mA Note *1: These are reference data. These are depend on FW processing. Note *2: These are reference,not guaranteed. VM current VDD current VCC current VM current Item Symbol Condition Standard Value Unit Remarks

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 RAA305350MGBM (Driver Block)

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Example for circuit of Driver Block (Analog & Driver) A D BIAS TEMP VSS VCC VM PGND AD2 HA2_INN HA2_INP HD2_OUT HA1_INN HA1_INP HD1_OUT D/A TSD １０DAC_2 １０DAC_1 １０DAC_3 MON VDD REGM REG EXCLK LPF LPF OFFSET Control CURRENT Control D/A D/A CURRENT Control D/A OFFSET Control OUT1_A OUT1_B PWM/Linear OUT2_A OUT2_B PWM/Linear To monitor loop gain OUT3_B OUT3_A PWM/Linear HA3_INP HD3_OUT D/A CURRENT Control D/A LPF OFFSET Control IMGHD SWCLK SWDIO RESET_N TEST SPI_SCK0 SPI_CS0 SPI_DAT0 SPI_MISO0 SCL SDA ActAct Act 10uF 10uF HA3_INN 10uF GPIO10 SPI_CS1 SPI_SCK1 SPI_DAT1 GPIO11 ASIC BLOCK

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Electrical specification (Analog block) Ta=25 degrees C If not specified, VCC=VM=2.8V, VDD=1.8V, Ta=25 degrees C min typ max RES ― 12 ― bit DRLAD ― ― 080h CODE DRHAD F7Fh ― ― CODE VINLAD ― 0 ― V VINHAD ― VCC ― V TCAD 3.375 ― ― us FCLK ― ― 16 MHｚ VOLMN ― ― 0.10 V VOHMN VCC-0.1 ― ― V GHS -12 0 12 % BWHA ― 10 ― kHz *1 RES ― 8 ― bit DNLDA8 -1 ― 1 LSB *1 INLDA8 (Reference value) (Reference value) LSB *1 DRLDA8 ― ― 15h CODE DRHDA8 EBh ― ― CODE VOZSDA8 ― ― 0.1 V VOFSDA8 VCC-0.1 ― ― V TCDA8 ― ― (Reference value) us *1 IIBMINIC ― ― 10 uA IIBMAXIC1 1.0 ― ― mA IIBMAXIC2 2.0 ― ― mA DRLIDA8 ― ― 11h CODE DRHIDA8 D6h ― ― CODE Item Symbol Condition Standard Value Unit Remarks 12bit ADC Resolution 684uV/LSB @VCC=2.8V Liniearity minimum code about 0.1V Liniearity maximum code about VCC-0.1V Zero scale input voltage Full scale input voltage Conversion time clock frequency Hall Amplifier Differential Gain accuracy x20, x30, x40, x80 x120, x160, x100, x150, x7 Lo output voltage Hi output voltage Output LPF cut-off frequency -3dB Hall Amplifier offset adjusting 8bit DAC Resolution 10.9mV/LSB @VCC=2.8V Differential Nonlinearity guaranteed monotonic, IO=0mA DAC setting code DRLDA8～DRHDA8 Integral Nonlinearity IO=0mA DAC setting code DRLDA8～DRHDA8 Liniearity minimum code about 0.25V IO=0mA Liniearity maximum code about 2.75V IO=0mA Zero scale output voltage DAC setting code 00h, IO=0mA Full scale output voltage DAC setting code FFh, IO=0mA Output response time DRLDA8～DRHDA8 Constant Current Amplifier FET Tr minimum current DAC setting code 00h VIN=0V, ISET[1:0]=01b Internal DAC linearity minimum code RL=0.75kohm, Vb=0, ISET[1:0]=01b FET Tr maximum current 1 DAC setting code D6h VIN=VCC-0.5V, ISET[1:0]=00b FET Tr maximum current 2 DAC setting code D6h VIN=VCC-0.5V, ISET[1:0]=01b Internal DAC linearity maximum code RL=0.75kohm, Vb=0, ISET[1:0]=01b

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 If not specified, VCC=VM=2.8V, VDD=1.8V, Ta=25 degrees C min typ max RESIS - 10 - bit DRLIDA10IS ― ― C0h CODE *1 DRHIDA10IS 340h ― ― CODE *1 Note *1: These are reference , not guaranteed. If not specified, VCC=VM=2.8V, VDD=1.8V, Ta=25 degrees C min typ max RONIS - 3.6 5.8 ohm *1 TON1 - 0.3 0.45 μｓ TOFF1 - 0.12 0.24 μｓ Tr1 - 0.13 0.52 μｓ Tf1 - 0.05 0.10 μｓ TON2 - 0.26 0.39 μｓ TOFF2 - 0.12 0.24 μｓ Tr2 - 0.11 0.44 μｓ Tf2 - 0.05 0.10 μｓ TON3 - 0.24 0.36 μｓ TOFF3 - 0.12 0.24 μｓ Tr3 - 0.08 0.32 μｓ Tf3 - 0.05 0.10 μｓ Note *1: These are reference , not guaranteed. Fall downtime 3 From 90% to 10%, Io=100mA IS slew rate setting=101b Turn on time 3 Threshold 50%, Io=100mA IS slew rate setting=101b Turn off time 3 Threshold 50%, Io=100mA IS slew rate setting=101b Rise up time 3 From 10% to 90%, Io=100mA IS slew rate setting=101b Turn off time 2 Threshold 50%, Io=100mA IS slew rate setting=110b Rise up time 2 From 10% to 90%, Io=100mA IS slew rate setting=110b Fall downtime 2 From 90% to 10%, Io=100mA IS slew rate setting=110b Threshold 50%, Io=100mA IS slew rate setting=000b Rise up time 1 From 10% to 90%, Io=100mA IS slew rate setting=000b Fall downtime 1 From 90% to 10%, Io=100mA IS slew rate setting=000b Turn on time 2 Threshold 50%, Io=100mA IS slew rate setting=110b Remarks PWM driver (CH1,2,3) On resistance IS Io=100mA, VM=2.8V Total of top and bottom resistance Turn on time 1 Threshold 50%, Io=100mA IS slew rate setting=000b Turn off time 1 Item Symbol Condition Standard Value Unit IS internal DAC liniearity maximum code RL=28ohm IS internal DAC liniearity minimum code RL=28ohm IS DAC Resolution Remarks Linear Driver (CH1,2,3) Item Symbol Condition Standard Value Unit Electrical specification (Driver block) Ta=25 degrees C

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 RAA305350MGBM (Controller Block)

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 BBR:Bus BRidge TAU:Timer Array Unit Controller Block outline Block diagram Block diagram is shown in below. Figure 1.1 RAA305350MGBM Block diagram SPI BBR CPU Bus Interface SWCLK INT (37ch) CPU Kernel (ARM Cortex-M0+) Serial Wrire Debug TAU(4ch) IICA ADC12 CPU Bus Peripheral Bus 32 32 RAA305350MGBMPORT RAM (8KB) FLASH ROM (Code 48KB) CH1/CH2 Driver AMP DAC8CH3 Driver 1.3V REG POR/LVD System Control RAM IF FLASH IF ANACNT Driver Block PLL CLKC WDT PORT Controller Block PORT SWDIO debugger UART(SAU) ROM IF ROM (4KB) 32 16 16 161616 SLAVE SPI GREEN _DSP_V2 RAM 8KB DSP SMEM CH3 CNT CH1/CH2 CNT GREEN _DSP_V2 RAM 8KB

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Pin connection (1/2) SCL SDA SPI_SCLK0 PORT IIC CPU INT DSP INT SPI SPI_SDAT0 SPI_MISO0 SPI_CS0 SPI_SCLK1 SLAVE SPI SPI_DAT1 SPI_CS1 INTIN0 INTIN7 INTIN4 GPIO00 GPIO01 GPIO02 GPIO03 GPIO07 GPIO04 GPIO08 GPIO09 GPIO12 INT IN0

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Pin connection (2/2) SWCLK SWDIO GPIO10 PORT CPU Debug CPU INT DSP INT GPIO11 IMGHD INTIN5 INT IN1 INT IN2 INT IN3 GPIO05 GPIO06 GPIO10 GPIO11 INTIN6 INTIN1 INTIN2 INTIN3

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 controller peripheral I/O Features shown in Table (1) Controller Features Function block Interrupt controller (INT) · Internal Interrupts : 37 sources

• External interrupts : 8 sources
• ICUIN input sense : Edge sense (rise edge, fall edge, both edges)
• Priority : Programable TIMER ARRAY UNIT(TAU) · Channels : 4ch
• Count bit : 16 bits counter, down counting
• Timer scale : fCLK/20 to fCLK/215 General purpose I/O & Pin control · GPIO number of lines : 12 lines (GPIO) (PORT) · I/O pins : Can be set to each I/O pin using the corresponds input and output control register bits. : Can be select to each I/O from GPIO and peripheral module Pin mode register 0/1/2/3.
• I/O pins control : Each pins can be changed GPIO and other peripheral functions with setting the operation mode register.
• I/O pins pull-up : Enables and disables the pull-up resistors. Serial Peripheral Interface · Number of channels : 1 channel (SPI) · Character length : 8 bits
• Order of transfer : MSB first or LSB first
• Shift clock : Internal or external shift clock
• Internal shift clock source : fCLK/20 to fCLK/215
• Baud rate count : 2-256
• Transmit interrupt factor : Transmit buffer empty or Transmit end
• Receive error detection : Overrun
• Chip Select : Chip select signal
• DSP register access : Registers are accessible from CPU Slave Serial Peripheral Interface · Number of channels : 1 channel (SLAVE SPI) · Character length : 8 bits
• Order of transfer : MSB first
• Shift clock : external shift clock
• Transmit interrupt factor : Transmit end
• Receive/Send buffer : 1Byte address buffer(Receive) and 6 Byte data buffer(Send)
• Chip Select : Chip select signal
• DSP register access : Registers are accessible from CPU

Features

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 controller peripheral I/O Features shown in Table (2)

• Channels : 1 channel
• Character length : 7/8/9 -bit length can be selected
• Transfer order : MSB and LSB first can be selected
• Stop bit length : 1 or 2 bit can be selected
• Parity check : Can be enabled or disabled
• Attribute of parity check : Even or Odd parity can be selected
• Internal clock source : Dividable range = : fCLK/20 to fCLK/215
• Baud rate counter : Maximum 2-256
• Transmit interrupt factor : Transmit buffer empty or Transmit end can be selected. Error interrupt also.
• Error detection : Framing error, Parity error, Overrun error.
• Clock source : External Input (EXCLK)
• SYSTEM/DSP clocks : 32.4MHz max
• PWM clocks : 162MHz max
• Standby Function : SLEEP, DEEP-SLEEP
• PLL clock(=PWM clocks) : MAX : 162MHz
• PLL control : PLL can be stop.
• OIS module clock control : OIS module clock control can be stop
• Channels : 1 channel
• Clock frequency : Standard mode (fastest transfer rate: 100 kbps) : Fast mode (fastest transfer rate: 400 kbps) : Fast mode+ (fastest transfer rate: 1 Mbps)
• Transmit interrupt factor : Transfer end interrupt
• Error detection : Overrun error Parity error (ACK error)
• Image stabilizer drive function : 2 channel PWM or Linear (H-bridge)
• DSP register access : Registers are accessible through CPU Bus.
• Auto focus drive function : 1 channel PWM or Linear (H-bridge)
• DSP register access : Registers are accessible through CPU Bus.

(AFCNT) CH1,CH2 Control Multi Master & Slave SERIAL INTERFACE IICA (IICA) (OISCNT) Function block Clock /PLL/ System control Universal asynchronous Receiver Transmitter (UART)

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06

• Channels : 2 channels
• Arithmetic operation : Multiplication Signed 32 bits * Signed 32 bits = Signed 32 bits Multiplication results (64 bits) can be shifted right any number of bits : Addition/ Substruct Signed 32 bits + Signed 32 bits = Signed 32 bits Signed 32 bits - Signed 32 bits = Signed 32 bits Internally calculated with 33bits precision. : Limit calculation Upper-/lower-limits can be set. : Capable to generate an interrupt to the CPU at program halt.
• Interrupt requests : When program halts: Executes the STOP, break, and undefined instructions.
• Memory Capacity : 16byte (GREEN_DSP_V2 1->GREEN_DSP_V2 2) 16byte (GREEN_DSP_V2 2->GREEN_DSP_V2 1)
• Interrupt requests : GREEN_DSP_V2 1->GREEN_DSP_V2 2 (Software interrupt) GREEN_DSP_V2 2->GREEN_DSP_V2 1
• AMP,DAC8 control : Control register
• DSP register access : Registers are accessible through CPU Bus.
• Resolution : 12bits
• Channels : 6ch
• Conversion mode : Single mode, Scan mode
• DSP register access : Registers are accessible through CPU Bus. Function block Shared Memory (DSP SMEM)

(GREEN_DSP_V2 1, 2) Analog Control (ANACNT) 12bit ADC Control (ADC12) controller peripheral I/O Features shown in Table (3)

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Electrical characteristics (Controller block) Ta=25 degrees C Min Typ Max 'H' output voltage VOH IOH=-2mA VDD*0.8 - VDD V note1 'L' output voltage VOL IOL=2mA 0 VDD*0.2 V note1 'H' input current IIH VI=VDD - - 1 uA note2 'L' input current IIL VI=0V - - -1 uA note2 Pull-up resistance Rup 10 - 200 Kohm note3 'H' input voltage VIH VDD*0.7 - VDD V - 'L' input voltage VIL 0 - VDD*0.3 V - Unit RemarksSymbolItem Conditions Limit If not specified VDD=1.8V, VCC=VM=2.8V, Ta=25 degrees C note1. correspondence terminal: SCL, SDA, SPI_SCK0, SPI_DAT0, SPI_MISO0, SPI_CS0, SPI_SCK1, SPI_DAT1, SPI_CS1, SWCLK, SWDIO, GPIO10, GPIO11 note2. in condition that pull-up resistance is not connected. (The built-in pull-up resistor is disabled by the F/W.) note3. correspondence terminal: SPI_SCK1, SPI_DAT1, SPI_CS1, SWCLK, SWDIO, GPIO10, GPIO11 DC characteristics

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Electrical characteristics (Controller block) Ta=25 degrees C AC characteristics (1) EXTERNAL CLOCK (CLOCK) If not specified, VDD=1.8V VCC=VM=2.8V Ta=25 degrees C Items Symbol Conditions Limit Unit RemarksMin Max Input Frequency fclk - 6 29 MHz - Input 'H' pulse width twh ＞ 0.5VDD 14 - ns - Input 'L' pulse width twl ＜ 0.5VDD 14 - ns - Input rise time Tr VDD voltage 10% to 90% - 2 ns - Input fall time Tf VDD voltage 10% to 90% - 2 ns - Cycle-to-cycle period jitter tjit(CC) - - 2 % - Period Jitter tjit(per) - -4 4 % -

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Outline drawing

<A1115171•A1116348• A1115173> RAA305350MGBM R19DS0112EJ0106 Rev.1.06

Revision History

Description

Rev 1.06 16th.Mar.2021 - New

( 24 / 25 ) RAA305350MGBM R19DS0112EJ0106 Rev.1.06 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1.Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti- static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2.Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power i s supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3.Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4.Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5.Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6.Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7.Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8.Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product.

( 25 / 25 ) RAA305350MGBM R19DS0112EJ0106 Rev.1.06 Notice 1.Descriptions of circuits, software and other related information in this document are provided only to illustrate the opera tion of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software , and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2.Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims in volving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technic al information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application exampl es. 3.No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property r ights of Renesas Electronics or others. 4.You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export, manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, i f required. 5.You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesa s Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or r everse engineering. 6.Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. T he intended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. “Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; h ome electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large -scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data s heet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pos e a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; e tc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 7.No semiconductor product is absolutely secure. Notwithstanding any security measures or features that may be implemented in Renesas Electronics hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or sec urity breach, including but not limited to any unauthorized access to or use of a Renesas Electronics product or a system that uses a Renesas Electronics product. RENESAS ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (“Vulnerability Issues”). RENESAS ELECTRONICS DISCLAIMS ANY AND ALL RESPONSIBILITY OR LIABILITY ARISING FROM OR RELATED TO ANY VULNERABILITY ISSUES. FURTHERMORE, TO THE EXTENT PERMITTED BY APPLICABLE LAW, RENESAS ELECTRONICS DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, WITH RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. 8.When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 9.Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconducto r products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless de signated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics docu ment, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfu nction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunct ion prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer softwa re alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you . 10.Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compat ibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that re gulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in complia nce with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11.Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose man ufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export contr ol laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 12.It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in thi s document. 13.This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written con sent of Renesas Electronics. 14.Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this do cument or Renesas Electronics products. (Note1)“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note2)“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (Rev.5.0-1 October 2020) Corporate Headquarters Contact information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up -to- date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/. Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.